1 1.1 jmcneill // SPDX-License-Identifier: GPL-2.0 2 1.1 jmcneill // Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu (a] quantatw.com 3 1.1 jmcneill 4 1.1 jmcneill /dts-v1/; 5 1.1 jmcneill #include "nuvoton-npcm730.dtsi" 6 1.1 jmcneill #include "nuvoton-npcm730-gsj-gpio.dtsi" 7 1.1 jmcneill 8 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 9 1.1 jmcneill 10 1.1 jmcneill / { 11 1.1 jmcneill model = "Quanta GSJ Board (Device Tree v12)"; 12 1.1 jmcneill compatible = "nuvoton,npcm750"; 13 1.1 jmcneill 14 1.1 jmcneill aliases { 15 1.1 jmcneill ethernet1 = &gmac0; 16 1.1 jmcneill serial3 = &serial3; 17 1.1 jmcneill i2c1 = &i2c1; 18 1.1 jmcneill i2c2 = &i2c2; 19 1.1 jmcneill i2c3 = &i2c3; 20 1.1 jmcneill i2c4 = &i2c4; 21 1.1 jmcneill i2c8 = &i2c8; 22 1.1 jmcneill i2c9 = &i2c9; 23 1.1 jmcneill i2c10 = &i2c10; 24 1.1 jmcneill i2c11 = &i2c11; 25 1.1 jmcneill i2c12 = &i2c12; 26 1.1 jmcneill i2c15 = &i2c15; 27 1.1 jmcneill fiu0 = &fiu0; 28 1.1 jmcneill }; 29 1.1 jmcneill 30 1.1 jmcneill chosen { 31 1.1 jmcneill stdout-path = &serial3; 32 1.1 jmcneill }; 33 1.1 jmcneill 34 1.1 jmcneill memory { 35 1.1 jmcneill reg = <0 0x40000000>; 36 1.1 jmcneill }; 37 1.1 jmcneill 38 1.1 jmcneill leds { 39 1.1 jmcneill compatible = "gpio-leds"; 40 1.1 jmcneill 41 1.1 jmcneill led-bmc-live { 42 1.1 jmcneill gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; 43 1.1 jmcneill linux,default-trigger = "heartbeat"; 44 1.1 jmcneill }; 45 1.1 jmcneill 46 1.1 jmcneill LED_U2_0_LOCATE { 47 1.1 jmcneill gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 48 1.1 jmcneill default-state = "off"; 49 1.1 jmcneill }; 50 1.1 jmcneill 51 1.1 jmcneill LED_U2_1_LOCATE { 52 1.1 jmcneill gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; 53 1.1 jmcneill default-state = "off"; 54 1.1 jmcneill }; 55 1.1 jmcneill 56 1.1 jmcneill LED_U2_2_LOCATE { 57 1.1 jmcneill gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; 58 1.1 jmcneill default-state = "off"; 59 1.1 jmcneill }; 60 1.1 jmcneill 61 1.1 jmcneill LED_U2_3_LOCATE { 62 1.1 jmcneill gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 63 1.1 jmcneill default-state = "off"; 64 1.1 jmcneill }; 65 1.1 jmcneill 66 1.1 jmcneill LED_U2_4_LOCATE { 67 1.1 jmcneill gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; 68 1.1 jmcneill default-state = "off"; 69 1.1 jmcneill }; 70 1.1 jmcneill 71 1.1 jmcneill LED_U2_5_LOCATE { 72 1.1 jmcneill gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; 73 1.1 jmcneill default-state = "off"; 74 1.1 jmcneill }; 75 1.1 jmcneill 76 1.1 jmcneill LED_BMC_TRAY_PWRGD { 77 1.1 jmcneill gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; 78 1.1 jmcneill default-state = "off"; 79 1.1 jmcneill }; 80 1.1 jmcneill 81 1.1 jmcneill LED_U2_7_FAULT { 82 1.1 jmcneill gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; 83 1.1 jmcneill default-state = "off"; 84 1.1 jmcneill }; 85 1.1 jmcneill 86 1.1 jmcneill LED_U2_6_LOCATE { 87 1.1 jmcneill gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; 88 1.1 jmcneill default-state = "off"; 89 1.1 jmcneill }; 90 1.1 jmcneill 91 1.1 jmcneill LED_U2_7_LOCATE { 92 1.1 jmcneill gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; 93 1.1 jmcneill default-state = "off"; 94 1.1 jmcneill }; 95 1.1 jmcneill 96 1.1 jmcneill LED_U2_0_FAULT { 97 1.1 jmcneill gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 98 1.1 jmcneill default-state = "off"; 99 1.1 jmcneill }; 100 1.1 jmcneill 101 1.1 jmcneill LED_U2_1_FAULT { 102 1.1 jmcneill gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 103 1.1 jmcneill default-state = "off"; 104 1.1 jmcneill }; 105 1.1 jmcneill 106 1.1 jmcneill LED_U2_2_FAULT { 107 1.1 jmcneill gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; 108 1.1 jmcneill default-state = "off"; 109 1.1 jmcneill }; 110 1.1 jmcneill 111 1.1 jmcneill LED_U2_3_FAULT { 112 1.1 jmcneill gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; 113 1.1 jmcneill default-state = "off"; 114 1.1 jmcneill }; 115 1.1 jmcneill 116 1.1 jmcneill LED_U2_4_FAULT { 117 1.1 jmcneill gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; 118 1.1 jmcneill default-state = "off"; 119 1.1 jmcneill }; 120 1.1 jmcneill 121 1.1 jmcneill LED_U2_5_FAULT { 122 1.1 jmcneill gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; 123 1.1 jmcneill default-state = "off"; 124 1.1 jmcneill }; 125 1.1 jmcneill 126 1.1 jmcneill LED_U2_6_FAULT { 127 1.1 jmcneill gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; 128 1.1 jmcneill default-state = "off"; 129 1.1 jmcneill }; 130 1.1 jmcneill }; 131 1.1 jmcneill }; 132 1.1 jmcneill 133 1.1 jmcneill &fiu0 { 134 1.1 jmcneill pinctrl-names = "default"; 135 1.1 jmcneill pinctrl-0 = <&spi0cs1_pins>; 136 1.1 jmcneill status = "okay"; 137 1.1 jmcneill 138 1.1 jmcneill spi-nor@0 { 139 1.1 jmcneill compatible = "jedec,spi-nor"; 140 1.1 jmcneill #address-cells = <1>; 141 1.1 jmcneill #size-cells = <1>; 142 1.1 jmcneill reg = <0>; 143 1.1 jmcneill spi-rx-bus-width = <2>; 144 1.1 jmcneill 145 1.1 jmcneill partitions@80000000 { 146 1.1 jmcneill compatible = "fixed-partitions"; 147 1.1 jmcneill #address-cells = <1>; 148 1.1 jmcneill #size-cells = <1>; 149 1.1 jmcneill bmc@0{ 150 1.1 jmcneill label = "bmc"; 151 1.1 jmcneill reg = <0x000000 0x2000000>; 152 1.1 jmcneill }; 153 1.1 jmcneill u-boot@0 { 154 1.1 jmcneill label = "u-boot"; 155 1.1 jmcneill reg = <0x0000000 0x80000>; 156 1.1 jmcneill read-only; 157 1.1 jmcneill }; 158 1.1 jmcneill u-boot-env@100000{ 159 1.1 jmcneill label = "u-boot-env"; 160 1.1 jmcneill reg = <0x00100000 0x40000>; 161 1.1 jmcneill }; 162 1.1 jmcneill kernel@200000 { 163 1.1 jmcneill label = "kernel"; 164 1.1 jmcneill reg = <0x0200000 0x600000>; 165 1.1 jmcneill }; 166 1.1 jmcneill rofs@800000 { 167 1.1 jmcneill label = "rofs"; 168 1.1 jmcneill reg = <0x800000 0x1400000>; 169 1.1 jmcneill }; 170 1.1 jmcneill rwfs@1c00000 { 171 1.1 jmcneill label = "rwfs"; 172 1.1 jmcneill reg = <0x1c00000 0x300000>; 173 1.1 jmcneill }; 174 1.1 jmcneill reserved@1f00000 { 175 1.1 jmcneill label = "reserved"; 176 1.1 jmcneill reg = <0x1f00000 0x100000>; 177 1.1 jmcneill }; 178 1.1 jmcneill }; 179 1.1 jmcneill }; 180 1.1 jmcneill }; 181 1.1 jmcneill 182 1.1 jmcneill &gmac0 { 183 1.1 jmcneill phy-mode = "rgmii-id"; 184 1.1 jmcneill status = "okay"; 185 1.1 jmcneill }; 186 1.1 jmcneill 187 1.1 jmcneill &ehci1 { 188 1.1 jmcneill status = "okay"; 189 1.1 jmcneill }; 190 1.1 jmcneill 191 1.1 jmcneill &watchdog1 { 192 1.1 jmcneill status = "okay"; 193 1.1 jmcneill }; 194 1.1 jmcneill 195 1.1 jmcneill &rng { 196 1.1 jmcneill status = "okay"; 197 1.1 jmcneill }; 198 1.1 jmcneill 199 1.1 jmcneill &serial0 { 200 1.1 jmcneill status = "okay"; 201 1.1 jmcneill }; 202 1.1 jmcneill 203 1.1 jmcneill &serial1 { 204 1.1 jmcneill status = "okay"; 205 1.1 jmcneill }; 206 1.1 jmcneill 207 1.1 jmcneill &serial2 { 208 1.1 jmcneill status = "okay"; 209 1.1 jmcneill }; 210 1.1 jmcneill 211 1.1 jmcneill &serial3 { 212 1.1 jmcneill status = "okay"; 213 1.1 jmcneill }; 214 1.1 jmcneill 215 1.1 jmcneill &adc { 216 1.1 jmcneill status = "okay"; 217 1.1 jmcneill }; 218 1.1 jmcneill 219 1.1 jmcneill &i2c1 { 220 1.1 jmcneill status = "okay"; 221 1.1 jmcneill 222 1.1 jmcneill lm75@5c { 223 1.1 jmcneill compatible = "maxim,max31725"; 224 1.1 jmcneill reg = <0x5c>; 225 1.1 jmcneill status = "okay"; 226 1.1 jmcneill }; 227 1.1 jmcneill }; 228 1.1 jmcneill 229 1.1 jmcneill &i2c2 { 230 1.1 jmcneill status = "okay"; 231 1.1 jmcneill 232 1.1 jmcneill lm75@5c { 233 1.1 jmcneill compatible = "maxim,max31725"; 234 1.1 jmcneill reg = <0x5c>; 235 1.1 jmcneill status = "okay"; 236 1.1 jmcneill }; 237 1.1 jmcneill }; 238 1.1 jmcneill 239 1.1 jmcneill &i2c3 { 240 1.1 jmcneill status = "okay"; 241 1.1 jmcneill 242 1.1 jmcneill lm75@5c { 243 1.1 jmcneill compatible = "maxim,max31725"; 244 1.1 jmcneill reg = <0x5c>; 245 1.1 jmcneill }; 246 1.1 jmcneill }; 247 1.1 jmcneill 248 1.1 jmcneill &i2c4 { 249 1.1 jmcneill status = "okay"; 250 1.1 jmcneill 251 1.1 jmcneill lm75@5c { 252 1.1 jmcneill compatible = "maxim,max31725"; 253 1.1 jmcneill reg = <0x5c>; 254 1.1 jmcneill }; 255 1.1 jmcneill }; 256 1.1 jmcneill 257 1.1 jmcneill &i2c8 { 258 1.1 jmcneill status = "okay"; 259 1.1 jmcneill }; 260 1.1 jmcneill 261 1.1 jmcneill &i2c9 { 262 1.1 jmcneill status = "okay"; 263 1.1 jmcneill 264 1.1 jmcneill eeprom@55 { 265 1.1 jmcneill compatible = "atmel,24c64"; 266 1.1 jmcneill reg = <0x55>; 267 1.1 jmcneill }; 268 1.1 jmcneill }; 269 1.1 jmcneill 270 1.1 jmcneill &i2c10 { 271 1.1 jmcneill status = "okay"; 272 1.1 jmcneill 273 1.1 jmcneill eeprom@55 { 274 1.1 jmcneill compatible = "atmel,24c64"; 275 1.1 jmcneill reg = <0x55>; 276 1.1 jmcneill }; 277 1.1 jmcneill }; 278 1.1 jmcneill 279 1.1 jmcneill &i2c11 { 280 1.1 jmcneill status = "okay"; 281 1.1 jmcneill 282 1.1 jmcneill /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */ 283 1.1 jmcneill power-brick@36 { 284 1.1 jmcneill compatible = "delta,dps800"; 285 1.1 jmcneill reg = <0x36>; 286 1.1 jmcneill }; 287 1.1 jmcneill 288 1.1 jmcneill hotswap@15 { 289 1.1 jmcneill compatible = "ti,lm5066i"; 290 1.1 jmcneill reg = <0x15>; 291 1.1 jmcneill }; 292 1.1 jmcneill }; 293 1.1 jmcneill 294 1.1 jmcneill &i2c12 { 295 1.1 jmcneill status = "okay"; 296 1.1 jmcneill 297 1.1 jmcneill ucd90160@6b { 298 1.1 jmcneill compatible = "ti,ucd90160"; 299 1.1 jmcneill reg = <0x6b>; 300 1.1 jmcneill }; 301 1.1 jmcneill }; 302 1.1 jmcneill 303 1.1 jmcneill &i2c15 { 304 1.1 jmcneill status = "okay"; 305 1.1 jmcneill 306 1.1 jmcneill i2c-switch@75 { 307 1.1 jmcneill compatible = "nxp,pca9548"; 308 1.1 jmcneill #address-cells = <1>; 309 1.1 jmcneill #size-cells = <0>; 310 1.1 jmcneill reg = <0x75>; 311 1.1 jmcneill i2c-mux-idle-disconnect; 312 1.1 jmcneill 313 1.1 jmcneill i2c_u20: i2c@0 { 314 1.1 jmcneill #address-cells = <1>; 315 1.1 jmcneill #size-cells = <0>; 316 1.1 jmcneill reg = <0>; 317 1.1 jmcneill }; 318 1.1 jmcneill 319 1.1 jmcneill i2c_u21: i2c@1 { 320 1.1 jmcneill #address-cells = <1>; 321 1.1 jmcneill #size-cells = <0>; 322 1.1 jmcneill reg = <1>; 323 1.1 jmcneill }; 324 1.1 jmcneill 325 1.1 jmcneill i2c_u22: i2c@2 { 326 1.1 jmcneill #address-cells = <1>; 327 1.1 jmcneill #size-cells = <0>; 328 1.1 jmcneill reg = <2>; 329 1.1 jmcneill }; 330 1.1 jmcneill 331 1.1 jmcneill i2c_u23: i2c@3 { 332 1.1 jmcneill #address-cells = <1>; 333 1.1 jmcneill #size-cells = <0>; 334 1.1 jmcneill reg = <3>; 335 1.1 jmcneill }; 336 1.1 jmcneill 337 1.1 jmcneill i2c_u24: i2c@4 { 338 1.1 jmcneill #address-cells = <1>; 339 1.1 jmcneill #size-cells = <0>; 340 1.1 jmcneill reg = <4>; 341 1.1 jmcneill }; 342 1.1 jmcneill 343 1.1 jmcneill i2c_u25: i2c@5 { 344 1.1 jmcneill #address-cells = <1>; 345 1.1 jmcneill #size-cells = <0>; 346 1.1 jmcneill reg = <5>; 347 1.1 jmcneill }; 348 1.1 jmcneill 349 1.1 jmcneill i2c_u26: i2c@6 { 350 1.1 jmcneill #address-cells = <1>; 351 1.1 jmcneill #size-cells = <0>; 352 1.1 jmcneill reg = <6>; 353 1.1 jmcneill }; 354 1.1 jmcneill 355 1.1 jmcneill i2c_u27: i2c@7 { 356 1.1 jmcneill #address-cells = <1>; 357 1.1 jmcneill #size-cells = <0>; 358 1.1 jmcneill reg = <7>; 359 1.1 jmcneill }; 360 1.1 jmcneill }; 361 1.1 jmcneill }; 362 1.1 jmcneill 363 1.1 jmcneill &pwm_fan { 364 1.1 jmcneill pinctrl-names = "default"; 365 1.1 jmcneill pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins 366 1.1 jmcneill &fanin0_pins &fanin1_pins 367 1.1 jmcneill &fanin2_pins &fanin3_pins 368 1.1 jmcneill &fanin4_pins &fanin5_pins>; 369 1.1 jmcneill status = "okay"; 370 1.1 jmcneill 371 1.1 jmcneill fan@0 { 372 1.1 jmcneill reg = <0x00>; 373 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x00 0x01>; 374 1.1 jmcneill cooling-levels = <127 255>; 375 1.1 jmcneill }; 376 1.1 jmcneill 377 1.1 jmcneill fan@1 { 378 1.1 jmcneill reg = <0x01>; 379 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x02 0x03>; 380 1.1 jmcneill cooling-levels = /bits/ 8 <127 255>; 381 1.1 jmcneill }; 382 1.1 jmcneill 383 1.1 jmcneill fan@2 { 384 1.1 jmcneill reg = <0x02>; 385 1.1 jmcneill fan-tach-ch = /bits/ 8 <0x04 0x05>; 386 1.1 jmcneill cooling-levels = /bits/ 8 <127 255>; 387 1.1 jmcneill }; 388 1.1 jmcneill }; 389 1.1 jmcneill 390 1.1 jmcneill &pinctrl { 391 1.1 jmcneill pinctrl-names = "default"; 392 1.1 jmcneill pinctrl-0 = < 393 1.1 jmcneill /* GPI pins*/ 394 1.1 jmcneill &gpio8_pins 395 1.1 jmcneill &gpio9_pins 396 1.1 jmcneill &gpio12_pins 397 1.1 jmcneill &gpio13_pins 398 1.1 jmcneill &gpio14_pins 399 1.1 jmcneill &gpio60_pins 400 1.1 jmcneill &gpio83_pins 401 1.1 jmcneill &gpio91_pins 402 1.1 jmcneill &gpio92_pins 403 1.1 jmcneill &gpio95_pins 404 1.1 jmcneill &gpio136_pins 405 1.1 jmcneill &gpio137_pins 406 1.1 jmcneill &gpio141_pins 407 1.1 jmcneill &gpio144_pins 408 1.1 jmcneill &gpio145_pins 409 1.1 jmcneill &gpio146_pins 410 1.1 jmcneill &gpio147_pins 411 1.1 jmcneill &gpio148_pins 412 1.1 jmcneill &gpio149_pins 413 1.1 jmcneill &gpio150_pins 414 1.1 jmcneill &gpio151_pins 415 1.1 jmcneill &gpio152_pins 416 1.1 jmcneill &gpio153_pins 417 1.1 jmcneill &gpio154_pins 418 1.1 jmcneill &gpio155_pins 419 1.1 jmcneill &gpio156_pins 420 1.1 jmcneill &gpio157_pins 421 1.1 jmcneill &gpio158_pins 422 1.1 jmcneill &gpio159_pins 423 1.1 jmcneill &gpio161_pins 424 1.1 jmcneill &gpio162_pins 425 1.1 jmcneill &gpio163_pins 426 1.1 jmcneill &gpio164_pins 427 1.1 jmcneill &gpio165_pins 428 1.1 jmcneill &gpio166_pins 429 1.1 jmcneill &gpio167_pins 430 1.1 jmcneill &gpio168_pins 431 1.1 jmcneill &gpio169_pins 432 1.1 jmcneill &gpio170_pins 433 1.1 jmcneill &gpio177_pins 434 1.1 jmcneill &gpio191_pins 435 1.1 jmcneill &gpio192_pins 436 1.1 jmcneill &gpio203_pins 437 1.1 jmcneill /* GPO pins*/ 438 1.1 jmcneill &gpio0pp_pins 439 1.1 jmcneill &gpio1pp_pins 440 1.1 jmcneill &gpio2pp_pins 441 1.1 jmcneill &gpio3pp_pins 442 1.1 jmcneill &gpio4pp_pins 443 1.1 jmcneill &gpio5pp_pins 444 1.1 jmcneill &gpio6pp_pins 445 1.1 jmcneill &gpio7pp_pins 446 1.1 jmcneill &gpio10pp_pins 447 1.1 jmcneill &gpio11pp_pins 448 1.1 jmcneill &gpio15od_pins 449 1.1 jmcneill &gpio17pp_pins 450 1.1 jmcneill &gpio18pp_pins 451 1.1 jmcneill &gpio19pp_pins 452 1.1 jmcneill &gpio24pp_pins 453 1.1 jmcneill &gpio25pp_pins 454 1.1 jmcneill &gpio37od_pins 455 1.1 jmcneill &gpio59pp_pins 456 1.1 jmcneill &gpio72od_pins 457 1.1 jmcneill &gpio73od_pins 458 1.1 jmcneill &gpio74od_pins 459 1.1 jmcneill &gpio75od_pins 460 1.1 jmcneill &gpio76od_pins 461 1.1 jmcneill &gpio77od_pins 462 1.1 jmcneill &gpio78od_pins 463 1.1 jmcneill &gpio79od_pins 464 1.1 jmcneill &gpio84pp_pins 465 1.1 jmcneill &gpio85pp_pins 466 1.1 jmcneill &gpio86pp_pins 467 1.1 jmcneill &gpio87pp_pins 468 1.1 jmcneill &gpio88pp_pins 469 1.1 jmcneill &gpio89pp_pins 470 1.1 jmcneill &gpio90pp_pins 471 1.1 jmcneill &gpio93pp_pins 472 1.1 jmcneill &gpio94pp_pins 473 1.1 jmcneill &gpio125pp_pins 474 1.1 jmcneill &gpio126od_pins 475 1.1 jmcneill &gpio127od_pins 476 1.1 jmcneill &gpio142od_pins 477 1.1 jmcneill &gpio143ol_pins 478 1.1 jmcneill &gpio175od_pins 479 1.1 jmcneill &gpio176od_pins 480 1.1 jmcneill &gpio190od_pins 481 1.1 jmcneill &gpio194pp_pins 482 1.1 jmcneill &gpio195od_pins 483 1.1 jmcneill &gpio196od_pins 484 1.1 jmcneill &gpio197od_pins 485 1.1 jmcneill &gpio198od_pins 486 1.1 jmcneill &gpio199od_pins 487 1.1 jmcneill &gpio200pp_pins 488 1.1 jmcneill &gpio202od_pins 489 1.1 jmcneill >; 490 1.1 jmcneill }; 491