1 1.1.1.3 skrll // SPDX-License-Identifier: GPL-2.0-only 2 1.1 jmcneill /* 3 1.1.1.4 jmcneill * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 4 1.1 jmcneill */ 5 1.1 jmcneill /dts-v1/; 6 1.1 jmcneill 7 1.1 jmcneill #include "omap34xx.dtsi" 8 1.1 jmcneill #include "omap3-evm-common.dtsi" 9 1.1.1.2 jmcneill #include "omap3-evm-processor-common.dtsi" 10 1.1 jmcneill 11 1.1 jmcneill / { 12 1.1 jmcneill model = "TI OMAP35XX EVM (TMDSEVM3530)"; 13 1.1.1.2 jmcneill compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; 14 1.1.1.2 jmcneill }; 15 1.1.1.2 jmcneill 16 1.1.1.2 jmcneill &omap3_pmx_core2 { 17 1.1.1.2 jmcneill pinctrl-names = "default"; 18 1.1.1.2 jmcneill pinctrl-0 = <&hsusb2_2_pins>; 19 1.1.1.2 jmcneill 20 1.1.1.2 jmcneill ehci_phy_pins: pinmux_ehci_phy_pins { 21 1.1.1.2 jmcneill pinctrl-single,pins = < 22 1.1.1.2 jmcneill 23 1.1.1.2 jmcneill /* EHCI PHY reset GPIO etk_d7.gpio_21 */ 24 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) 25 1.1.1.2 jmcneill 26 1.1.1.2 jmcneill /* EHCI VBUS etk_d8.gpio_22 */ 27 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) 28 1.1.1.2 jmcneill >; 29 1.1.1.2 jmcneill }; 30 1.1.1.2 jmcneill 31 1.1.1.2 jmcneill /* Used by OHCI and EHCI. OHCI won't work without external phy */ 32 1.1.1.2 jmcneill hsusb2_2_pins: pinmux_hsusb2_2_pins { 33 1.1.1.2 jmcneill pinctrl-single,pins = < 34 1.1.1.2 jmcneill 35 1.1.1.2 jmcneill /* etk_d10.hsusb2_clk */ 36 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) 37 1.1.1.2 jmcneill 38 1.1.1.2 jmcneill /* etk_d11.hsusb2_stp */ 39 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) 40 1.1.1.2 jmcneill 41 1.1.1.2 jmcneill /* etk_d12.hsusb2_dir */ 42 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) 43 1.1.1.2 jmcneill 44 1.1.1.2 jmcneill /* etk_d13.hsusb2_nxt */ 45 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) 46 1.1.1.2 jmcneill 47 1.1.1.2 jmcneill /* etk_d14.hsusb2_data0 */ 48 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) 49 1.1.1.2 jmcneill 50 1.1.1.2 jmcneill /* etk_d15.hsusb2_data1 */ 51 1.1.1.2 jmcneill OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) 52 1.1.1.2 jmcneill >; 53 1.1.1.2 jmcneill }; 54 1.1.1.2 jmcneill }; 55 1.1.1.2 jmcneill 56 1.1.1.2 jmcneill &gpmc { 57 1.1.1.2 jmcneill nand@0,0 { 58 1.1.1.2 jmcneill compatible = "ti,omap2-nand"; 59 1.1.1.2 jmcneill reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 60 1.1.1.2 jmcneill interrupt-parent = <&gpmc>; 61 1.1.1.2 jmcneill interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 62 1.1.1.2 jmcneill <1 IRQ_TYPE_NONE>; /* termcount */ 63 1.1.1.2 jmcneill linux,mtd-name= "micron,mt29f2g16abdhc"; 64 1.1.1.2 jmcneill nand-bus-width = <16>; 65 1.1.1.2 jmcneill gpmc,device-width = <2>; 66 1.1.1.2 jmcneill ti,nand-ecc-opt = "bch8"; 67 1.1.1.2 jmcneill 68 1.1.1.2 jmcneill gpmc,sync-clk-ps = <0>; 69 1.1.1.2 jmcneill gpmc,cs-on-ns = <0>; 70 1.1.1.2 jmcneill gpmc,cs-rd-off-ns = <44>; 71 1.1.1.2 jmcneill gpmc,cs-wr-off-ns = <44>; 72 1.1.1.2 jmcneill gpmc,adv-on-ns = <6>; 73 1.1.1.2 jmcneill gpmc,adv-rd-off-ns = <34>; 74 1.1.1.2 jmcneill gpmc,adv-wr-off-ns = <44>; 75 1.1.1.2 jmcneill gpmc,we-off-ns = <40>; 76 1.1.1.2 jmcneill gpmc,oe-off-ns = <54>; 77 1.1.1.2 jmcneill gpmc,access-ns = <64>; 78 1.1.1.2 jmcneill gpmc,rd-cycle-ns = <82>; 79 1.1.1.2 jmcneill gpmc,wr-cycle-ns = <82>; 80 1.1.1.2 jmcneill gpmc,wr-access-ns = <40>; 81 1.1.1.2 jmcneill gpmc,wr-data-mux-bus-ns = <0>; 82 1.1 jmcneill 83 1.1.1.2 jmcneill #address-cells = <1>; 84 1.1.1.2 jmcneill #size-cells = <1>; 85 1.1 jmcneill }; 86 1.1 jmcneill }; 87
Indexes created Wed Oct 01 19:09:53 GMT 2025