1 1.1.1.3 skrll // SPDX-License-Identifier: GPL-2.0-only 2 1.1 jmcneill /* 3 1.1 jmcneill * Common Device Tree Source for IGEPv2 4 1.1 jmcneill * 5 1.1.1.4 jmcneill * Copyright (C) 2014 Javier Martinez Canillas <javier (a] dowhile0.org> 6 1.1 jmcneill * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo (a] gmail.com> 7 1.1 jmcneill */ 8 1.1 jmcneill 9 1.1 jmcneill #include "omap3-igep.dtsi" 10 1.1 jmcneill #include "omap-gpmc-smsc9221.dtsi" 11 1.1 jmcneill 12 1.1 jmcneill / { 13 1.1 jmcneill 14 1.1 jmcneill leds { 15 1.1 jmcneill pinctrl-names = "default"; 16 1.1 jmcneill pinctrl-0 = <&leds_pins>; 17 1.1 jmcneill compatible = "gpio-leds"; 18 1.1 jmcneill 19 1.1 jmcneill boot { 20 1.1 jmcneill label = "omap3:green:boot"; 21 1.1 jmcneill gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 22 1.1 jmcneill default-state = "on"; 23 1.1 jmcneill }; 24 1.1 jmcneill 25 1.1 jmcneill user0 { 26 1.1 jmcneill label = "omap3:red:user0"; 27 1.1 jmcneill gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; 28 1.1 jmcneill default-state = "off"; 29 1.1 jmcneill }; 30 1.1 jmcneill 31 1.1 jmcneill user1 { 32 1.1 jmcneill label = "omap3:red:user1"; 33 1.1 jmcneill gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 34 1.1 jmcneill default-state = "off"; 35 1.1 jmcneill }; 36 1.1 jmcneill 37 1.1 jmcneill user2 { 38 1.1 jmcneill label = "omap3:green:user1"; 39 1.1 jmcneill gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; 40 1.1 jmcneill }; 41 1.1 jmcneill }; 42 1.1 jmcneill 43 1.1 jmcneill /* HS USB Port 1 Power */ 44 1.1 jmcneill hsusb1_power: hsusb1_power_reg { 45 1.1 jmcneill compatible = "regulator-fixed"; 46 1.1 jmcneill regulator-name = "hsusb1_vbus"; 47 1.1 jmcneill regulator-min-microvolt = <3300000>; 48 1.1 jmcneill regulator-max-microvolt = <3300000>; 49 1.1 jmcneill gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ 50 1.1 jmcneill startup-delay-us = <70000>; 51 1.1 jmcneill }; 52 1.1 jmcneill 53 1.1 jmcneill /* HS USB Host PHY on PORT 1 */ 54 1.1 jmcneill hsusb1_phy: hsusb1_phy { 55 1.1 jmcneill compatible = "usb-nop-xceiv"; 56 1.1 jmcneill reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ 57 1.1 jmcneill vcc-supply = <&hsusb1_power>; 58 1.1.1.2 jmcneill #phy-cells = <0>; 59 1.1 jmcneill }; 60 1.1 jmcneill 61 1.1 jmcneill tfp410: encoder { 62 1.1 jmcneill compatible = "ti,tfp410"; 63 1.1 jmcneill powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ 64 1.1 jmcneill 65 1.1 jmcneill ports { 66 1.1 jmcneill #address-cells = <1>; 67 1.1 jmcneill #size-cells = <0>; 68 1.1 jmcneill 69 1.1 jmcneill port@0 { 70 1.1 jmcneill reg = <0>; 71 1.1 jmcneill 72 1.1 jmcneill tfp410_in: endpoint { 73 1.1 jmcneill remote-endpoint = <&dpi_out>; 74 1.1 jmcneill }; 75 1.1 jmcneill }; 76 1.1 jmcneill 77 1.1 jmcneill port@1 { 78 1.1 jmcneill reg = <1>; 79 1.1 jmcneill 80 1.1 jmcneill tfp410_out: endpoint { 81 1.1 jmcneill remote-endpoint = <&dvi_connector_in>; 82 1.1 jmcneill }; 83 1.1 jmcneill }; 84 1.1 jmcneill }; 85 1.1 jmcneill }; 86 1.1 jmcneill 87 1.1 jmcneill dvi0: connector { 88 1.1 jmcneill compatible = "dvi-connector"; 89 1.1 jmcneill label = "dvi"; 90 1.1 jmcneill 91 1.1 jmcneill digital; 92 1.1 jmcneill 93 1.1 jmcneill ddc-i2c-bus = <&i2c3>; 94 1.1 jmcneill 95 1.1 jmcneill port { 96 1.1 jmcneill dvi_connector_in: endpoint { 97 1.1 jmcneill remote-endpoint = <&tfp410_out>; 98 1.1 jmcneill }; 99 1.1 jmcneill }; 100 1.1 jmcneill }; 101 1.1 jmcneill }; 102 1.1 jmcneill 103 1.1 jmcneill &omap3_pmx_core { 104 1.1 jmcneill pinctrl-names = "default"; 105 1.1 jmcneill pinctrl-0 = < 106 1.1 jmcneill &tfp410_pins 107 1.1 jmcneill &dss_dpi_pins 108 1.1 jmcneill >; 109 1.1 jmcneill 110 1.1 jmcneill tfp410_pins: pinmux_tfp410_pins { 111 1.1 jmcneill pinctrl-single,pins = < 112 1.1 jmcneill OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 113 1.1 jmcneill >; 114 1.1 jmcneill }; 115 1.1 jmcneill 116 1.1 jmcneill dss_dpi_pins: pinmux_dss_dpi_pins { 117 1.1 jmcneill pinctrl-single,pins = < 118 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 119 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 120 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 121 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 122 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 123 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 124 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 125 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 126 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 127 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 128 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 129 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 130 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 131 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 132 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 133 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 134 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 135 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 136 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 137 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 138 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 139 1.1 jmcneill OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 140 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 141 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 142 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 143 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 144 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 145 1.1 jmcneill OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 146 1.1 jmcneill >; 147 1.1 jmcneill }; 148 1.1 jmcneill 149 1.1 jmcneill uart2_pins: pinmux_uart2_pins { 150 1.1 jmcneill pinctrl-single,pins = < 151 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ 152 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ 153 1.1 jmcneill OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 154 1.1 jmcneill OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 155 1.1 jmcneill >; 156 1.1 jmcneill }; 157 1.1 jmcneill 158 1.1 jmcneill smsc9221_pins: pinmux_smsc9221_pins { 159 1.1 jmcneill pinctrl-single,pins = < 160 1.1 jmcneill OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 161 1.1 jmcneill >; 162 1.1 jmcneill }; 163 1.1 jmcneill }; 164 1.1 jmcneill 165 1.1 jmcneill &omap3_pmx_core2 { 166 1.1 jmcneill pinctrl-names = "default"; 167 1.1 jmcneill pinctrl-0 = < 168 1.1 jmcneill &hsusbb1_pins 169 1.1 jmcneill >; 170 1.1 jmcneill 171 1.1 jmcneill hsusbb1_pins: pinmux_hsusbb1_pins { 172 1.1 jmcneill pinctrl-single,pins = < 173 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ 174 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ 175 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ 176 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ 177 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ 178 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ 179 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ 180 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ 181 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ 182 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ 183 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ 184 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ 185 1.1 jmcneill >; 186 1.1 jmcneill }; 187 1.1 jmcneill 188 1.1 jmcneill leds_pins: pinmux_leds_pins { 189 1.1 jmcneill pinctrl-single,pins = < 190 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ 191 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ 192 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ 193 1.1 jmcneill >; 194 1.1 jmcneill }; 195 1.1 jmcneill 196 1.1 jmcneill mmc1_wp_pins: pinmux_mmc1_cd_pins { 197 1.1 jmcneill pinctrl-single,pins = < 198 1.1 jmcneill OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ 199 1.1 jmcneill >; 200 1.1 jmcneill }; 201 1.1 jmcneill }; 202 1.1 jmcneill 203 1.1 jmcneill &i2c3 { 204 1.1 jmcneill clock-frequency = <100000>; 205 1.1 jmcneill 206 1.1 jmcneill /* 207 1.1 jmcneill * Display monitor features are burnt in the EEPROM 208 1.1 jmcneill * as EDID data. 209 1.1 jmcneill */ 210 1.1 jmcneill eeprom@50 { 211 1.1 jmcneill compatible = "ti,eeprom"; 212 1.1 jmcneill reg = <0x50>; 213 1.1 jmcneill }; 214 1.1 jmcneill }; 215 1.1 jmcneill 216 1.1 jmcneill &gpmc { 217 1.1 jmcneill ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ 218 1.1 jmcneill <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ 219 1.1 jmcneill 220 1.1 jmcneill ethernet@gpmc { 221 1.1 jmcneill pinctrl-names = "default"; 222 1.1 jmcneill pinctrl-0 = <&smsc9221_pins>; 223 1.1 jmcneill reg = <5 0 0xff>; 224 1.1 jmcneill interrupt-parent = <&gpio6>; 225 1.1 jmcneill interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 226 1.1 jmcneill }; 227 1.1 jmcneill }; 228 1.1 jmcneill 229 1.1 jmcneill &uart2 { 230 1.1 jmcneill pinctrl-names = "default"; 231 1.1 jmcneill pinctrl-0 = <&uart2_pins>; 232 1.1 jmcneill }; 233 1.1 jmcneill 234 1.1 jmcneill &usbhshost { 235 1.1 jmcneill port1-mode = "ehci-phy"; 236 1.1 jmcneill }; 237 1.1 jmcneill 238 1.1 jmcneill &usbhsehci { 239 1.1 jmcneill phys = <&hsusb1_phy>; 240 1.1 jmcneill }; 241 1.1 jmcneill 242 1.1 jmcneill &vpll2 { 243 1.1 jmcneill /* Needed for DSS */ 244 1.1 jmcneill regulator-name = "vdds_dsi"; 245 1.1 jmcneill }; 246 1.1 jmcneill 247 1.1 jmcneill &dss { 248 1.1.1.4 jmcneill status = "okay"; 249 1.1 jmcneill 250 1.1 jmcneill port { 251 1.1 jmcneill dpi_out: endpoint { 252 1.1 jmcneill remote-endpoint = <&tfp410_in>; 253 1.1 jmcneill data-lines = <24>; 254 1.1 jmcneill }; 255 1.1 jmcneill }; 256 1.1 jmcneill }; 257 1.1 jmcneill 258 1.1 jmcneill &mmc1 { 259 1.1 jmcneill pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; 260 1.1 jmcneill wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ 261 1.1 jmcneill }; 262