1 1.1 skrll // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 1.1 skrll /* 3 1.1 skrll * Google Veyron Tiger Rev 0+ board device tree source 4 1.1 skrll * 5 1.1 skrll * Copyright 2016 Google, Inc 6 1.1 skrll */ 7 1.1 skrll 8 1.1 skrll /dts-v1/; 9 1.1 skrll #include "rk3288-veyron-fievel.dts" 10 1.1 skrll #include "rk3288-veyron-edp.dtsi" 11 1.1 skrll 12 1.1 skrll / { 13 1.1 skrll model = "Google Tiger"; 14 1.1 skrll compatible = "google,veyron-tiger-rev8", "google,veyron-tiger-rev7", 15 1.1 skrll "google,veyron-tiger-rev6", "google,veyron-tiger-rev5", 16 1.1 skrll "google,veyron-tiger-rev4", "google,veyron-tiger-rev3", 17 1.1 skrll "google,veyron-tiger-rev2", "google,veyron-tiger-rev1", 18 1.1 skrll "google,veyron-tiger-rev0", "google,veyron-tiger", 19 1.1 skrll "google,veyron", "rockchip,rk3288"; 20 1.1 skrll 21 1.1 skrll /delete-node/ vcc18-lcd; 22 1.1 skrll }; 23 1.1 skrll 24 1.1 skrll &backlight { 25 1.1 skrll /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ 26 1.1.1.2 jmcneill brightness-levels = <3 255>; 27 1.1 skrll num-interpolated-steps = <252>; 28 1.1 skrll }; 29 1.1 skrll 30 1.1 skrll &backlight_regulator { 31 1.1 skrll vin-supply = <&vccsys>; 32 1.1 skrll }; 33 1.1 skrll 34 1.1 skrll &i2c3 { 35 1.1 skrll status = "okay"; 36 1.1 skrll 37 1.1 skrll clock-frequency = <400000>; 38 1.1 skrll i2c-scl-falling-time-ns = <50>; 39 1.1 skrll i2c-scl-rising-time-ns = <300>; 40 1.1 skrll 41 1.1 skrll touchscreen@10 { 42 1.1 skrll compatible = "elan,ekth3500"; 43 1.1 skrll reg = <0x10>; 44 1.1 skrll interrupt-parent = <&gpio2>; 45 1.1 skrll interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>; 46 1.1 skrll pinctrl-names = "default"; 47 1.1 skrll pinctrl-0 = <&touch_int &touch_rst>; 48 1.1 skrll reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; 49 1.1 skrll vcc33-supply = <&vcc33_io>; 50 1.1 skrll vccio-supply = <&vcc33_io>; 51 1.1 skrll wakeup-source; 52 1.1 skrll }; 53 1.1 skrll }; 54 1.1 skrll 55 1.1 skrll &panel { 56 1.1.1.2 jmcneill compatible = "auo,b101ean01"; 57 1.1 skrll 58 1.1 skrll /delete-node/ panel-timing; 59 1.1 skrll 60 1.1 skrll panel-timing { 61 1.1 skrll clock-frequency = <66666667>; 62 1.1 skrll hactive = <1280>; 63 1.1 skrll hfront-porch = <18>; 64 1.1 skrll hback-porch = <21>; 65 1.1 skrll hsync-len = <32>; 66 1.1 skrll vactive = <800>; 67 1.1 skrll vfront-porch = <4>; 68 1.1 skrll vback-porch = <8>; 69 1.1 skrll vsync-len = <18>; 70 1.1 skrll }; 71 1.1 skrll }; 72 1.1 skrll 73 1.1 skrll &pinctrl { 74 1.1 skrll lcd { 75 1.1 skrll /delete-node/ avdd-1v8-disp-en; 76 1.1 skrll }; 77 1.1 skrll 78 1.1 skrll touchscreen { 79 1.1 skrll touch_int: touch-int { 80 1.1 skrll rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 81 1.1 skrll }; 82 1.1 skrll 83 1.1 skrll touch_rst: touch-rst { 84 1.1 skrll rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 85 1.1 skrll }; 86 1.1 skrll }; 87 1.1 skrll }; 88