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rv1108.dtsi revision 1.1.1.3 
      1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2 
      3 #include <dt-bindings/gpio/gpio.h>
      4 #include <dt-bindings/interrupt-controller/irq.h>
      5 #include <dt-bindings/interrupt-controller/arm-gic.h>
      6 #include <dt-bindings/clock/rv1108-cru.h>
      7 #include <dt-bindings/pinctrl/rockchip.h>
      8 #include <dt-bindings/thermal/thermal.h>
      9 / {
     10 	#address-cells = <1>;
     11 	#size-cells = <1>;
     12 
     13 	compatible = "rockchip,rv1108";
     14 
     15 	interrupt-parent = <&gic>;
     16 
     17 	aliases {
     18 		i2c0 = &i2c0;
     19 		i2c1 = &i2c1;
     20 		i2c2 = &i2c2;
     21 		i2c3 = &i2c3;
     22 		serial0 = &uart0;
     23 		serial1 = &uart1;
     24 		serial2 = &uart2;
     25 	};
     26 
     27 	cpus {
     28 		#address-cells = <1>;
     29 		#size-cells = <0>;
     30 
     31 		cpu0: cpu@f00 {
     32 			device_type = "cpu";
     33 			compatible = "arm,cortex-a7";
     34 			reg = <0xf00>;
     35 			clocks = <&cru ARMCLK>;
     36 			#cooling-cells = <2>; /* min followed by max */
     37 			dynamic-power-coefficient = <75>;
     38 			operating-points-v2 = <&cpu_opp_table>;
     39 		};
     40 	};
     41 
     42 	cpu_opp_table: opp_table {
     43 		compatible = "operating-points-v2";
     44 
     45 		opp-408000000 {
     46 			opp-hz = /bits/ 64 <408000000>;
     47 			opp-microvolt = <975000>;
     48 			clock-latency-ns = <40000>;
     49 		};
     50 		opp-600000000 {
     51 			opp-hz = /bits/ 64 <600000000>;
     52 			opp-microvolt = <975000>;
     53 			clock-latency-ns = <40000>;
     54 		};
     55 		opp-816000000 {
     56 			opp-hz = /bits/ 64 <816000000>;
     57 			opp-microvolt = <1025000>;
     58 			clock-latency-ns = <40000>;
     59 		};
     60 		opp-1008000000 {
     61 			opp-hz = /bits/ 64 <1008000000>;
     62 			opp-microvolt = <1150000>;
     63 			clock-latency-ns = <40000>;
     64 		};
     65 	};
     66 
     67 	arm-pmu {
     68 		compatible = "arm,cortex-a7-pmu";
     69 		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
     70 	};
     71 
     72 	timer {
     73 		compatible = "arm,armv7-timer";
     74 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
     75 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
     76 		clock-frequency = <24000000>;
     77 	};
     78 
     79 	xin24m: oscillator {
     80 		compatible = "fixed-clock";
     81 		clock-frequency = <24000000>;
     82 		clock-output-names = "xin24m";
     83 		#clock-cells = <0>;
     84 	};
     85 
     86 	amba {
     87 		compatible = "simple-bus";
     88 		#address-cells = <1>;
     89 		#size-cells = <1>;
     90 		ranges;
     91 
     92 		pdma: pdma@102a0000 {
     93 			compatible = "arm,pl330", "arm,primecell";
     94 			reg = <0x102a0000 0x4000>;
     95 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
     96 			#dma-cells = <1>;
     97 			arm,pl330-broken-no-flushp;
     98 			clocks = <&cru ACLK_DMAC>;
     99 			clock-names = "apb_pclk";
    100 		};
    101 	};
    102 
    103 	bus_intmem@10080000 {
    104 		compatible = "mmio-sram";
    105 		reg = <0x10080000 0x2000>;
    106 		#address-cells = <1>;
    107 		#size-cells = <1>;
    108 		ranges = <0 0x10080000 0x2000>;
    109 	};
    110 
    111 	uart2: serial@10210000 {
    112 		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
    113 		reg = <0x10210000 0x100>;
    114 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
    115 		reg-shift = <2>;
    116 		reg-io-width = <4>;
    117 		clock-frequency = <24000000>;
    118 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
    119 		clock-names = "baudclk", "apb_pclk";
    120 		pinctrl-names = "default";
    121 		pinctrl-0 = <&uart2m0_xfer>;
    122 		status = "disabled";
    123 	};
    124 
    125 	uart1: serial@10220000 {
    126 		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
    127 		reg = <0x10220000 0x100>;
    128 		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
    129 		reg-shift = <2>;
    130 		reg-io-width = <4>;
    131 		clock-frequency = <24000000>;
    132 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
    133 		clock-names = "baudclk", "apb_pclk";
    134 		pinctrl-names = "default";
    135 		pinctrl-0 = <&uart1_xfer>;
    136 		status = "disabled";
    137 	};
    138 
    139 	uart0: serial@10230000 {
    140 		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
    141 		reg = <0x10230000 0x100>;
    142 		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
    143 		reg-shift = <2>;
    144 		reg-io-width = <4>;
    145 		clock-frequency = <24000000>;
    146 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
    147 		clock-names = "baudclk", "apb_pclk";
    148 		pinctrl-names = "default";
    149 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
    150 		status = "disabled";
    151 	};
    152 
    153 	i2c1: i2c@10240000 {
    154 		compatible = "rockchip,rv1108-i2c";
    155 		reg = <0x10240000 0x1000>;
    156 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
    157 		#address-cells = <1>;
    158 		#size-cells = <0>;
    159 		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
    160 		clock-names = "i2c", "pclk";
    161 		pinctrl-names = "default";
    162 		pinctrl-0 = <&i2c1_xfer>;
    163 		rockchip,grf = <&grf>;
    164 		status = "disabled";
    165 	};
    166 
    167 	i2c2: i2c@10250000 {
    168 		compatible = "rockchip,rv1108-i2c";
    169 		reg = <0x10250000 0x1000>;
    170 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    171 		#address-cells = <1>;
    172 		#size-cells = <0>;
    173 		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
    174 		clock-names = "i2c", "pclk";
    175 		pinctrl-names = "default";
    176 		pinctrl-0 = <&i2c2m1_xfer>;
    177 		rockchip,grf = <&grf>;
    178 		status = "disabled";
    179 	};
    180 
    181 	i2c3: i2c@10260000 {
    182 		compatible = "rockchip,rv1108-i2c";
    183 		reg = <0x10260000 0x1000>;
    184 		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
    185 		#address-cells = <1>;
    186 		#size-cells = <0>;
    187 		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
    188 		clock-names = "i2c", "pclk";
    189 		pinctrl-names = "default";
    190 		pinctrl-0 = <&i2c3_xfer>;
    191 		rockchip,grf = <&grf>;
    192 		status = "disabled";
    193 	};
    194 
    195 	spi: spi@10270000 {
    196 		compatible = "rockchip,rv1108-spi";
    197 		reg = <0x10270000 0x1000>;
    198 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
    199 		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
    200 		clock-names = "spiclk", "apb_pclk";
    201 		dmas = <&pdma 8>, <&pdma 9>;
    202 		#dma-cells = <2>;
    203 		#address-cells = <1>;
    204 		#size-cells = <0>;
    205 		status = "disabled";
    206 	};
    207 
    208 	pwm4: pwm@10280000 {
    209 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    210 		reg = <0x10280000 0x10>;
    211 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    212 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
    213 		clock-names = "pwm", "pclk";
    214 		pinctrl-names = "default";
    215 		pinctrl-0 = <&pwm4_pin>;
    216 		#pwm-cells = <3>;
    217 		status = "disabled";
    218 	};
    219 
    220 	pwm5: pwm@10280010 {
    221 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    222 		reg = <0x10280010 0x10>;
    223 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    224 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
    225 		clock-names = "pwm", "pclk";
    226 		pinctrl-names = "default";
    227 		pinctrl-0 = <&pwm5_pin>;
    228 		#pwm-cells = <3>;
    229 		status = "disabled";
    230 	};
    231 
    232 	pwm6: pwm@10280020 {
    233 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    234 		reg = <0x10280020 0x10>;
    235 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    236 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
    237 		clock-names = "pwm", "pclk";
    238 		pinctrl-names = "default";
    239 		pinctrl-0 = <&pwm6_pin>;
    240 		#pwm-cells = <3>;
    241 		status = "disabled";
    242 	};
    243 
    244 	pwm7: pwm@10280030 {
    245 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    246 		reg = <0x10280030 0x10>;
    247 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    248 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
    249 		clock-names = "pwm", "pclk";
    250 		pinctrl-names = "default";
    251 		pinctrl-0 = <&pwm7_pin>;
    252 		#pwm-cells = <3>;
    253 		status = "disabled";
    254 	};
    255 
    256 	grf: syscon@10300000 {
    257 		compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
    258 		reg = <0x10300000 0x1000>;
    259 		#address-cells = <1>;
    260 		#size-cells = <1>;
    261 
    262 		u2phy: usb2-phy@100 {
    263 			compatible = "rockchip,rv1108-usb2phy";
    264 			reg = <0x100 0x0c>;
    265 			clocks = <&cru SCLK_USBPHY>;
    266 			clock-names = "phyclk";
    267 			#clock-cells = <0>;
    268 			clock-output-names = "usbphy";
    269 			rockchip,usbgrf = <&usbgrf>;
    270 			status = "disabled";
    271 
    272 			u2phy_otg: otg-port {
    273 				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
    274 				interrupt-names = "otg-mux";
    275 				#phy-cells = <0>;
    276 				status = "disabled";
    277 			};
    278 
    279 			u2phy_host: host-port {
    280 				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
    281 				interrupt-names = "linestate";
    282 				#phy-cells = <0>;
    283 				status = "disabled";
    284 			};
    285 		};
    286 	};
    287 
    288 	watchdog: wdt@10360000 {
    289 		compatible = "snps,dw-wdt";
    290 		reg = <0x10360000 0x100>;
    291 		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
    292 		clocks = <&cru PCLK_WDT>;
    293 		clock-names = "pclk_wdt";
    294 		status = "disabled";
    295 	};
    296 
    297 	thermal-zones {
    298 		soc_thermal: soc-thermal {
    299 			polling-delay-passive = <20>;
    300 			polling-delay = <1000>;
    301 			sustainable-power = <50>;
    302 			thermal-sensors = <&tsadc 0>;
    303 
    304 			trips {
    305 				threshold: trip-point0 {
    306 					temperature = <70000>;
    307 					hysteresis = <2000>;
    308 					type = "passive";
    309 				};
    310 				target: trip-point1 {
    311 					temperature = <85000>;
    312 					hysteresis = <2000>;
    313 					type = "passive";
    314 				};
    315 				soc_crit: soc-crit {
    316 					temperature = <95000>;
    317 					hysteresis = <2000>;
    318 					type = "critical";
    319 				};
    320 			};
    321 
    322 			cooling-maps {
    323 				map0 {
    324 					trip = <&target>;
    325 					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
    326 					contribution = <4096>;
    327 				};
    328 			};
    329 		};
    330 	};
    331 
    332 	tsadc: tsadc@10370000 {
    333 		compatible = "rockchip,rv1108-tsadc";
    334 		reg = <0x10370000 0x100>;
    335 		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
    336 		assigned-clocks = <&cru SCLK_TSADC>;
    337 		assigned-clock-rates = <750000>;
    338 		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
    339 		clock-names = "tsadc", "apb_pclk";
    340 		pinctrl-names = "init", "default", "sleep";
    341 		pinctrl-0 = <&otp_gpio>;
    342 		pinctrl-1 = <&otp_out>;
    343 		pinctrl-2 = <&otp_gpio>;
    344 		resets = <&cru SRST_TSADC>;
    345 		reset-names = "tsadc-apb";
    346 		rockchip,hw-tshut-temp = <120000>;
    347 		#thermal-sensor-cells = <1>;
    348 		status = "disabled";
    349 	};
    350 
    351 	adc: adc@1038c000 {
    352 		compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
    353 		reg = <0x1038c000 0x100>;
    354 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
    355 		#io-channel-cells = <1>;
    356 		clock-frequency = <1000000>;
    357 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
    358 		clock-names = "saradc", "apb_pclk";
    359 		status = "disabled";
    360 	};
    361 
    362 	i2c0: i2c@20000000 {
    363 		compatible = "rockchip,rv1108-i2c";
    364 		reg = <0x20000000 0x1000>;
    365 		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
    366 		#address-cells = <1>;
    367 		#size-cells = <0>;
    368 		clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
    369 		clock-names = "i2c", "pclk";
    370 		pinctrl-names = "default";
    371 		pinctrl-0 = <&i2c0_xfer>;
    372 		rockchip,grf = <&grf>;
    373 		status = "disabled";
    374 	};
    375 
    376 	pwm0: pwm@20040000 {
    377 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    378 		reg = <0x20040000 0x10>;
    379 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
    380 		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
    381 		clock-names = "pwm", "pclk";
    382 		pinctrl-names = "default";
    383 		pinctrl-0 = <&pwm0_pin>;
    384 		#pwm-cells = <3>;
    385 		status = "disabled";
    386 	};
    387 
    388 	pwm1: pwm@20040010 {
    389 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    390 		reg = <0x20040010 0x10>;
    391 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
    392 		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
    393 		clock-names = "pwm", "pclk";
    394 		pinctrl-names = "default";
    395 		pinctrl-0 = <&pwm1_pin>;
    396 		#pwm-cells = <3>;
    397 		status = "disabled";
    398 	};
    399 
    400 	pwm2: pwm@20040020 {
    401 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    402 		reg = <0x20040020 0x10>;
    403 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
    404 		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
    405 		clock-names = "pwm", "pclk";
    406 		pinctrl-names = "default";
    407 		pinctrl-0 = <&pwm2_pin>;
    408 		#pwm-cells = <3>;
    409 		status = "disabled";
    410 	};
    411 
    412 	pwm3: pwm@20040030 {
    413 		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
    414 		reg = <0x20040030 0x10>;
    415 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
    416 		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
    417 		clock-names = "pwm", "pclk";
    418 		pinctrl-names = "default";
    419 		pinctrl-0 = <&pwm3_pin>;
    420 		#pwm-cells = <3>;
    421 		status = "disabled";
    422 	};
    423 
    424 	pmugrf: syscon@20060000 {
    425 		compatible = "rockchip,rv1108-pmugrf", "syscon";
    426 		reg = <0x20060000 0x1000>;
    427 	};
    428 
    429 	usbgrf: syscon@202a0000 {
    430 		compatible = "rockchip,rv1108-usbgrf", "syscon";
    431 		reg = <0x202a0000 0x1000>;
    432 	};
    433 
    434 	cru: clock-controller@20200000 {
    435 		compatible = "rockchip,rv1108-cru";
    436 		reg = <0x20200000 0x1000>;
    437 		rockchip,grf = <&grf>;
    438 		#clock-cells = <1>;
    439 		#reset-cells = <1>;
    440 	};
    441 
    442 	emmc: dwmmc@30110000 {
    443 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
    444 		reg = <0x30110000 0x4000>;
    445 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
    446 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
    447 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
    448 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
    449 		fifo-depth = <0x100>;
    450 		max-frequency = <150000000>;
    451 		status = "disabled";
    452 	};
    453 
    454 	sdio: dwmmc@30120000 {
    455 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
    456 		reg = <0x30120000 0x4000>;
    457 		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
    458 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
    459 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
    460 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
    461 		fifo-depth = <0x100>;
    462 		max-frequency = <150000000>;
    463 		status = "disabled";
    464 	};
    465 
    466 	sdmmc: dwmmc@30130000 {
    467 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
    468 		reg = <0x30130000 0x4000>;
    469 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
    470 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
    471 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
    472 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
    473 		fifo-depth = <0x100>;
    474 		max-frequency = <100000000>;
    475 		pinctrl-names = "default";
    476 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
    477 		status = "disabled";
    478 	};
    479 
    480 	usb_host_ehci: usb@30140000 {
    481 		compatible = "generic-ehci";
    482 		reg = <0x30140000 0x20000>;
    483 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    484 		clocks = <&cru HCLK_HOST0>, <&u2phy>;
    485 		clock-names = "usbhost", "utmi";
    486 		phys = <&u2phy_host>;
    487 		phy-names = "usb";
    488 		status = "disabled";
    489 	};
    490 
    491 	usb_host_ohci: usb@30160000 {
    492 		compatible = "generic-ohci";
    493 		reg = <0x30160000 0x20000>;
    494 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
    495 		clocks = <&cru HCLK_HOST0>, <&u2phy>;
    496 		clock-names = "usbhost", "utmi";
    497 		phys = <&u2phy_host>;
    498 		phy-names = "usb";
    499 		status = "disabled";
    500 	};
    501 
    502 	usb_otg: usb@30180000 {
    503 		compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
    504 			     "snps,dwc2";
    505 		reg = <0x30180000 0x40000>;
    506 		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
    507 		clocks = <&cru HCLK_OTG>;
    508 		clock-names = "otg";
    509 		dr_mode = "otg";
    510 		g-np-tx-fifo-size = <16>;
    511 		g-rx-fifo-size = <280>;
    512 		g-tx-fifo-size = <256 128 128 64 32 16>;
    513 		g-use-dma;
    514 		phys = <&u2phy_otg>;
    515 		phy-names = "usb2-phy";
    516 		status = "disabled";
    517 	};
    518 
    519 	gic: interrupt-controller@32010000 {
    520 		compatible = "arm,gic-400";
    521 		interrupt-controller;
    522 		#interrupt-cells = <3>;
    523 		#address-cells = <0>;
    524 
    525 		reg = <0x32011000 0x1000>,
    526 		      <0x32012000 0x2000>,
    527 		      <0x32014000 0x2000>,
    528 		      <0x32016000 0x2000>;
    529 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
    530 	};
    531 
    532 	pinctrl: pinctrl {
    533 		compatible = "rockchip,rv1108-pinctrl";
    534 		rockchip,grf = <&grf>;
    535 		rockchip,pmu = <&pmugrf>;
    536 		#address-cells = <1>;
    537 		#size-cells = <1>;
    538 		ranges;
    539 
    540 		gpio0: gpio0@20030000 {
    541 			compatible = "rockchip,gpio-bank";
    542 			reg = <0x20030000 0x100>;
    543 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
    544 			clocks = <&xin24m>;
    545 
    546 			gpio-controller;
    547 			#gpio-cells = <2>;
    548 
    549 			interrupt-controller;
    550 			#interrupt-cells = <2>;
    551 		};
    552 
    553 		gpio1: gpio1@10310000 {
    554 			compatible = "rockchip,gpio-bank";
    555 			reg = <0x10310000 0x100>;
    556 			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
    557 			clocks = <&xin24m>;
    558 
    559 			gpio-controller;
    560 			#gpio-cells = <2>;
    561 
    562 			interrupt-controller;
    563 			#interrupt-cells = <2>;
    564 		};
    565 
    566 		gpio2: gpio2@10320000 {
    567 			compatible = "rockchip,gpio-bank";
    568 			reg = <0x10320000 0x100>;
    569 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
    570 			clocks = <&xin24m>;
    571 
    572 			gpio-controller;
    573 			#gpio-cells = <2>;
    574 
    575 			interrupt-controller;
    576 			#interrupt-cells = <2>;
    577 		};
    578 
    579 		gpio3: gpio3@10330000 {
    580 			compatible = "rockchip,gpio-bank";
    581 			reg = <0x10330000 0x100>;
    582 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
    583 			clocks = <&xin24m>;
    584 
    585 			gpio-controller;
    586 			#gpio-cells = <2>;
    587 
    588 			interrupt-controller;
    589 			#interrupt-cells = <2>;
    590 		};
    591 
    592 		pcfg_pull_up: pcfg-pull-up {
    593 			bias-pull-up;
    594 		};
    595 
    596 		pcfg_pull_down: pcfg-pull-down {
    597 			bias-pull-down;
    598 		};
    599 
    600 		pcfg_pull_none: pcfg-pull-none {
    601 			bias-disable;
    602 		};
    603 
    604 		pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
    605 			drive-strength = <8>;
    606 		};
    607 
    608 		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
    609 			drive-strength = <12>;
    610 		};
    611 
    612 		pcfg_pull_none_smt: pcfg-pull-none-smt {
    613 			bias-disable;
    614 			input-schmitt-enable;
    615 		};
    616 
    617 		pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
    618 			bias-pull-up;
    619 			drive-strength = <8>;
    620 		};
    621 
    622 		pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
    623 			drive-strength = <4>;
    624 		};
    625 
    626 		pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
    627 			bias-pull-up;
    628 			drive-strength = <4>;
    629 		};
    630 
    631 		pcfg_output_high: pcfg-output-high {
    632 			output-high;
    633 		};
    634 
    635 		pcfg_output_low: pcfg-output-low {
    636 			output-low;
    637 		};
    638 
    639 		pcfg_input_high: pcfg-input-high {
    640 			bias-pull-up;
    641 			input-enable;
    642 		};
    643 
    644 		i2c0 {
    645 			i2c0_xfer: i2c0-xfer {
    646 				rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
    647 						<0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
    648 			};
    649 		};
    650 
    651 		i2c1 {
    652 			i2c1_xfer: i2c1-xfer {
    653 				rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
    654 						<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
    655 			};
    656 		};
    657 
    658 		i2c2m1 {
    659 			i2c2m1_xfer: i2c2m1-xfer {
    660 				rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
    661 						<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
    662 			};
    663 
    664 			i2c2m1_gpio: i2c2m1-gpio {
    665 				rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
    666 						<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
    667 			};
    668 		};
    669 
    670 		i2c2m05v {
    671 			i2c2m05v_xfer: i2c2m05v-xfer {
    672 				rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
    673 						<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
    674 			};
    675 
    676 			i2c2m05v_gpio: i2c2m05v-gpio {
    677 				rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
    678 						<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
    679 			};
    680 		};
    681 
    682 		i2c3 {
    683 			i2c3_xfer: i2c3-xfer {
    684 				rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
    685 						<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
    686 			};
    687 		};
    688 
    689 		pwm0 {
    690 			pwm0_pin: pwm0-pin {
    691 				rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
    692 			};
    693 		};
    694 
    695 		pwm1 {
    696 			pwm1_pin: pwm1-pin {
    697 				rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
    698 			};
    699 		};
    700 
    701 		pwm2 {
    702 			pwm2_pin: pwm2-pin {
    703 				rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
    704 			};
    705 		};
    706 
    707 		pwm3 {
    708 			pwm3_pin: pwm3-pin {
    709 				rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
    710 			};
    711 		};
    712 
    713 		pwm4 {
    714 			pwm4_pin: pwm4-pin {
    715 				rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
    716 			};
    717 		};
    718 
    719 		pwm5 {
    720 			pwm5_pin: pwm5-pin {
    721 				rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
    722 			};
    723 		};
    724 
    725 		pwm6 {
    726 			pwm6_pin: pwm6-pin {
    727 				rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
    728 			};
    729 		};
    730 
    731 		pwm7 {
    732 			pwm7_pin: pwm7-pin {
    733 				rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
    734 			};
    735 		};
    736 
    737 		sdmmc {
    738 			sdmmc_clk: sdmmc-clk {
    739 				rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
    740 			};
    741 
    742 			sdmmc_cmd: sdmmc-cmd {
    743 				rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
    744 			};
    745 
    746 			sdmmc_cd: sdmmc-cd {
    747 				rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
    748 			};
    749 
    750 			sdmmc_bus1: sdmmc-bus1 {
    751 				rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
    752 			};
    753 
    754 			sdmmc_bus4: sdmmc-bus4 {
    755 				rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
    756 						<3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
    757 						<3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
    758 						<3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
    759 			};
    760 		};
    761 
    762 		tsadc {
    763 			otp_out: otp-out {
    764 				rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
    765 			};
    766 
    767 			otp_gpio: otp-gpio {
    768 				rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
    769 			};
    770 		};
    771 
    772 		uart0 {
    773 			uart0_xfer: uart0-xfer {
    774 				rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
    775 						<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
    776 			};
    777 
    778 			uart0_cts: uart0-cts {
    779 				rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
    780 			};
    781 
    782 			uart0_rts: uart0-rts {
    783 				rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
    784 			};
    785 
    786 			uart0_rts_gpio: uart0-rts-gpio {
    787 				rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
    788 			};
    789 		};
    790 
    791 		uart1 {
    792 			uart1_xfer: uart1-xfer {
    793 				rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
    794 						<1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
    795 			};
    796 
    797 			uart1_cts: uart1-cts {
    798 				rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
    799 			};
    800 
    801 			uart1_rts: uart1-rts {
    802 				rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
    803 			};
    804 		};
    805 
    806 		uart2m0 {
    807 			uart2m0_xfer: uart2m0-xfer {
    808 				rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
    809 						<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
    810 			};
    811 		};
    812 
    813 		uart2m1 {
    814 			uart2m1_xfer: uart2m1-xfer {
    815 				rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
    816 						<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
    817 			};
    818 		};
    819 
    820 		uart2_5v {
    821 			uart2_5v_cts: uart2_5v-cts {
    822 				rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
    823 			};
    824 
    825 			uart2_5v_rts: uart2_5v-rts {
    826 				rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
    827 			};
    828 		};
    829 	};
    830 };
    831