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      1  1.1.1.4     skrll // SPDX-License-Identifier: GPL-2.0-or-later
      2      1.1  jmcneill /*
      3      1.1  jmcneill  * DTS file for all SPEAr1340 SoCs
      4      1.1  jmcneill  *
      5      1.1  jmcneill  * Copyright 2012 Viresh Kumar <vireshk (a] kernel.org>
      6      1.1  jmcneill  */
      7      1.1  jmcneill 
      8      1.1  jmcneill /include/ "spear13xx.dtsi"
      9      1.1  jmcneill 
     10      1.1  jmcneill / {
     11      1.1  jmcneill 	compatible = "st,spear1340";
     12      1.1  jmcneill 
     13      1.1  jmcneill 	ahb {
     14      1.1  jmcneill 
     15      1.1  jmcneill 		spics: spics@e0700000{
     16      1.1  jmcneill 			compatible = "st,spear-spics-gpio";
     17      1.1  jmcneill 			reg = <0xe0700000 0x1000>;
     18      1.1  jmcneill 			st-spics,peripcfg-reg = <0x42c>;
     19      1.1  jmcneill 			st-spics,sw-enable-bit = <21>;
     20      1.1  jmcneill 			st-spics,cs-value-bit = <20>;
     21      1.1  jmcneill 			st-spics,cs-enable-mask = <3>;
     22      1.1  jmcneill 			st-spics,cs-enable-shift = <18>;
     23      1.1  jmcneill 			gpio-controller;
     24      1.1  jmcneill 			#gpio-cells = <2>;
     25      1.1  jmcneill 			status = "disabled";
     26      1.1  jmcneill 		};
     27      1.1  jmcneill 
     28      1.1  jmcneill 		miphy0: miphy@eb800000 {
     29      1.1  jmcneill 			compatible = "st,spear1340-miphy";
     30      1.1  jmcneill 			reg = <0xeb800000 0x4000>;
     31      1.1  jmcneill 			misc = <&misc>;
     32      1.1  jmcneill 			#phy-cells = <1>;
     33      1.1  jmcneill 			status = "disabled";
     34      1.1  jmcneill 		};
     35      1.1  jmcneill 
     36      1.1  jmcneill 		ahci0: ahci@b1000000 {
     37      1.1  jmcneill 			compatible = "snps,spear-ahci";
     38      1.1  jmcneill 			reg = <0xb1000000 0x10000>;
     39      1.1  jmcneill 			interrupts = <0 72 0x4>;
     40      1.1  jmcneill 			phys = <&miphy0 0>;
     41      1.1  jmcneill 			phy-names = "sata-phy";
     42      1.1  jmcneill 			status = "disabled";
     43      1.1  jmcneill 		};
     44      1.1  jmcneill 
     45      1.1  jmcneill 		pcie0: pcie@b1000000 {
     46      1.1  jmcneill 			compatible = "st,spear1340-pcie", "snps,dw-pcie";
     47      1.1  jmcneill 			reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
     48      1.1  jmcneill 			reg-names = "dbi", "config";
     49      1.1  jmcneill 			interrupts = <0 68 0x4>;
     50      1.1  jmcneill 			interrupt-map-mask = <0 0 0 0>;
     51      1.1  jmcneill 			interrupt-map = <0x0 0 &gic 0 68 0x4>;
     52      1.1  jmcneill 			num-lanes = <1>;
     53      1.1  jmcneill 			phys = <&miphy0 1>;
     54      1.1  jmcneill 			phy-names = "pcie-phy";
     55      1.1  jmcneill 			#address-cells = <3>;
     56      1.1  jmcneill 			#size-cells = <2>;
     57      1.1  jmcneill 			device_type = "pci";
     58      1.1  jmcneill 			ranges = <0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
     59      1.1  jmcneill 				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
     60  1.1.1.2  jmcneill 			bus-range = <0x00 0xff>;
     61      1.1  jmcneill 			status = "disabled";
     62      1.1  jmcneill 		};
     63      1.1  jmcneill 
     64      1.1  jmcneill 		i2s-play@b2400000 {
     65      1.1  jmcneill 			compatible = "snps,designware-i2s";
     66      1.1  jmcneill 			reg = <0xb2400000 0x10000>;
     67      1.1  jmcneill 			interrupt-names = "play_irq";
     68      1.1  jmcneill 			interrupts = <0 98 0x4
     69      1.1  jmcneill 				      0 99 0x4>;
     70      1.1  jmcneill 			play;
     71      1.1  jmcneill 			channel = <8>;
     72      1.1  jmcneill 			status = "disabled";
     73      1.1  jmcneill 		};
     74      1.1  jmcneill 
     75      1.1  jmcneill 		i2s-rec@b2000000 {
     76      1.1  jmcneill 			compatible = "snps,designware-i2s";
     77      1.1  jmcneill 			reg = <0xb2000000 0x10000>;
     78      1.1  jmcneill 			interrupt-names = "record_irq";
     79      1.1  jmcneill 			interrupts = <0 100  0x4
     80      1.1  jmcneill 				      0 101 0x4>;
     81      1.1  jmcneill 			record;
     82      1.1  jmcneill 			channel = <8>;
     83      1.1  jmcneill 			status = "disabled";
     84      1.1  jmcneill 		};
     85      1.1  jmcneill 
     86      1.1  jmcneill 		pinmux: pinmux@e0700000 {
     87      1.1  jmcneill 			compatible = "st,spear1340-pinmux";
     88      1.1  jmcneill 			reg = <0xe0700000 0x1000>;
     89      1.1  jmcneill 			#gpio-range-cells = <3>;
     90      1.1  jmcneill 		};
     91      1.1  jmcneill 
     92      1.1  jmcneill 		pwm: pwm@e0180000 {
     93      1.1  jmcneill 			compatible ="st,spear13xx-pwm";
     94      1.1  jmcneill 			reg = <0xe0180000 0x1000>;
     95      1.1  jmcneill 			#pwm-cells = <2>;
     96      1.1  jmcneill 			status = "disabled";
     97      1.1  jmcneill 		};
     98      1.1  jmcneill 
     99      1.1  jmcneill 		spdif-in@d0100000 {
    100      1.1  jmcneill 			compatible = "st,spdif-in";
    101      1.1  jmcneill 			reg = < 0xd0100000 0x20000
    102      1.1  jmcneill 				0xd0110000 0x10000 >;
    103      1.1  jmcneill 			interrupts = <0 84 0x4>;
    104      1.1  jmcneill 			status = "disabled";
    105      1.1  jmcneill 		};
    106      1.1  jmcneill 
    107      1.1  jmcneill 		spdif-out@d0000000 {
    108      1.1  jmcneill 			compatible = "st,spdif-out";
    109      1.1  jmcneill 			reg = <0xd0000000 0x20000>;
    110      1.1  jmcneill 			interrupts = <0 85 0x4>;
    111      1.1  jmcneill 			status = "disabled";
    112      1.1  jmcneill 		};
    113      1.1  jmcneill 
    114      1.1  jmcneill 		spi1: spi@5d400000 {
    115      1.1  jmcneill 			compatible = "arm,pl022", "arm,primecell";
    116      1.1  jmcneill 			reg = <0x5d400000 0x1000>;
    117      1.1  jmcneill 			#address-cells = <1>;
    118      1.1  jmcneill 			#size-cells = <0>;
    119      1.1  jmcneill 			interrupts = <0 99 0x4>;
    120      1.1  jmcneill 			status = "disabled";
    121      1.1  jmcneill 		};
    122      1.1  jmcneill 
    123      1.1  jmcneill 		apb {
    124      1.1  jmcneill 			i2c1: i2c@b4000000 {
    125      1.1  jmcneill 				#address-cells = <1>;
    126      1.1  jmcneill 				#size-cells = <0>;
    127      1.1  jmcneill 				compatible = "snps,designware-i2c";
    128      1.1  jmcneill 				reg = <0xb4000000 0x1000>;
    129      1.1  jmcneill 				interrupts = <0 104 0x4>;
    130      1.1  jmcneill 				write-16bit;
    131      1.1  jmcneill 				status = "disabled";
    132      1.1  jmcneill 			};
    133      1.1  jmcneill 
    134      1.1  jmcneill 			serial@b4100000 {
    135      1.1  jmcneill 				compatible = "arm,pl011", "arm,primecell";
    136      1.1  jmcneill 				reg = <0xb4100000 0x1000>;
    137      1.1  jmcneill 				interrupts = <0 105 0x4>;
    138      1.1  jmcneill 				status = "disabled";
    139  1.1.1.3  jmcneill 				dmas = <&dwdma0 12 0 1>,
    140  1.1.1.3  jmcneill 					<&dwdma0 13 1 0>;
    141      1.1  jmcneill 				dma-names = "tx", "rx";
    142      1.1  jmcneill 			};
    143      1.1  jmcneill 
    144      1.1  jmcneill 			thermal@e07008c4 {
    145      1.1  jmcneill 				st,thermal-flags = <0x2a00>;
    146      1.1  jmcneill 			};
    147      1.1  jmcneill 
    148      1.1  jmcneill 			gpiopinctrl: gpio@e2800000 {
    149      1.1  jmcneill 				compatible = "st,spear-plgpio";
    150      1.1  jmcneill 				reg = <0xe2800000 0x1000>;
    151      1.1  jmcneill 				interrupts = <0 107 0x4>;
    152      1.1  jmcneill 				#interrupt-cells = <1>;
    153      1.1  jmcneill 				interrupt-controller;
    154      1.1  jmcneill 				gpio-controller;
    155      1.1  jmcneill 				#gpio-cells = <2>;
    156      1.1  jmcneill 				gpio-ranges = <&pinmux 0 0 252>;
    157      1.1  jmcneill 				status = "disabled";
    158      1.1  jmcneill 
    159      1.1  jmcneill 				st-plgpio,ngpio = <250>;
    160      1.1  jmcneill 				st-plgpio,wdata-reg = <0x40>;
    161      1.1  jmcneill 				st-plgpio,dir-reg = <0x00>;
    162      1.1  jmcneill 				st-plgpio,ie-reg = <0x80>;
    163      1.1  jmcneill 				st-plgpio,rdata-reg = <0x20>;
    164      1.1  jmcneill 				st-plgpio,mis-reg = <0xa0>;
    165      1.1  jmcneill 				st-plgpio,eit-reg = <0x60>;
    166      1.1  jmcneill 			};
    167      1.1  jmcneill 		};
    168      1.1  jmcneill 	};
    169      1.1  jmcneill };
    170