sun5i-gr8.dtsi revision 1.1.1.1
1 /* 2 * Copyright 2016 Mylne Josserand 3 * 4 * Mylne Josserand <mylene.josserand (at) free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45 #include <dt-bindings/clock/sun5i-ccu.h> 46 #include <dt-bindings/dma/sun4i-a10.h> 47 #include <dt-bindings/pinctrl/sun4i-a10.h> 48 #include <dt-bindings/reset/sun5i-ccu.h> 49 50 / { 51 interrupt-parent = <&intc>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a8"; 62 reg = <0x0>; 63 clocks = <&ccu CLK_CPU>; 64 }; 65 }; 66 67 clocks { 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges; 71 72 osc24M: clk@01c20050 { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <24000000>; 76 clock-output-names = "osc24M"; 77 }; 78 79 osc32k: clk@0 { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <32768>; 83 clock-output-names = "osc32k"; 84 }; 85 }; 86 87 display-engine { 88 compatible = "allwinner,sun5i-a13-display-engine"; 89 allwinner,pipelines = <&fe0>; 90 }; 91 92 soc@01c00000 { 93 compatible = "simple-bus"; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 ranges; 97 98 sram-controller@01c00000 { 99 compatible = "allwinner,sun4i-a10-sram-controller"; 100 reg = <0x01c00000 0x30>; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 ranges; 104 105 sram_a: sram@00000000 { 106 compatible = "mmio-sram"; 107 reg = <0x00000000 0xc000>; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0 0x00000000 0xc000>; 111 }; 112 113 sram_d: sram@00010000 { 114 compatible = "mmio-sram"; 115 reg = <0x00010000 0x1000>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00010000 0x1000>; 119 120 otg_sram: sram-section@0000 { 121 compatible = "allwinner,sun4i-a10-sram-d"; 122 reg = <0x0000 0x1000>; 123 status = "disabled"; 124 }; 125 }; 126 }; 127 128 dma: dma-controller@01c02000 { 129 compatible = "allwinner,sun4i-a10-dma"; 130 reg = <0x01c02000 0x1000>; 131 interrupts = <27>; 132 clocks = <&ccu CLK_AHB_DMA>; 133 #dma-cells = <2>; 134 }; 135 136 nfc: nand@01c03000 { 137 compatible = "allwinner,sun4i-a10-nand"; 138 reg = <0x01c03000 0x1000>; 139 interrupts = <37>; 140 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; 141 clock-names = "ahb", "mod"; 142 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 143 dma-names = "rxtx"; 144 status = "disabled"; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 }; 148 149 spi0: spi@01c05000 { 150 compatible = "allwinner,sun4i-a10-spi"; 151 reg = <0x01c05000 0x1000>; 152 interrupts = <10>; 153 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; 154 clock-names = "ahb", "mod"; 155 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 156 <&dma SUN4I_DMA_DEDICATED 26>; 157 dma-names = "rx", "tx"; 158 status = "disabled"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 }; 162 163 spi1: spi@01c06000 { 164 compatible = "allwinner,sun4i-a10-spi"; 165 reg = <0x01c06000 0x1000>; 166 interrupts = <11>; 167 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; 168 clock-names = "ahb", "mod"; 169 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 170 <&dma SUN4I_DMA_DEDICATED 8>; 171 dma-names = "rx", "tx"; 172 status = "disabled"; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 }; 176 177 tve0: tv-encoder@01c0a000 { 178 compatible = "allwinner,sun4i-a10-tv-encoder"; 179 reg = <0x01c0a000 0x1000>; 180 clocks = <&ccu CLK_AHB_TVE>; 181 resets = <&ccu RST_TVE>; 182 status = "disabled"; 183 184 port { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 tve0_in_tcon0: endpoint@0 { 189 reg = <0>; 190 remote-endpoint = <&tcon0_out_tve0>; 191 }; 192 }; 193 }; 194 195 tcon0: lcd-controller@01c0c000 { 196 compatible = "allwinner,sun5i-a13-tcon"; 197 reg = <0x01c0c000 0x1000>; 198 interrupts = <44>; 199 resets = <&ccu RST_LCD>; 200 reset-names = "lcd"; 201 clocks = <&ccu CLK_AHB_LCD>, 202 <&ccu CLK_TCON_CH0>, 203 <&ccu CLK_TCON_CH1>; 204 clock-names = "ahb", 205 "tcon-ch0", 206 "tcon-ch1"; 207 clock-output-names = "tcon-pixel-clock"; 208 status = "disabled"; 209 210 ports { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 tcon0_in: port@0 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <0>; 218 219 tcon0_in_be0: endpoint@0 { 220 reg = <0>; 221 remote-endpoint = <&be0_out_tcon0>; 222 }; 223 }; 224 225 tcon0_out: port@1 { 226 #address-cells = <1>; 227 #size-cells = <0>; 228 reg = <1>; 229 230 tcon0_out_tve0: endpoint@1 { 231 reg = <1>; 232 remote-endpoint = <&tve0_in_tcon0>; 233 }; 234 }; 235 }; 236 }; 237 238 mmc0: mmc@01c0f000 { 239 compatible = "allwinner,sun5i-a13-mmc"; 240 reg = <0x01c0f000 0x1000>; 241 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; 242 clock-names = "ahb", "mmc"; 243 interrupts = <32>; 244 status = "disabled"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 mmc1: mmc@01c10000 { 250 compatible = "allwinner,sun5i-a13-mmc"; 251 reg = <0x01c10000 0x1000>; 252 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; 253 clock-names = "ahb", "mmc"; 254 interrupts = <33>; 255 status = "disabled"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 }; 259 260 mmc2: mmc@01c11000 { 261 compatible = "allwinner,sun5i-a13-mmc"; 262 reg = <0x01c11000 0x1000>; 263 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; 264 clock-names = "ahb", "mmc"; 265 interrupts = <34>; 266 status = "disabled"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 }; 270 271 usb_otg: usb@01c13000 { 272 compatible = "allwinner,sun4i-a10-musb"; 273 reg = <0x01c13000 0x0400>; 274 clocks = <&ccu CLK_AHB_OTG>; 275 interrupts = <38>; 276 interrupt-names = "mc"; 277 phys = <&usbphy 0>; 278 phy-names = "usb"; 279 extcon = <&usbphy 0>; 280 allwinner,sram = <&otg_sram 1>; 281 status = "disabled"; 282 283 dr_mode = "otg"; 284 }; 285 286 usbphy: phy@01c13400 { 287 #phy-cells = <1>; 288 compatible = "allwinner,sun5i-a13-usb-phy"; 289 reg = <0x01c13400 0x10 0x01c14800 0x4>; 290 reg-names = "phy_ctrl", "pmu1"; 291 clocks = <&ccu CLK_USB_PHY0>; 292 clock-names = "usb_phy"; 293 resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; 294 reset-names = "usb0_reset", "usb1_reset"; 295 status = "disabled"; 296 }; 297 298 ehci0: usb@01c14000 { 299 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; 300 reg = <0x01c14000 0x100>; 301 interrupts = <39>; 302 clocks = <&ccu CLK_AHB_EHCI>; 303 phys = <&usbphy 1>; 304 phy-names = "usb"; 305 status = "disabled"; 306 }; 307 308 ohci0: usb@01c14400 { 309 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; 310 reg = <0x01c14400 0x100>; 311 interrupts = <40>; 312 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; 313 phys = <&usbphy 1>; 314 phy-names = "usb"; 315 status = "disabled"; 316 }; 317 318 spi2: spi@01c17000 { 319 compatible = "allwinner,sun4i-a10-spi"; 320 reg = <0x01c17000 0x1000>; 321 interrupts = <12>; 322 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; 323 clock-names = "ahb", "mod"; 324 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 325 <&dma SUN4I_DMA_DEDICATED 28>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 }; 331 332 ccu: clock@01c20000 { 333 compatible = "nextthing,gr8-ccu"; 334 reg = <0x01c20000 0x400>; 335 clocks = <&osc24M>, <&osc32k>; 336 clock-names = "hosc", "losc"; 337 #clock-cells = <1>; 338 #reset-cells = <1>; 339 }; 340 341 intc: interrupt-controller@01c20400 { 342 compatible = "allwinner,sun4i-a10-ic"; 343 reg = <0x01c20400 0x400>; 344 interrupt-controller; 345 #interrupt-cells = <1>; 346 }; 347 348 pio: pinctrl@01c20800 { 349 compatible = "nextthing,gr8-pinctrl"; 350 reg = <0x01c20800 0x400>; 351 interrupts = <28>; 352 clocks = <&ccu CLK_APB0_PIO>; 353 gpio-controller; 354 interrupt-controller; 355 #interrupt-cells = <3>; 356 #gpio-cells = <3>; 357 358 i2c0_pins_a: i2c0@0 { 359 pins = "PB0", "PB1"; 360 function = "i2c0"; 361 }; 362 363 i2c1_pins_a: i2c1@0 { 364 pins = "PB15", "PB16"; 365 function = "i2c1"; 366 }; 367 368 i2c2_pins_a: i2c2@0 { 369 pins = "PB17", "PB18"; 370 function = "i2c2"; 371 }; 372 373 i2s0_data_pins_a: i2s0-data@0 { 374 pins = "PB6", "PB7", "PB8", "PB9"; 375 function = "i2s0"; 376 }; 377 378 i2s0_mclk_pins_a: i2s0-mclk@0 { 379 pins = "PB5"; 380 function = "i2s0"; 381 }; 382 383 ir0_rx_pins_a: ir0@0 { 384 pins = "PB4"; 385 function = "ir0"; 386 }; 387 388 lcd_rgb666_pins: lcd-rgb666@0 { 389 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 390 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 391 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 392 "PD24", "PD25", "PD26", "PD27"; 393 function = "lcd0"; 394 }; 395 396 mmc0_pins_a: mmc0@0 { 397 pins = "PF0", "PF1", "PF2", "PF3", 398 "PF4", "PF5"; 399 function = "mmc0"; 400 drive-strength = <30>; 401 }; 402 403 nand_pins_a: nand-base0@0 { 404 pins = "PC0", "PC1", "PC2", 405 "PC5", "PC8", "PC9", "PC10", 406 "PC11", "PC12", "PC13", "PC14", 407 "PC15"; 408 function = "nand0"; 409 }; 410 411 nand_cs0_pins_a: nand-cs@0 { 412 pins = "PC4"; 413 function = "nand0"; 414 }; 415 416 nand_rb0_pins_a: nand-rb@0 { 417 pins = "PC6"; 418 function = "nand0"; 419 }; 420 421 pwm0_pins_a: pwm0@0 { 422 pins = "PB2"; 423 function = "pwm0"; 424 }; 425 426 pwm1_pins: pwm1 { 427 pins = "PG13"; 428 function = "pwm1"; 429 }; 430 431 spdif_tx_pins_a: spdif@0 { 432 pins = "PB10"; 433 function = "spdif"; 434 bias-pull-up; 435 }; 436 437 uart1_pins_a: uart1@1 { 438 pins = "PG3", "PG4"; 439 function = "uart1"; 440 }; 441 442 uart1_cts_rts_pins_a: uart1-cts-rts@0 { 443 pins = "PG5", "PG6"; 444 function = "uart1"; 445 }; 446 447 uart2_pins_a: uart2@1 { 448 pins = "PD2", "PD3"; 449 function = "uart2"; 450 }; 451 452 uart2_cts_rts_pins_a: uart2-cts-rts@0 { 453 pins = "PD4", "PD5"; 454 function = "uart2"; 455 }; 456 457 uart3_pins_a: uart3@1 { 458 pins = "PG9", "PG10"; 459 function = "uart3"; 460 }; 461 462 uart3_cts_rts_pins_a: uart3-cts-rts@0 { 463 pins = "PG11", "PG12"; 464 function = "uart3"; 465 }; 466 }; 467 468 pwm: pwm@01c20e00 { 469 compatible = "allwinner,sun5i-a10s-pwm"; 470 reg = <0x01c20e00 0xc>; 471 clocks = <&ccu CLK_HOSC>; 472 #pwm-cells = <3>; 473 status = "disabled"; 474 }; 475 476 timer@01c20c00 { 477 compatible = "allwinner,sun4i-a10-timer"; 478 reg = <0x01c20c00 0x90>; 479 interrupts = <22>; 480 clocks = <&ccu CLK_HOSC>; 481 }; 482 483 wdt: watchdog@01c20c90 { 484 compatible = "allwinner,sun4i-a10-wdt"; 485 reg = <0x01c20c90 0x10>; 486 }; 487 488 spdif: spdif@01c21000 { 489 #sound-dai-cells = <0>; 490 compatible = "allwinner,sun4i-a10-spdif"; 491 reg = <0x01c21000 0x400>; 492 interrupts = <13>; 493 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; 494 clock-names = "apb", "spdif"; 495 dmas = <&dma SUN4I_DMA_NORMAL 2>, 496 <&dma SUN4I_DMA_NORMAL 2>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 ir0: ir@01c21800 { 502 compatible = "allwinner,sun4i-a10-ir"; 503 clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; 504 clock-names = "apb", "ir"; 505 interrupts = <5>; 506 reg = <0x01c21800 0x40>; 507 status = "disabled"; 508 }; 509 510 i2s0: i2s@01c22400 { 511 #sound-dai-cells = <0>; 512 compatible = "allwinner,sun4i-a10-i2s"; 513 reg = <0x01c22400 0x400>; 514 interrupts = <16>; 515 clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>; 516 clock-names = "apb", "mod"; 517 dmas = <&dma SUN4I_DMA_NORMAL 3>, 518 <&dma SUN4I_DMA_NORMAL 3>; 519 dma-names = "rx", "tx"; 520 status = "disabled"; 521 }; 522 523 lradc: lradc@01c22800 { 524 compatible = "allwinner,sun4i-a10-lradc-keys"; 525 reg = <0x01c22800 0x100>; 526 interrupts = <31>; 527 status = "disabled"; 528 }; 529 530 codec: codec@01c22c00 { 531 #sound-dai-cells = <0>; 532 compatible = "allwinner,sun4i-a10-codec"; 533 reg = <0x01c22c00 0x40>; 534 interrupts = <30>; 535 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; 536 clock-names = "apb", "codec"; 537 dmas = <&dma SUN4I_DMA_NORMAL 19>, 538 <&dma SUN4I_DMA_NORMAL 19>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 rtp: rtp@01c25000 { 544 compatible = "allwinner,sun5i-a13-ts"; 545 reg = <0x01c25000 0x100>; 546 interrupts = <29>; 547 #thermal-sensor-cells = <0>; 548 }; 549 550 uart1: serial@01c28400 { 551 compatible = "snps,dw-apb-uart"; 552 reg = <0x01c28400 0x400>; 553 interrupts = <2>; 554 reg-shift = <2>; 555 reg-io-width = <4>; 556 clocks = <&ccu CLK_APB1_UART1>; 557 status = "disabled"; 558 }; 559 560 uart2: serial@01c28800 { 561 compatible = "snps,dw-apb-uart"; 562 reg = <0x01c28800 0x400>; 563 interrupts = <3>; 564 reg-shift = <2>; 565 reg-io-width = <4>; 566 clocks = <&ccu CLK_APB1_UART2>; 567 status = "disabled"; 568 }; 569 570 uart3: serial@01c28c00 { 571 compatible = "snps,dw-apb-uart"; 572 reg = <0x01c28c00 0x400>; 573 interrupts = <4>; 574 reg-shift = <2>; 575 reg-io-width = <4>; 576 clocks = <&ccu CLK_APB1_UART3>; 577 status = "disabled"; 578 }; 579 580 i2c0: i2c@01c2ac00 { 581 compatible = "allwinner,sun4i-a10-i2c"; 582 reg = <0x01c2ac00 0x400>; 583 interrupts = <7>; 584 clocks = <&ccu CLK_APB1_I2C0>; 585 status = "disabled"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 590 i2c1: i2c@01c2b000 { 591 compatible = "allwinner,sun4i-a10-i2c"; 592 reg = <0x01c2b000 0x400>; 593 interrupts = <8>; 594 clocks = <&ccu CLK_APB1_I2C1>; 595 status = "disabled"; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 }; 599 600 i2c2: i2c@01c2b400 { 601 compatible = "allwinner,sun4i-a10-i2c"; 602 reg = <0x01c2b400 0x400>; 603 interrupts = <9>; 604 clocks = <&ccu CLK_APB1_I2C2>; 605 status = "disabled"; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 }; 609 610 timer@01c60000 { 611 compatible = "allwinner,sun5i-a13-hstimer"; 612 reg = <0x01c60000 0x1000>; 613 interrupts = <82>, <83>; 614 clocks = <&ccu CLK_AHB_HSTIMER>; 615 }; 616 617 fe0: display-frontend@01e00000 { 618 compatible = "allwinner,sun5i-a13-display-frontend"; 619 reg = <0x01e00000 0x20000>; 620 interrupts = <47>; 621 clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>, 622 <&ccu CLK_DRAM_DE_FE>; 623 clock-names = "ahb", "mod", 624 "ram"; 625 resets = <&ccu RST_DE_FE>; 626 status = "disabled"; 627 628 ports { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 632 fe0_out: port@1 { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <1>; 636 637 fe0_out_be0: endpoint@0 { 638 reg = <0>; 639 remote-endpoint = <&be0_in_fe0>; 640 }; 641 }; 642 }; 643 }; 644 645 be0: display-backend@01e60000 { 646 compatible = "allwinner,sun5i-a13-display-backend"; 647 reg = <0x01e60000 0x10000>; 648 clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, 649 <&ccu CLK_DRAM_DE_BE>; 650 clock-names = "ahb", "mod", 651 "ram"; 652 resets = <&ccu RST_DE_BE>; 653 status = "disabled"; 654 655 assigned-clocks = <&ccu CLK_DE_BE>; 656 assigned-clock-rates = <300000000>; 657 658 ports { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 662 be0_in: port@0 { 663 #address-cells = <1>; 664 #size-cells = <0>; 665 reg = <0>; 666 667 be0_in_fe0: endpoint@0 { 668 reg = <0>; 669 remote-endpoint = <&fe0_out_be0>; 670 }; 671 }; 672 673 be0_out: port@1 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 reg = <1>; 677 678 be0_out_tcon0: endpoint@0 { 679 reg = <0>; 680 remote-endpoint = <&tcon0_in_be0>; 681 }; 682 }; 683 }; 684 }; 685 }; 686 }; 687
Indexes created Sun Oct 26 21:10:03 GMT 2025