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      1  1.1  jmcneill /*	$NetBSD: agilex-clock.h,v 1.1.1.1 2021/11/07 16:49:58 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /* SPDX-License-Identifier: GPL-2.0 */
      4  1.1  jmcneill /*
      5  1.1  jmcneill  * Copyright (C) 2019, Intel Corporation
      6  1.1  jmcneill  */
      7  1.1  jmcneill 
      8  1.1  jmcneill #ifndef __AGILEX_CLOCK_H
      9  1.1  jmcneill #define __AGILEX_CLOCK_H
     10  1.1  jmcneill 
     11  1.1  jmcneill /* fixed rate clocks */
     12  1.1  jmcneill #define AGILEX_OSC1			0
     13  1.1  jmcneill #define AGILEX_CB_INTOSC_HS_DIV2_CLK	1
     14  1.1  jmcneill #define AGILEX_CB_INTOSC_LS_CLK		2
     15  1.1  jmcneill #define AGILEX_L4_SYS_FREE_CLK		3
     16  1.1  jmcneill #define AGILEX_F2S_FREE_CLK		4
     17  1.1  jmcneill 
     18  1.1  jmcneill /* PLL clocks */
     19  1.1  jmcneill #define AGILEX_MAIN_PLL_CLK		5
     20  1.1  jmcneill #define AGILEX_MAIN_PLL_C0_CLK		6
     21  1.1  jmcneill #define AGILEX_MAIN_PLL_C1_CLK		7
     22  1.1  jmcneill #define AGILEX_MAIN_PLL_C2_CLK		8
     23  1.1  jmcneill #define AGILEX_MAIN_PLL_C3_CLK		9
     24  1.1  jmcneill #define AGILEX_PERIPH_PLL_CLK		10
     25  1.1  jmcneill #define AGILEX_PERIPH_PLL_C0_CLK	11
     26  1.1  jmcneill #define AGILEX_PERIPH_PLL_C1_CLK	12
     27  1.1  jmcneill #define AGILEX_PERIPH_PLL_C2_CLK	13
     28  1.1  jmcneill #define AGILEX_PERIPH_PLL_C3_CLK	14
     29  1.1  jmcneill #define AGILEX_MPU_FREE_CLK		15
     30  1.1  jmcneill #define AGILEX_MPU_CCU_CLK		16
     31  1.1  jmcneill #define AGILEX_BOOT_CLK			17
     32  1.1  jmcneill 
     33  1.1  jmcneill /* fixed factor clocks */
     34  1.1  jmcneill #define AGILEX_L3_MAIN_FREE_CLK		18
     35  1.1  jmcneill #define AGILEX_NOC_FREE_CLK		19
     36  1.1  jmcneill #define AGILEX_S2F_USR0_CLK		20
     37  1.1  jmcneill #define AGILEX_NOC_CLK			21
     38  1.1  jmcneill #define AGILEX_EMAC_A_FREE_CLK		22
     39  1.1  jmcneill #define AGILEX_EMAC_B_FREE_CLK		23
     40  1.1  jmcneill #define AGILEX_EMAC_PTP_FREE_CLK	24
     41  1.1  jmcneill #define AGILEX_GPIO_DB_FREE_CLK		25
     42  1.1  jmcneill #define AGILEX_SDMMC_FREE_CLK		26
     43  1.1  jmcneill #define AGILEX_S2F_USER0_FREE_CLK	27
     44  1.1  jmcneill #define AGILEX_S2F_USER1_FREE_CLK	28
     45  1.1  jmcneill #define AGILEX_PSI_REF_FREE_CLK		29
     46  1.1  jmcneill 
     47  1.1  jmcneill /* Gate clocks */
     48  1.1  jmcneill #define AGILEX_MPU_CLK			30
     49  1.1  jmcneill #define AGILEX_MPU_L2RAM_CLK		31
     50  1.1  jmcneill #define AGILEX_MPU_PERIPH_CLK		32
     51  1.1  jmcneill #define AGILEX_L4_MAIN_CLK		33
     52  1.1  jmcneill #define AGILEX_L4_MP_CLK		34
     53  1.1  jmcneill #define AGILEX_L4_SP_CLK		35
     54  1.1  jmcneill #define AGILEX_CS_AT_CLK		36
     55  1.1  jmcneill #define AGILEX_CS_TRACE_CLK		37
     56  1.1  jmcneill #define AGILEX_CS_PDBG_CLK		38
     57  1.1  jmcneill #define AGILEX_CS_TIMER_CLK		39
     58  1.1  jmcneill #define AGILEX_S2F_USER0_CLK		40
     59  1.1  jmcneill #define AGILEX_EMAC0_CLK		41
     60  1.1  jmcneill #define AGILEX_EMAC1_CLK		43
     61  1.1  jmcneill #define AGILEX_EMAC2_CLK		44
     62  1.1  jmcneill #define AGILEX_EMAC_PTP_CLK		45
     63  1.1  jmcneill #define AGILEX_GPIO_DB_CLK		46
     64  1.1  jmcneill #define AGILEX_NAND_CLK			47
     65  1.1  jmcneill #define AGILEX_PSI_REF_CLK		48
     66  1.1  jmcneill #define AGILEX_S2F_USER1_CLK		49
     67  1.1  jmcneill #define AGILEX_SDMMC_CLK		50
     68  1.1  jmcneill #define AGILEX_SPI_M_CLK		51
     69  1.1  jmcneill #define AGILEX_USB_CLK			52
     70  1.1  jmcneill #define AGILEX_NAND_X_CLK		53
     71  1.1  jmcneill #define AGILEX_NAND_ECC_CLK		54
     72  1.1  jmcneill #define AGILEX_NUM_CLKS			55
     73  1.1  jmcneill 
     74  1.1  jmcneill #endif	/* __AGILEX_CLOCK_H */
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