11.1Sskrll/* $NetBSD: amlogic,s4-pll-clkc.h,v 1.1.1.1 2026/01/18 05:21:28 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 41.1Sskrll/* 51.1Sskrll * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved. 61.1Sskrll * Author: Yu Tu <yu.tu@amlogic.com> 71.1Sskrll */ 81.1Sskrll 91.1Sskrll#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H 101.1Sskrll#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H 111.1Sskrll 121.1Sskrll#define CLKID_FIXED_PLL_DCO 0 131.1Sskrll#define CLKID_FIXED_PLL 1 141.1Sskrll#define CLKID_FCLK_DIV2_DIV 2 151.1Sskrll#define CLKID_FCLK_DIV2 3 161.1Sskrll#define CLKID_FCLK_DIV3_DIV 4 171.1Sskrll#define CLKID_FCLK_DIV3 5 181.1Sskrll#define CLKID_FCLK_DIV4_DIV 6 191.1Sskrll#define CLKID_FCLK_DIV4 7 201.1Sskrll#define CLKID_FCLK_DIV5_DIV 8 211.1Sskrll#define CLKID_FCLK_DIV5 9 221.1Sskrll#define CLKID_FCLK_DIV7_DIV 10 231.1Sskrll#define CLKID_FCLK_DIV7 11 241.1Sskrll#define CLKID_FCLK_DIV2P5_DIV 12 251.1Sskrll#define CLKID_FCLK_DIV2P5 13 261.1Sskrll#define CLKID_GP0_PLL_DCO 14 271.1Sskrll#define CLKID_GP0_PLL 15 281.1Sskrll#define CLKID_HIFI_PLL_DCO 16 291.1Sskrll#define CLKID_HIFI_PLL 17 301.1Sskrll#define CLKID_HDMI_PLL_DCO 18 311.1Sskrll#define CLKID_HDMI_PLL_OD 19 321.1Sskrll#define CLKID_HDMI_PLL 20 331.1Sskrll#define CLKID_MPLL_50M_DIV 21 341.1Sskrll#define CLKID_MPLL_50M 22 351.1Sskrll#define CLKID_MPLL_PREDIV 23 361.1Sskrll#define CLKID_MPLL0_DIV 24 371.1Sskrll#define CLKID_MPLL0 25 381.1Sskrll#define CLKID_MPLL1_DIV 26 391.1Sskrll#define CLKID_MPLL1 27 401.1Sskrll#define CLKID_MPLL2_DIV 28 411.1Sskrll#define CLKID_MPLL2 29 421.1Sskrll#define CLKID_MPLL3_DIV 30 431.1Sskrll#define CLKID_MPLL3 31 441.1Sskrll 451.1Sskrll#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */ 46