11.1Sskrll/* $NetBSD: amlogic,a1-peripherals-clkc.h,v 1.1.1.1 2026/01/18 05:21:28 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 41.1Sskrll/* 51.1Sskrll * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 61.1Sskrll * Author: Jian Hu <jian.hu@amlogic.com> 71.1Sskrll * 81.1Sskrll * Copyright (c) 2023, SberDevices. All Rights Reserved. 91.1Sskrll * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 101.1Sskrll */ 111.1Sskrll 121.1Sskrll#ifndef __A1_PERIPHERALS_CLKC_H 131.1Sskrll#define __A1_PERIPHERALS_CLKC_H 141.1Sskrll 151.1Sskrll#define CLKID_XTAL_IN 0 161.1Sskrll#define CLKID_FIXPLL_IN 1 171.1Sskrll#define CLKID_USB_PHY_IN 2 181.1Sskrll#define CLKID_USB_CTRL_IN 3 191.1Sskrll#define CLKID_HIFIPLL_IN 4 201.1Sskrll#define CLKID_SYSPLL_IN 5 211.1Sskrll#define CLKID_DDS_IN 6 221.1Sskrll#define CLKID_SYS 7 231.1Sskrll#define CLKID_CLKTREE 8 241.1Sskrll#define CLKID_RESET_CTRL 9 251.1Sskrll#define CLKID_ANALOG_CTRL 10 261.1Sskrll#define CLKID_PWR_CTRL 11 271.1Sskrll#define CLKID_PAD_CTRL 12 281.1Sskrll#define CLKID_SYS_CTRL 13 291.1Sskrll#define CLKID_TEMP_SENSOR 14 301.1Sskrll#define CLKID_AM2AXI_DIV 15 311.1Sskrll#define CLKID_SPICC_B 16 321.1Sskrll#define CLKID_SPICC_A 17 331.1Sskrll#define CLKID_MSR 18 341.1Sskrll#define CLKID_AUDIO 19 351.1Sskrll#define CLKID_JTAG_CTRL 20 361.1Sskrll#define CLKID_SARADC_EN 21 371.1Sskrll#define CLKID_PWM_EF 22 381.1Sskrll#define CLKID_PWM_CD 23 391.1Sskrll#define CLKID_PWM_AB 24 401.1Sskrll#define CLKID_CEC 25 411.1Sskrll#define CLKID_I2C_S 26 421.1Sskrll#define CLKID_IR_CTRL 27 431.1Sskrll#define CLKID_I2C_M_D 28 441.1Sskrll#define CLKID_I2C_M_C 29 451.1Sskrll#define CLKID_I2C_M_B 30 461.1Sskrll#define CLKID_I2C_M_A 31 471.1Sskrll#define CLKID_ACODEC 32 481.1Sskrll#define CLKID_OTP 33 491.1Sskrll#define CLKID_SD_EMMC_A 34 501.1Sskrll#define CLKID_USB_PHY 35 511.1Sskrll#define CLKID_USB_CTRL 36 521.1Sskrll#define CLKID_SYS_DSPB 37 531.1Sskrll#define CLKID_SYS_DSPA 38 541.1Sskrll#define CLKID_DMA 39 551.1Sskrll#define CLKID_IRQ_CTRL 40 561.1Sskrll#define CLKID_NIC 41 571.1Sskrll#define CLKID_GIC 42 581.1Sskrll#define CLKID_UART_C 43 591.1Sskrll#define CLKID_UART_B 44 601.1Sskrll#define CLKID_UART_A 45 611.1Sskrll#define CLKID_SYS_PSRAM 46 621.1Sskrll#define CLKID_RSA 47 631.1Sskrll#define CLKID_CORESIGHT 48 641.1Sskrll#define CLKID_AM2AXI_VAD 49 651.1Sskrll#define CLKID_AUDIO_VAD 50 661.1Sskrll#define CLKID_AXI_DMC 51 671.1Sskrll#define CLKID_AXI_PSRAM 52 681.1Sskrll#define CLKID_RAMB 53 691.1Sskrll#define CLKID_RAMA 54 701.1Sskrll#define CLKID_AXI_SPIFC 55 711.1Sskrll#define CLKID_AXI_NIC 56 721.1Sskrll#define CLKID_AXI_DMA 57 731.1Sskrll#define CLKID_CPU_CTRL 58 741.1Sskrll#define CLKID_ROM 59 751.1Sskrll#define CLKID_PROC_I2C 60 761.1Sskrll#define CLKID_DSPA_SEL 61 771.1Sskrll#define CLKID_DSPB_SEL 62 781.1Sskrll#define CLKID_DSPA_EN 63 791.1Sskrll#define CLKID_DSPA_EN_NIC 64 801.1Sskrll#define CLKID_DSPB_EN 65 811.1Sskrll#define CLKID_DSPB_EN_NIC 66 821.1Sskrll#define CLKID_RTC 67 831.1Sskrll#define CLKID_CECA_32K 68 841.1Sskrll#define CLKID_CECB_32K 69 851.1Sskrll#define CLKID_24M 70 861.1Sskrll#define CLKID_12M 71 871.1Sskrll#define CLKID_FCLK_DIV2_DIVN 72 881.1Sskrll#define CLKID_GEN 73 891.1Sskrll#define CLKID_SARADC_SEL 74 901.1Sskrll#define CLKID_SARADC 75 911.1Sskrll#define CLKID_PWM_A 76 921.1Sskrll#define CLKID_PWM_B 77 931.1Sskrll#define CLKID_PWM_C 78 941.1Sskrll#define CLKID_PWM_D 79 951.1Sskrll#define CLKID_PWM_E 80 961.1Sskrll#define CLKID_PWM_F 81 971.1Sskrll#define CLKID_SPICC 82 981.1Sskrll#define CLKID_TS 83 991.1Sskrll#define CLKID_SPIFC 84 1001.1Sskrll#define CLKID_USB_BUS 85 1011.1Sskrll#define CLKID_SD_EMMC 86 1021.1Sskrll#define CLKID_PSRAM 87 1031.1Sskrll#define CLKID_DMC 88 1041.1Sskrll#define CLKID_SYS_A_SEL 89 1051.1Sskrll#define CLKID_SYS_A_DIV 90 1061.1Sskrll#define CLKID_SYS_A 91 1071.1Sskrll#define CLKID_SYS_B_SEL 92 1081.1Sskrll#define CLKID_SYS_B_DIV 93 1091.1Sskrll#define CLKID_SYS_B 94 1101.1Sskrll#define CLKID_DSPA_A_SEL 95 1111.1Sskrll#define CLKID_DSPA_A_DIV 96 1121.1Sskrll#define CLKID_DSPA_A 97 1131.1Sskrll#define CLKID_DSPA_B_SEL 98 1141.1Sskrll#define CLKID_DSPA_B_DIV 99 1151.1Sskrll#define CLKID_DSPA_B 100 1161.1Sskrll#define CLKID_DSPB_A_SEL 101 1171.1Sskrll#define CLKID_DSPB_A_DIV 102 1181.1Sskrll#define CLKID_DSPB_A 103 1191.1Sskrll#define CLKID_DSPB_B_SEL 104 1201.1Sskrll#define CLKID_DSPB_B_DIV 105 1211.1Sskrll#define CLKID_DSPB_B 106 1221.1Sskrll#define CLKID_RTC_32K_IN 107 1231.1Sskrll#define CLKID_RTC_32K_DIV 108 1241.1Sskrll#define CLKID_RTC_32K_XTAL 109 1251.1Sskrll#define CLKID_RTC_32K_SEL 110 1261.1Sskrll#define CLKID_CECB_32K_IN 111 1271.1Sskrll#define CLKID_CECB_32K_DIV 112 1281.1Sskrll#define CLKID_CECB_32K_SEL_PRE 113 1291.1Sskrll#define CLKID_CECB_32K_SEL 114 1301.1Sskrll#define CLKID_CECA_32K_IN 115 1311.1Sskrll#define CLKID_CECA_32K_DIV 116 1321.1Sskrll#define CLKID_CECA_32K_SEL_PRE 117 1331.1Sskrll#define CLKID_CECA_32K_SEL 118 1341.1Sskrll#define CLKID_DIV2_PRE 119 1351.1Sskrll#define CLKID_24M_DIV2 120 1361.1Sskrll#define CLKID_GEN_SEL 121 1371.1Sskrll#define CLKID_GEN_DIV 122 1381.1Sskrll#define CLKID_SARADC_DIV 123 1391.1Sskrll#define CLKID_PWM_A_SEL 124 1401.1Sskrll#define CLKID_PWM_A_DIV 125 1411.1Sskrll#define CLKID_PWM_B_SEL 126 1421.1Sskrll#define CLKID_PWM_B_DIV 127 1431.1Sskrll#define CLKID_PWM_C_SEL 128 1441.1Sskrll#define CLKID_PWM_C_DIV 129 1451.1Sskrll#define CLKID_PWM_D_SEL 130 1461.1Sskrll#define CLKID_PWM_D_DIV 131 1471.1Sskrll#define CLKID_PWM_E_SEL 132 1481.1Sskrll#define CLKID_PWM_E_DIV 133 1491.1Sskrll#define CLKID_PWM_F_SEL 134 1501.1Sskrll#define CLKID_PWM_F_DIV 135 1511.1Sskrll#define CLKID_SPICC_SEL 136 1521.1Sskrll#define CLKID_SPICC_DIV 137 1531.1Sskrll#define CLKID_SPICC_SEL2 138 1541.1Sskrll#define CLKID_TS_DIV 139 1551.1Sskrll#define CLKID_SPIFC_SEL 140 1561.1Sskrll#define CLKID_SPIFC_DIV 141 1571.1Sskrll#define CLKID_SPIFC_SEL2 142 1581.1Sskrll#define CLKID_USB_BUS_SEL 143 1591.1Sskrll#define CLKID_USB_BUS_DIV 144 1601.1Sskrll#define CLKID_SD_EMMC_SEL 145 1611.1Sskrll#define CLKID_SD_EMMC_DIV 146 1621.1Sskrll#define CLKID_SD_EMMC_SEL2 147 1631.1Sskrll#define CLKID_PSRAM_SEL 148 1641.1Sskrll#define CLKID_PSRAM_DIV 149 1651.1Sskrll#define CLKID_PSRAM_SEL2 150 1661.1Sskrll#define CLKID_DMC_SEL 151 1671.1Sskrll#define CLKID_DMC_DIV 152 1681.1Sskrll#define CLKID_DMC_SEL2 153 1691.1Sskrll#define CLKID_SYS_PLL_DIV16 154 1701.1Sskrll 1711.1Sskrll#endif /* __A1_PERIPHERALS_CLKC_H */ 172