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      1      1.1  jmcneill /*	$NetBSD: aspeed-clock.h,v 1.1.1.4 2020/01/03 14:33:05 skrll Exp $	*/
      2      1.1  jmcneill 
      3      1.1  jmcneill /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
      4      1.1  jmcneill 
      5      1.1  jmcneill #ifndef DT_BINDINGS_ASPEED_CLOCK_H
      6      1.1  jmcneill #define DT_BINDINGS_ASPEED_CLOCK_H
      7      1.1  jmcneill 
      8      1.1  jmcneill #define ASPEED_CLK_GATE_ECLK		0
      9      1.1  jmcneill #define ASPEED_CLK_GATE_GCLK		1
     10      1.1  jmcneill #define ASPEED_CLK_GATE_MCLK		2
     11      1.1  jmcneill #define ASPEED_CLK_GATE_VCLK		3
     12      1.1  jmcneill #define ASPEED_CLK_GATE_BCLK		4
     13      1.1  jmcneill #define ASPEED_CLK_GATE_DCLK		5
     14      1.1  jmcneill #define ASPEED_CLK_GATE_REFCLK		6
     15      1.1  jmcneill #define ASPEED_CLK_GATE_USBPORT2CLK	7
     16      1.1  jmcneill #define ASPEED_CLK_GATE_LCLK		8
     17      1.1  jmcneill #define ASPEED_CLK_GATE_USBUHCICLK	9
     18      1.1  jmcneill #define ASPEED_CLK_GATE_D1CLK		10
     19      1.1  jmcneill #define ASPEED_CLK_GATE_YCLK		11
     20      1.1  jmcneill #define ASPEED_CLK_GATE_USBPORT1CLK	12
     21      1.1  jmcneill #define ASPEED_CLK_GATE_UART1CLK	13
     22      1.1  jmcneill #define ASPEED_CLK_GATE_UART2CLK	14
     23      1.1  jmcneill #define ASPEED_CLK_GATE_UART5CLK	15
     24      1.1  jmcneill #define ASPEED_CLK_GATE_ESPICLK		16
     25      1.1  jmcneill #define ASPEED_CLK_GATE_MAC1CLK		17
     26      1.1  jmcneill #define ASPEED_CLK_GATE_MAC2CLK		18
     27      1.1  jmcneill #define ASPEED_CLK_GATE_RSACLK		19
     28      1.1  jmcneill #define ASPEED_CLK_GATE_UART3CLK	20
     29      1.1  jmcneill #define ASPEED_CLK_GATE_UART4CLK	21
     30  1.1.1.3  jmcneill #define ASPEED_CLK_GATE_SDCLK		22
     31      1.1  jmcneill #define ASPEED_CLK_GATE_LHCCLK		23
     32      1.1  jmcneill #define ASPEED_CLK_HPLL			24
     33      1.1  jmcneill #define ASPEED_CLK_AHB			25
     34      1.1  jmcneill #define ASPEED_CLK_APB			26
     35      1.1  jmcneill #define ASPEED_CLK_UART			27
     36      1.1  jmcneill #define ASPEED_CLK_SDIO			28
     37      1.1  jmcneill #define ASPEED_CLK_ECLK			29
     38      1.1  jmcneill #define ASPEED_CLK_ECLK_MUX		30
     39      1.1  jmcneill #define ASPEED_CLK_LHCLK		31
     40      1.1  jmcneill #define ASPEED_CLK_MAC			32
     41      1.1  jmcneill #define ASPEED_CLK_BCLK			33
     42      1.1  jmcneill #define ASPEED_CLK_MPLL			34
     43  1.1.1.2  jmcneill #define ASPEED_CLK_24M			35
     44  1.1.1.4     skrll #define ASPEED_CLK_MAC1RCLK		36
     45  1.1.1.4     skrll #define ASPEED_CLK_MAC2RCLK		37
     46      1.1  jmcneill 
     47      1.1  jmcneill #define ASPEED_RESET_XDMA		0
     48      1.1  jmcneill #define ASPEED_RESET_MCTP		1
     49      1.1  jmcneill #define ASPEED_RESET_ADC		2
     50      1.1  jmcneill #define ASPEED_RESET_JTAG_MASTER	3
     51      1.1  jmcneill #define ASPEED_RESET_MIC		4
     52      1.1  jmcneill #define ASPEED_RESET_PWM		5
     53  1.1.1.2  jmcneill #define ASPEED_RESET_PECI		6
     54      1.1  jmcneill #define ASPEED_RESET_I2C		7
     55      1.1  jmcneill #define ASPEED_RESET_AHB		8
     56  1.1.1.2  jmcneill #define ASPEED_RESET_CRT1		9
     57      1.1  jmcneill 
     58      1.1  jmcneill #endif
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