1 /* $NetBSD: aspeed-clock.h,v 1.1 2018/04/28 18:25:53 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 4 5 #ifndef DT_BINDINGS_ASPEED_CLOCK_H 6 #define DT_BINDINGS_ASPEED_CLOCK_H 7 8 #define ASPEED_CLK_GATE_ECLK 0 9 #define ASPEED_CLK_GATE_GCLK 1 10 #define ASPEED_CLK_GATE_MCLK 2 11 #define ASPEED_CLK_GATE_VCLK 3 12 #define ASPEED_CLK_GATE_BCLK 4 13 #define ASPEED_CLK_GATE_DCLK 5 14 #define ASPEED_CLK_GATE_REFCLK 6 15 #define ASPEED_CLK_GATE_USBPORT2CLK 7 16 #define ASPEED_CLK_GATE_LCLK 8 17 #define ASPEED_CLK_GATE_USBUHCICLK 9 18 #define ASPEED_CLK_GATE_D1CLK 10 19 #define ASPEED_CLK_GATE_YCLK 11 20 #define ASPEED_CLK_GATE_USBPORT1CLK 12 21 #define ASPEED_CLK_GATE_UART1CLK 13 22 #define ASPEED_CLK_GATE_UART2CLK 14 23 #define ASPEED_CLK_GATE_UART5CLK 15 24 #define ASPEED_CLK_GATE_ESPICLK 16 25 #define ASPEED_CLK_GATE_MAC1CLK 17 26 #define ASPEED_CLK_GATE_MAC2CLK 18 27 #define ASPEED_CLK_GATE_RSACLK 19 28 #define ASPEED_CLK_GATE_UART3CLK 20 29 #define ASPEED_CLK_GATE_UART4CLK 21 30 #define ASPEED_CLK_GATE_SDCLKCLK 22 31 #define ASPEED_CLK_GATE_LHCCLK 23 32 #define ASPEED_CLK_HPLL 24 33 #define ASPEED_CLK_AHB 25 34 #define ASPEED_CLK_APB 26 35 #define ASPEED_CLK_UART 27 36 #define ASPEED_CLK_SDIO 28 37 #define ASPEED_CLK_ECLK 29 38 #define ASPEED_CLK_ECLK_MUX 30 39 #define ASPEED_CLK_LHCLK 31 40 #define ASPEED_CLK_MAC 32 41 #define ASPEED_CLK_BCLK 33 42 #define ASPEED_CLK_MPLL 34 43 44 #define ASPEED_RESET_XDMA 0 45 #define ASPEED_RESET_MCTP 1 46 #define ASPEED_RESET_ADC 2 47 #define ASPEED_RESET_JTAG_MASTER 3 48 #define ASPEED_RESET_MIC 4 49 #define ASPEED_RESET_PWM 5 50 #define ASPEED_RESET_PCIVGA 6 51 #define ASPEED_RESET_I2C 7 52 #define ASPEED_RESET_AHB 8 53 54 #endif 55