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      1  1.1  jmcneill /*	$NetBSD: bcm63268-clock.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /* SPDX-License-Identifier: GPL-2.0+ */
      4  1.1  jmcneill 
      5  1.1  jmcneill #ifndef __DT_BINDINGS_CLOCK_BCM63268_H
      6  1.1  jmcneill #define __DT_BINDINGS_CLOCK_BCM63268_H
      7  1.1  jmcneill 
      8  1.1  jmcneill #define BCM63268_CLK_DIS_GLESS	0
      9  1.1  jmcneill #define BCM63268_CLK_VDSL_QPROC	1
     10  1.1  jmcneill #define BCM63268_CLK_VDSL_AFE	2
     11  1.1  jmcneill #define BCM63268_CLK_VDSL	3
     12  1.1  jmcneill #define BCM63268_CLK_MIPS	4
     13  1.1  jmcneill #define BCM63268_CLK_WLAN_OCP	5
     14  1.1  jmcneill #define BCM63268_CLK_DECT	6
     15  1.1  jmcneill #define BCM63268_CLK_FAP0	7
     16  1.1  jmcneill #define BCM63268_CLK_FAP1	8
     17  1.1  jmcneill #define BCM63268_CLK_SAR	9
     18  1.1  jmcneill #define BCM63268_CLK_ROBOSW	10
     19  1.1  jmcneill #define BCM63268_CLK_PCM	11
     20  1.1  jmcneill #define BCM63268_CLK_USBD	12
     21  1.1  jmcneill #define BCM63268_CLK_USBH	13
     22  1.1  jmcneill #define BCM63268_CLK_IPSEC	14
     23  1.1  jmcneill #define BCM63268_CLK_SPI	15
     24  1.1  jmcneill #define BCM63268_CLK_HSSPI	16
     25  1.1  jmcneill #define BCM63268_CLK_PCIE	17
     26  1.1  jmcneill #define BCM63268_CLK_PHYMIPS	18
     27  1.1  jmcneill #define BCM63268_CLK_GMAC	19
     28  1.1  jmcneill #define BCM63268_CLK_NAND	20
     29  1.1  jmcneill #define BCM63268_CLK_TBUS	27
     30  1.1  jmcneill #define BCM63268_CLK_ROBOSW250	31
     31  1.1  jmcneill 
     32  1.1  jmcneill #endif /* __DT_BINDINGS_CLOCK_BCM63268_H */
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