exynos3250.h revision 1.1.1.1.6.2
1 /* $NetBSD: exynos3250.h,v 1.1.1.1.6.2 2017/08/28 17:53:00 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * Author: Tomasz Figa <t.figa (at) samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Device Tree binding constants for Samsung Exynos3250 clock controllers. 12 */ 13 14 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 15 #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 16 17 /* 18 * Let each exported clock get a unique index, which is used on DT-enabled 19 * platforms to lookup the clock from a clock specifier. These indices are 20 * therefore considered an ABI and so must not be changed. This implies 21 * that new clocks should be added either in free spaces between clock groups 22 * or at the end. 23 */ 24 25 26 /* 27 * Main CMU 28 */ 29 30 #define CLK_OSCSEL 1 31 #define CLK_FIN_PLL 2 32 #define CLK_FOUT_APLL 3 33 #define CLK_FOUT_VPLL 4 34 #define CLK_FOUT_UPLL 5 35 #define CLK_FOUT_MPLL 6 36 #define CLK_ARM_CLK 7 37 38 /* Muxes */ 39 #define CLK_MOUT_MPLL_USER_L 16 40 #define CLK_MOUT_GDL 17 41 #define CLK_MOUT_MPLL_USER_R 18 42 #define CLK_MOUT_GDR 19 43 #define CLK_MOUT_EBI 20 44 #define CLK_MOUT_ACLK_200 21 45 #define CLK_MOUT_ACLK_160 22 46 #define CLK_MOUT_ACLK_100 23 47 #define CLK_MOUT_ACLK_266_1 24 48 #define CLK_MOUT_ACLK_266_0 25 49 #define CLK_MOUT_ACLK_266 26 50 #define CLK_MOUT_VPLL 27 51 #define CLK_MOUT_EPLL_USER 28 52 #define CLK_MOUT_EBI_1 29 53 #define CLK_MOUT_UPLL 30 54 #define CLK_MOUT_ACLK_400_MCUISP_SUB 31 55 #define CLK_MOUT_MPLL 32 56 #define CLK_MOUT_ACLK_400_MCUISP 33 57 #define CLK_MOUT_VPLLSRC 34 58 #define CLK_MOUT_CAM1 35 59 #define CLK_MOUT_CAM_BLK 36 60 #define CLK_MOUT_MFC 37 61 #define CLK_MOUT_MFC_1 38 62 #define CLK_MOUT_MFC_0 39 63 #define CLK_MOUT_G3D 40 64 #define CLK_MOUT_G3D_1 41 65 #define CLK_MOUT_G3D_0 42 66 #define CLK_MOUT_MIPI0 43 67 #define CLK_MOUT_FIMD0 44 68 #define CLK_MOUT_UART_ISP 45 69 #define CLK_MOUT_SPI1_ISP 46 70 #define CLK_MOUT_SPI0_ISP 47 71 #define CLK_MOUT_TSADC 48 72 #define CLK_MOUT_MMC1 49 73 #define CLK_MOUT_MMC0 50 74 #define CLK_MOUT_UART1 51 75 #define CLK_MOUT_UART0 52 76 #define CLK_MOUT_SPI1 53 77 #define CLK_MOUT_SPI0 54 78 #define CLK_MOUT_AUDIO 55 79 #define CLK_MOUT_MPLL_USER_C 56 80 #define CLK_MOUT_HPM 57 81 #define CLK_MOUT_CORE 58 82 #define CLK_MOUT_APLL 59 83 #define CLK_MOUT_ACLK_266_SUB 60 84 #define CLK_MOUT_UART2 61 85 #define CLK_MOUT_MMC2 62 86 87 /* Dividers */ 88 #define CLK_DIV_GPL 64 89 #define CLK_DIV_GDL 65 90 #define CLK_DIV_GPR 66 91 #define CLK_DIV_GDR 67 92 #define CLK_DIV_MPLL_PRE 68 93 #define CLK_DIV_ACLK_400_MCUISP 69 94 #define CLK_DIV_EBI 70 95 #define CLK_DIV_ACLK_200 71 96 #define CLK_DIV_ACLK_160 72 97 #define CLK_DIV_ACLK_100 73 98 #define CLK_DIV_ACLK_266 74 99 #define CLK_DIV_CAM1 75 100 #define CLK_DIV_CAM_BLK 76 101 #define CLK_DIV_MFC 77 102 #define CLK_DIV_G3D 78 103 #define CLK_DIV_MIPI0_PRE 79 104 #define CLK_DIV_MIPI0 80 105 #define CLK_DIV_FIMD0 81 106 #define CLK_DIV_UART_ISP 82 107 #define CLK_DIV_SPI1_ISP_PRE 83 108 #define CLK_DIV_SPI1_ISP 84 109 #define CLK_DIV_SPI0_ISP_PRE 85 110 #define CLK_DIV_SPI0_ISP 86 111 #define CLK_DIV_TSADC_PRE 87 112 #define CLK_DIV_TSADC 88 113 #define CLK_DIV_MMC1_PRE 89 114 #define CLK_DIV_MMC1 90 115 #define CLK_DIV_MMC0_PRE 91 116 #define CLK_DIV_MMC0 92 117 #define CLK_DIV_UART1 93 118 #define CLK_DIV_UART0 94 119 #define CLK_DIV_SPI1_PRE 95 120 #define CLK_DIV_SPI1 96 121 #define CLK_DIV_SPI0_PRE 97 122 #define CLK_DIV_SPI0 98 123 #define CLK_DIV_PCM 99 124 #define CLK_DIV_AUDIO 100 125 #define CLK_DIV_I2S 101 126 #define CLK_DIV_CORE2 102 127 #define CLK_DIV_APLL 103 128 #define CLK_DIV_PCLK_DBG 104 129 #define CLK_DIV_ATB 105 130 #define CLK_DIV_COREM 106 131 #define CLK_DIV_CORE 107 132 #define CLK_DIV_HPM 108 133 #define CLK_DIV_COPY 109 134 #define CLK_DIV_UART2 110 135 #define CLK_DIV_MMC2_PRE 111 136 #define CLK_DIV_MMC2 112 137 138 /* Gates */ 139 #define CLK_ASYNC_G3D 128 140 #define CLK_ASYNC_MFCL 129 141 #define CLK_PPMULEFT 130 142 #define CLK_GPIO_LEFT 131 143 #define CLK_ASYNC_ISPMX 132 144 #define CLK_ASYNC_FSYSD 133 145 #define CLK_ASYNC_LCD0X 134 146 #define CLK_ASYNC_CAMX 135 147 #define CLK_PPMURIGHT 136 148 #define CLK_GPIO_RIGHT 137 149 #define CLK_MONOCNT 138 150 #define CLK_TZPC6 139 151 #define CLK_PROVISIONKEY1 140 152 #define CLK_PROVISIONKEY0 141 153 #define CLK_CMU_ISPPART 142 154 #define CLK_TMU_APBIF 143 155 #define CLK_KEYIF 144 156 #define CLK_RTC 145 157 #define CLK_WDT 146 158 #define CLK_MCT 147 159 #define CLK_SECKEY 148 160 #define CLK_TZPC5 149 161 #define CLK_TZPC4 150 162 #define CLK_TZPC3 151 163 #define CLK_TZPC2 152 164 #define CLK_TZPC1 153 165 #define CLK_TZPC0 154 166 #define CLK_CMU_COREPART 155 167 #define CLK_CMU_TOPPART 156 168 #define CLK_PMU_APBIF 157 169 #define CLK_SYSREG 158 170 #define CLK_CHIP_ID 159 171 #define CLK_QEJPEG 160 172 #define CLK_PIXELASYNCM1 161 173 #define CLK_PIXELASYNCM0 162 174 #define CLK_PPMUCAMIF 163 175 #define CLK_QEM2MSCALER 164 176 #define CLK_QEGSCALER1 165 177 #define CLK_QEGSCALER0 166 178 #define CLK_SMMUJPEG 167 179 #define CLK_SMMUM2M2SCALER 168 180 #define CLK_SMMUGSCALER1 169 181 #define CLK_SMMUGSCALER0 170 182 #define CLK_JPEG 171 183 #define CLK_M2MSCALER 172 184 #define CLK_GSCALER1 173 185 #define CLK_GSCALER0 174 186 #define CLK_QEMFC 175 187 #define CLK_PPMUMFC_L 176 188 #define CLK_SMMUMFC_L 177 189 #define CLK_MFC 178 190 #define CLK_SMMUG3D 179 191 #define CLK_QEG3D 180 192 #define CLK_PPMUG3D 181 193 #define CLK_G3D 182 194 #define CLK_QE_CH1_LCD 183 195 #define CLK_QE_CH0_LCD 184 196 #define CLK_PPMULCD0 185 197 #define CLK_SMMUFIMD0 186 198 #define CLK_DSIM0 187 199 #define CLK_FIMD0 188 200 #define CLK_CAM1 189 201 #define CLK_UART_ISP_TOP 190 202 #define CLK_SPI1_ISP_TOP 191 203 #define CLK_SPI0_ISP_TOP 192 204 #define CLK_TSADC 193 205 #define CLK_PPMUFILE 194 206 #define CLK_USBOTG 195 207 #define CLK_USBHOST 196 208 #define CLK_SROMC 197 209 #define CLK_SDMMC1 198 210 #define CLK_SDMMC0 199 211 #define CLK_PDMA1 200 212 #define CLK_PDMA0 201 213 #define CLK_PWM 202 214 #define CLK_PCM 203 215 #define CLK_I2S 204 216 #define CLK_SPI1 205 217 #define CLK_SPI0 206 218 #define CLK_I2C7 207 219 #define CLK_I2C6 208 220 #define CLK_I2C5 209 221 #define CLK_I2C4 210 222 #define CLK_I2C3 211 223 #define CLK_I2C2 212 224 #define CLK_I2C1 213 225 #define CLK_I2C0 214 226 #define CLK_UART1 215 227 #define CLK_UART0 216 228 #define CLK_BLOCK_LCD 217 229 #define CLK_BLOCK_G3D 218 230 #define CLK_BLOCK_MFC 219 231 #define CLK_BLOCK_CAM 220 232 #define CLK_SMIES 221 233 #define CLK_UART2 222 234 #define CLK_SDMMC2 223 235 236 /* Special clocks */ 237 #define CLK_SCLK_JPEG 224 238 #define CLK_SCLK_M2MSCALER 225 239 #define CLK_SCLK_GSCALER1 226 240 #define CLK_SCLK_GSCALER0 227 241 #define CLK_SCLK_MFC 228 242 #define CLK_SCLK_G3D 229 243 #define CLK_SCLK_MIPIDPHY2L 230 244 #define CLK_SCLK_MIPI0 231 245 #define CLK_SCLK_FIMD0 232 246 #define CLK_SCLK_CAM1 233 247 #define CLK_SCLK_UART_ISP 234 248 #define CLK_SCLK_SPI1_ISP 235 249 #define CLK_SCLK_SPI0_ISP 236 250 #define CLK_SCLK_UPLL 237 251 #define CLK_SCLK_TSADC 238 252 #define CLK_SCLK_EBI 239 253 #define CLK_SCLK_MMC1 240 254 #define CLK_SCLK_MMC0 241 255 #define CLK_SCLK_I2S 242 256 #define CLK_SCLK_PCM 243 257 #define CLK_SCLK_SPI1 244 258 #define CLK_SCLK_SPI0 245 259 #define CLK_SCLK_UART1 246 260 #define CLK_SCLK_UART0 247 261 #define CLK_SCLK_UART2 248 262 #define CLK_SCLK_MMC2 249 263 264 /* 265 * Total number of clocks of main CMU. 266 * NOTE: Must be equal to last clock ID increased by one. 267 */ 268 #define CLK_NR_CLKS 250 269 270 /* 271 * CMU DMC 272 */ 273 274 #define CLK_FOUT_BPLL 1 275 #define CLK_FOUT_EPLL 2 276 277 /* Muxes */ 278 #define CLK_MOUT_MPLL_MIF 8 279 #define CLK_MOUT_BPLL 9 280 #define CLK_MOUT_DPHY 10 281 #define CLK_MOUT_DMC_BUS 11 282 #define CLK_MOUT_EPLL 12 283 284 /* Dividers */ 285 #define CLK_DIV_DMC 16 286 #define CLK_DIV_DPHY 17 287 #define CLK_DIV_DMC_PRE 18 288 #define CLK_DIV_DMCP 19 289 #define CLK_DIV_DMCD 20 290 291 /* 292 * Total number of clocks of main CMU. 293 * NOTE: Must be equal to last clock ID increased by one. 294 */ 295 #define NR_CLKS_DMC 21 296 297 /* 298 * CMU ISP 299 */ 300 301 /* Dividers */ 302 303 #define CLK_DIV_ISP1 1 304 #define CLK_DIV_ISP0 2 305 #define CLK_DIV_MCUISP1 3 306 #define CLK_DIV_MCUISP0 4 307 #define CLK_DIV_MPWM 5 308 309 /* Gates */ 310 311 #define CLK_UART_ISP 8 312 #define CLK_WDT_ISP 9 313 #define CLK_PWM_ISP 10 314 #define CLK_I2C1_ISP 11 315 #define CLK_I2C0_ISP 12 316 #define CLK_MPWM_ISP 13 317 #define CLK_MCUCTL_ISP 14 318 #define CLK_PPMUISPX 15 319 #define CLK_PPMUISPMX 16 320 #define CLK_QE_LITE1 17 321 #define CLK_QE_LITE0 18 322 #define CLK_QE_FD 19 323 #define CLK_QE_DRC 20 324 #define CLK_QE_ISP 21 325 #define CLK_CSIS1 22 326 #define CLK_SMMU_LITE1 23 327 #define CLK_SMMU_LITE0 24 328 #define CLK_SMMU_FD 25 329 #define CLK_SMMU_DRC 26 330 #define CLK_SMMU_ISP 27 331 #define CLK_GICISP 28 332 #define CLK_CSIS0 29 333 #define CLK_MCUISP 30 334 #define CLK_LITE1 31 335 #define CLK_LITE0 32 336 #define CLK_FD 33 337 #define CLK_DRC 34 338 #define CLK_ISP 35 339 #define CLK_QE_ISPCX 36 340 #define CLK_QE_SCALERP 37 341 #define CLK_QE_SCALERC 38 342 #define CLK_SMMU_SCALERP 39 343 #define CLK_SMMU_SCALERC 40 344 #define CLK_SCALERP 41 345 #define CLK_SCALERC 42 346 #define CLK_SPI1_ISP 43 347 #define CLK_SPI0_ISP 44 348 #define CLK_SMMU_ISPCX 45 349 #define CLK_ASYNCAXIM 46 350 #define CLK_SCLK_MPWM_ISP 47 351 352 /* 353 * Total number of clocks of CMU_ISP. 354 * NOTE: Must be equal to last clock ID increased by one. 355 */ 356 #define NR_CLKS_ISP 48 357 358 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ 359
Indexes created Sun Oct 19 02:09:48 GMT 2025