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exynos5260-clk.h revision 1.1.1.1.8.2
      1 /*	$NetBSD: exynos5260-clk.h,v 1.1.1.1.8.2 2017/12/03 11:38:35 jdolecek Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
      5  * Author: Rahul Sharma <rahul.sharma (at) samsung.com>
      6  *
      7  * This program is free software; you can redistribute it and/or modify
      8  * it under the terms of the GNU General Public License version 2 as
      9  * published by the Free Software Foundation.
     10  *
     11  * Provides Constants for Exynos5260 clocks.
     12 */
     13 
     14 #ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
     15 #define _DT_BINDINGS_CLK_EXYNOS5260_H
     16 
     17 /* Clock names: <cmu><type><IP> */
     18 
     19 /* List Of Clocks For CMU_TOP */
     20 
     21 #define TOP_FOUT_DISP_PLL				1
     22 #define TOP_FOUT_AUD_PLL				2
     23 #define TOP_MOUT_AUDTOP_PLL_USER			3
     24 #define TOP_MOUT_AUD_PLL				4
     25 #define TOP_MOUT_DISP_PLL				5
     26 #define TOP_MOUT_BUSTOP_PLL_USER			6
     27 #define TOP_MOUT_MEMTOP_PLL_USER			7
     28 #define TOP_MOUT_MEDIATOP_PLL_USER			8
     29 #define TOP_MOUT_DISP_DISP_333				9
     30 #define TOP_MOUT_ACLK_DISP_333				10
     31 #define TOP_MOUT_DISP_DISP_222				11
     32 #define TOP_MOUT_ACLK_DISP_222				12
     33 #define TOP_MOUT_DISP_MEDIA_PIXEL			13
     34 #define TOP_MOUT_FIMD1					14
     35 #define TOP_MOUT_SCLK_PERI_SPI0_CLK			15
     36 #define TOP_MOUT_SCLK_PERI_SPI1_CLK			16
     37 #define TOP_MOUT_SCLK_PERI_SPI2_CLK			17
     38 #define TOP_MOUT_SCLK_PERI_UART0_UCLK			18
     39 #define TOP_MOUT_SCLK_PERI_UART2_UCLK			19
     40 #define TOP_MOUT_SCLK_PERI_UART1_UCLK			20
     41 #define TOP_MOUT_BUS4_BUSTOP_100			21
     42 #define TOP_MOUT_BUS4_BUSTOP_400			22
     43 #define TOP_MOUT_BUS3_BUSTOP_100			23
     44 #define TOP_MOUT_BUS3_BUSTOP_400			24
     45 #define TOP_MOUT_BUS2_BUSTOP_400			25
     46 #define TOP_MOUT_BUS2_BUSTOP_100			26
     47 #define TOP_MOUT_BUS1_BUSTOP_100			27
     48 #define TOP_MOUT_BUS1_BUSTOP_400			28
     49 #define TOP_MOUT_SCLK_FSYS_USB				29
     50 #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A		30
     51 #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A		31
     52 #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A		32
     53 #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B		33
     54 #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B		34
     55 #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B		35
     56 #define TOP_MOUT_ACLK_ISP1_266				36
     57 #define TOP_MOUT_ISP1_MEDIA_266				37
     58 #define TOP_MOUT_ACLK_ISP1_400				38
     59 #define TOP_MOUT_ISP1_MEDIA_400				39
     60 #define TOP_MOUT_SCLK_ISP1_SPI0				40
     61 #define TOP_MOUT_SCLK_ISP1_SPI1				41
     62 #define TOP_MOUT_SCLK_ISP1_UART				42
     63 #define TOP_MOUT_SCLK_ISP1_SENSOR2			43
     64 #define TOP_MOUT_SCLK_ISP1_SENSOR1			44
     65 #define TOP_MOUT_SCLK_ISP1_SENSOR0			45
     66 #define TOP_MOUT_ACLK_MFC_333				46
     67 #define TOP_MOUT_MFC_BUSTOP_333				47
     68 #define TOP_MOUT_ACLK_G2D_333				48
     69 #define TOP_MOUT_G2D_BUSTOP_333				49
     70 #define TOP_MOUT_ACLK_GSCL_FIMC				50
     71 #define TOP_MOUT_GSCL_BUSTOP_FIMC			51
     72 #define TOP_MOUT_ACLK_GSCL_333				52
     73 #define TOP_MOUT_GSCL_BUSTOP_333			53
     74 #define TOP_MOUT_ACLK_GSCL_400				54
     75 #define TOP_MOUT_M2M_MEDIATOP_400			55
     76 #define TOP_DOUT_ACLK_MFC_333				56
     77 #define TOP_DOUT_ACLK_G2D_333				57
     78 #define TOP_DOUT_SCLK_ISP1_SENSOR2_A			58
     79 #define TOP_DOUT_SCLK_ISP1_SENSOR1_A			59
     80 #define TOP_DOUT_SCLK_ISP1_SENSOR0_A			60
     81 #define TOP_DOUT_ACLK_GSCL_FIMC				61
     82 #define TOP_DOUT_ACLK_GSCL_400				62
     83 #define TOP_DOUT_ACLK_GSCL_333				63
     84 #define TOP_DOUT_SCLK_ISP1_SPI0_B			64
     85 #define TOP_DOUT_SCLK_ISP1_SPI0_A			65
     86 #define TOP_DOUT_ACLK_ISP1_400				66
     87 #define TOP_DOUT_ACLK_ISP1_266				67
     88 #define TOP_DOUT_SCLK_ISP1_UART				68
     89 #define TOP_DOUT_SCLK_ISP1_SPI1_B			69
     90 #define TOP_DOUT_SCLK_ISP1_SPI1_A			70
     91 #define TOP_DOUT_SCLK_ISP1_SENSOR2_B			71
     92 #define TOP_DOUT_SCLK_ISP1_SENSOR1_B			72
     93 #define TOP_DOUT_SCLK_ISP1_SENSOR0_B			73
     94 #define TOP_DOUTTOP__SCLK_HPM_TARGETCLK			74
     95 #define TOP_DOUT_SCLK_DISP_PIXEL			75
     96 #define TOP_DOUT_ACLK_DISP_222				76
     97 #define TOP_DOUT_ACLK_DISP_333				77
     98 #define TOP_DOUT_ACLK_BUS4_100				78
     99 #define TOP_DOUT_ACLK_BUS4_400				79
    100 #define TOP_DOUT_ACLK_BUS3_100				80
    101 #define TOP_DOUT_ACLK_BUS3_400				81
    102 #define TOP_DOUT_ACLK_BUS2_100				82
    103 #define TOP_DOUT_ACLK_BUS2_400				83
    104 #define TOP_DOUT_ACLK_BUS1_100				84
    105 #define TOP_DOUT_ACLK_BUS1_400				85
    106 #define TOP_DOUT_SCLK_PERI_SPI1_B			86
    107 #define TOP_DOUT_SCLK_PERI_SPI1_A			87
    108 #define TOP_DOUT_SCLK_PERI_SPI0_B			88
    109 #define TOP_DOUT_SCLK_PERI_SPI0_A			89
    110 #define TOP_DOUT_SCLK_PERI_UART0			90
    111 #define TOP_DOUT_SCLK_PERI_UART2			91
    112 #define TOP_DOUT_SCLK_PERI_UART1			92
    113 #define TOP_DOUT_SCLK_PERI_SPI2_B			93
    114 #define TOP_DOUT_SCLK_PERI_SPI2_A			94
    115 #define TOP_DOUT_ACLK_PERI_AUD				95
    116 #define TOP_DOUT_ACLK_PERI_66				96
    117 #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B		97
    118 #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A		98
    119 #define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK		99
    120 #define TOP_DOUT_ACLK_FSYS_200				100
    121 #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B		101
    122 #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A		102
    123 #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B		103
    124 #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A		104
    125 #define TOP_SCLK_FIMD1					105
    126 #define TOP_SCLK_MMC2					106
    127 #define TOP_SCLK_MMC1					107
    128 #define TOP_SCLK_MMC0					108
    129 #define PHYCLK_DPTX_PHY_CH3_TXD_CLK			109
    130 #define PHYCLK_DPTX_PHY_CH2_TXD_CLK			110
    131 #define PHYCLK_DPTX_PHY_CH1_TXD_CLK			111
    132 #define PHYCLK_DPTX_PHY_CH0_TXD_CLK			112
    133 #define phyclk_hdmi_phy_tmds_clko			113
    134 #define PHYCLK_HDMI_PHY_PIXEL_CLKO			114
    135 #define PHYCLK_HDMI_LINK_O_TMDS_CLKHI			115
    136 #define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS		116
    137 #define PHYCLK_DPTX_PHY_O_REF_CLK_24M			117
    138 #define PHYCLK_DPTX_PHY_CLK_DIV2			118
    139 #define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0			119
    140 #define PHYCLK_USBHOST20_PHY_PHYCLOCK			120
    141 #define PHYCLK_USBHOST20_PHY_FREECLK			121
    142 #define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122
    143 #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123
    144 #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124
    145 #define TOP_NR_CLK					125
    146 
    147 
    148 /* List Of Clocks For CMU_EGL */
    149 
    150 #define EGL_FOUT_EGL_PLL				1
    151 #define EGL_FOUT_EGL_DPLL				2
    152 #define EGL_MOUT_EGL_B					3
    153 #define EGL_MOUT_EGL_PLL				4
    154 #define EGL_DOUT_EGL_PLL				5
    155 #define EGL_DOUT_EGL_PCLK_DBG				6
    156 #define EGL_DOUT_EGL_ATCLK				7
    157 #define EGL_DOUT_PCLK_EGL				8
    158 #define EGL_DOUT_ACLK_EGL				9
    159 #define EGL_DOUT_EGL2					10
    160 #define EGL_DOUT_EGL1					11
    161 #define EGL_NR_CLK					12
    162 
    163 
    164 /* List Of Clocks For CMU_KFC */
    165 
    166 #define KFC_FOUT_KFC_PLL				1
    167 #define KFC_MOUT_KFC_PLL				2
    168 #define KFC_MOUT_KFC					3
    169 #define KFC_DOUT_KFC_PLL				4
    170 #define KFC_DOUT_PCLK_KFC				5
    171 #define KFC_DOUT_ACLK_KFC				6
    172 #define KFC_DOUT_KFC_PCLK_DBG				7
    173 #define KFC_DOUT_KFC_ATCLK				8
    174 #define KFC_DOUT_KFC2					9
    175 #define KFC_DOUT_KFC1					10
    176 #define KFC_NR_CLK					11
    177 
    178 
    179 /* List Of Clocks For CMU_MIF */
    180 
    181 #define MIF_FOUT_MEM_PLL				1
    182 #define MIF_FOUT_MEDIA_PLL				2
    183 #define MIF_FOUT_BUS_PLL				3
    184 #define MIF_MOUT_CLK2X_PHY				4
    185 #define MIF_MOUT_MIF_DREX2X				5
    186 #define MIF_MOUT_CLKM_PHY				6
    187 #define MIF_MOUT_MIF_DREX				7
    188 #define MIF_MOUT_MEDIA_PLL				8
    189 #define MIF_MOUT_BUS_PLL				9
    190 #define MIF_MOUT_MEM_PLL				10
    191 #define MIF_DOUT_ACLK_BUS_100				11
    192 #define MIF_DOUT_ACLK_BUS_200				12
    193 #define MIF_DOUT_ACLK_MIF_466				13
    194 #define MIF_DOUT_CLK2X_PHY				14
    195 #define MIF_DOUT_CLKM_PHY				15
    196 #define MIF_DOUT_BUS_PLL				16
    197 #define MIF_DOUT_MEM_PLL				17
    198 #define MIF_DOUT_MEDIA_PLL				18
    199 #define MIF_CLK_LPDDR3PHY_WRAP1				19
    200 #define MIF_CLK_LPDDR3PHY_WRAP0				20
    201 #define MIF_CLK_MONOCNT					21
    202 #define MIF_CLK_MIF_RTC					22
    203 #define MIF_CLK_DREX1					23
    204 #define MIF_CLK_DREX0					24
    205 #define MIF_CLK_INTMEM					25
    206 #define MIF_SCLK_LPDDR3PHY_WRAP_U1			26
    207 #define MIF_SCLK_LPDDR3PHY_WRAP_U0			27
    208 #define MIF_NR_CLK					28
    209 
    210 
    211 /* List Of Clocks For CMU_G3D */
    212 
    213 #define G3D_FOUT_G3D_PLL				1
    214 #define G3D_MOUT_G3D_PLL				2
    215 #define G3D_DOUT_PCLK_G3D				3
    216 #define G3D_DOUT_ACLK_G3D				4
    217 #define G3D_CLK_G3D_HPM					5
    218 #define G3D_CLK_G3D					6
    219 #define G3D_NR_CLK					7
    220 
    221 
    222 /* List Of Clocks For CMU_AUD */
    223 
    224 #define AUD_MOUT_SCLK_AUD_PCM				1
    225 #define AUD_MOUT_SCLK_AUD_I2S				2
    226 #define AUD_MOUT_AUD_PLL_USER				3
    227 #define AUD_DOUT_ACLK_AUD_131				4
    228 #define AUD_DOUT_SCLK_AUD_UART				5
    229 #define AUD_DOUT_SCLK_AUD_PCM				6
    230 #define AUD_DOUT_SCLK_AUD_I2S				7
    231 #define AUD_CLK_AUD_UART				8
    232 #define AUD_CLK_PCM					9
    233 #define AUD_CLK_I2S					10
    234 #define AUD_CLK_DMAC					11
    235 #define AUD_CLK_SRAMC					12
    236 #define AUD_SCLK_AUD_UART				13
    237 #define AUD_SCLK_PCM					14
    238 #define AUD_SCLK_I2S					15
    239 #define AUD_NR_CLK					16
    240 
    241 
    242 /* List Of Clocks For CMU_MFC */
    243 
    244 #define MFC_MOUT_ACLK_MFC_333_USER			1
    245 #define MFC_DOUT_PCLK_MFC_83				2
    246 #define MFC_CLK_MFC					3
    247 #define MFC_CLK_SMMU2_MFCM1				4
    248 #define MFC_CLK_SMMU2_MFCM0				5
    249 #define MFC_NR_CLK					6
    250 
    251 
    252 /* List Of Clocks For CMU_GSCL */
    253 
    254 #define GSCL_MOUT_ACLK_CSIS				1
    255 #define GSCL_MOUT_ACLK_GSCL_FIMC_USER			2
    256 #define GSCL_MOUT_ACLK_M2M_400_USER			3
    257 #define GSCL_MOUT_ACLK_GSCL_333_USER			4
    258 #define GSCL_DOUT_ACLK_CSIS_200				5
    259 #define GSCL_DOUT_PCLK_M2M_100				6
    260 #define GSCL_CLK_PIXEL_GSCL1				7
    261 #define GSCL_CLK_PIXEL_GSCL0				8
    262 #define GSCL_CLK_MSCL1					9
    263 #define GSCL_CLK_MSCL0					10
    264 #define GSCL_CLK_GSCL1					11
    265 #define GSCL_CLK_GSCL0					12
    266 #define GSCL_CLK_FIMC_LITE_D				13
    267 #define GSCL_CLK_FIMC_LITE_B				14
    268 #define GSCL_CLK_FIMC_LITE_A				15
    269 #define GSCL_CLK_CSIS1					16
    270 #define GSCL_CLK_CSIS0					17
    271 #define GSCL_CLK_SMMU3_LITE_D				18
    272 #define GSCL_CLK_SMMU3_LITE_B				19
    273 #define GSCL_CLK_SMMU3_LITE_A				20
    274 #define GSCL_CLK_SMMU3_GSCL0				21
    275 #define GSCL_CLK_SMMU3_GSCL1				22
    276 #define GSCL_CLK_SMMU3_MSCL0				23
    277 #define GSCL_CLK_SMMU3_MSCL1				24
    278 #define GSCL_SCLK_CSIS1_WRAP				25
    279 #define GSCL_SCLK_CSIS0_WRAP				26
    280 #define GSCL_NR_CLK					27
    281 
    282 
    283 /* List Of Clocks For CMU_FSYS */
    284 
    285 #define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER		1
    286 #define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER		2
    287 #define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER	3
    288 #define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER	4
    289 #define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER		5
    290 #define FSYS_CLK_TSI					6
    291 #define FSYS_CLK_USBLINK				7
    292 #define FSYS_CLK_USBHOST20				8
    293 #define FSYS_CLK_USBDRD30				9
    294 #define FSYS_CLK_SROMC					10
    295 #define FSYS_CLK_PDMA					11
    296 #define FSYS_CLK_MMC2					12
    297 #define FSYS_CLK_MMC1					13
    298 #define FSYS_CLK_MMC0					14
    299 #define FSYS_CLK_RTIC					15
    300 #define FSYS_CLK_SMMU_RTIC				16
    301 #define FSYS_PHYCLK_USBDRD30				17
    302 #define FSYS_PHYCLK_USBHOST20				18
    303 #define FSYS_NR_CLK					19
    304 
    305 
    306 /* List Of Clocks For CMU_PERI */
    307 
    308 #define PERI_MOUT_SCLK_SPDIF				1
    309 #define PERI_MOUT_SCLK_I2SCOD				2
    310 #define PERI_MOUT_SCLK_PCM				3
    311 #define PERI_DOUT_I2S					4
    312 #define PERI_DOUT_PCM					5
    313 #define PERI_CLK_WDT_KFC				6
    314 #define PERI_CLK_WDT_EGL				7
    315 #define PERI_CLK_HSIC3					8
    316 #define PERI_CLK_HSIC2					9
    317 #define PERI_CLK_HSIC1					10
    318 #define PERI_CLK_HSIC0					11
    319 #define PERI_CLK_PCM					12
    320 #define PERI_CLK_MCT					13
    321 #define PERI_CLK_I2S					14
    322 #define PERI_CLK_I2CHDMI				15
    323 #define PERI_CLK_I2C7					16
    324 #define PERI_CLK_I2C6					17
    325 #define PERI_CLK_I2C5					18
    326 #define PERI_CLK_I2C4					19
    327 #define PERI_CLK_I2C9					20
    328 #define PERI_CLK_I2C8					21
    329 #define PERI_CLK_I2C11					22
    330 #define PERI_CLK_I2C10					23
    331 #define PERI_CLK_HDMICEC				24
    332 #define PERI_CLK_EFUSE_WRITER				25
    333 #define PERI_CLK_ABB					26
    334 #define PERI_CLK_UART2					27
    335 #define PERI_CLK_UART1					28
    336 #define PERI_CLK_UART0					29
    337 #define PERI_CLK_ADC					30
    338 #define PERI_CLK_TMU4					31
    339 #define PERI_CLK_TMU3					32
    340 #define PERI_CLK_TMU2					33
    341 #define PERI_CLK_TMU1					34
    342 #define PERI_CLK_TMU0					35
    343 #define PERI_CLK_SPI2					36
    344 #define PERI_CLK_SPI1					37
    345 #define PERI_CLK_SPI0					38
    346 #define PERI_CLK_SPDIF					39
    347 #define PERI_CLK_PWM					40
    348 #define PERI_CLK_UART4					41
    349 #define PERI_CLK_CHIPID					42
    350 #define PERI_CLK_PROVKEY0				43
    351 #define PERI_CLK_PROVKEY1				44
    352 #define PERI_CLK_SECKEY					45
    353 #define PERI_CLK_TOP_RTC				46
    354 #define PERI_CLK_TZPC10					47
    355 #define PERI_CLK_TZPC9					48
    356 #define PERI_CLK_TZPC8					49
    357 #define PERI_CLK_TZPC7					50
    358 #define PERI_CLK_TZPC6					51
    359 #define PERI_CLK_TZPC5					52
    360 #define PERI_CLK_TZPC4					53
    361 #define PERI_CLK_TZPC3					54
    362 #define PERI_CLK_TZPC2					55
    363 #define PERI_CLK_TZPC1					56
    364 #define PERI_CLK_TZPC0					57
    365 #define PERI_SCLK_UART2					58
    366 #define PERI_SCLK_UART1					59
    367 #define PERI_SCLK_UART0					60
    368 #define PERI_SCLK_SPI2					61
    369 #define PERI_SCLK_SPI1					62
    370 #define PERI_SCLK_SPI0					63
    371 #define PERI_SCLK_SPDIF					64
    372 #define PERI_SCLK_I2S					65
    373 #define PERI_SCLK_PCM1					66
    374 #define PERI_NR_CLK					67
    375 
    376 
    377 /* List Of Clocks For CMU_DISP */
    378 
    379 #define DISP_MOUT_SCLK_HDMI_SPDIF			1
    380 #define DISP_MOUT_SCLK_HDMI_PIXEL			2
    381 #define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER	3
    382 #define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER	4
    383 #define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER		5
    384 #define DISP_MOUT_HDMI_PHY_PIXEL			6
    385 #define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER	7
    386 #define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS	8
    387 #define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER	9
    388 #define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER		10
    389 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER	11
    390 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER	12
    391 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER	13
    392 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER	14
    393 #define DISP_MOUT_ACLK_DISP_222_USER			15
    394 #define DISP_MOUT_SCLK_DISP_PIXEL_USER			16
    395 #define DISP_MOUT_ACLK_DISP_333_USER			17
    396 #define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI		18
    397 #define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL			19
    398 #define DISP_DOUT_PCLK_DISP_111				20
    399 #define DISP_CLK_SMMU_TV				21
    400 #define DISP_CLK_SMMU_FIMD1M1				22
    401 #define DISP_CLK_SMMU_FIMD1M0				23
    402 #define DISP_CLK_PIXEL_MIXER				24
    403 #define DISP_CLK_PIXEL_DISP				25
    404 #define DISP_CLK_MIXER					26
    405 #define DISP_CLK_MIPIPHY				27
    406 #define DISP_CLK_HDMIPHY				28
    407 #define DISP_CLK_HDMI					29
    408 #define DISP_CLK_FIMD1					30
    409 #define DISP_CLK_DSIM1					31
    410 #define DISP_CLK_DPPHY					32
    411 #define DISP_CLK_DP					33
    412 #define DISP_SCLK_PIXEL					34
    413 #define DISP_MOUT_HDMI_PHY_PIXEL_USER			35
    414 #define DISP_NR_CLK					36
    415 
    416 
    417 /* List Of Clocks For CMU_G2D */
    418 
    419 #define G2D_MOUT_ACLK_G2D_333_USER			1
    420 #define G2D_DOUT_PCLK_G2D_83				2
    421 #define G2D_CLK_SMMU3_JPEG				3
    422 #define G2D_CLK_MDMA					4
    423 #define G2D_CLK_JPEG					5
    424 #define G2D_CLK_G2D					6
    425 #define G2D_CLK_SSS					7
    426 #define G2D_CLK_SLIM_SSS				8
    427 #define G2D_CLK_SMMU_SLIM_SSS				9
    428 #define G2D_CLK_SMMU_SSS				10
    429 #define G2D_CLK_SMMU_MDMA				11
    430 #define G2D_CLK_SMMU3_G2D				12
    431 #define G2D_NR_CLK					13
    432 
    433 
    434 /* List Of Clocks For CMU_ISP */
    435 
    436 #define ISP_MOUT_ISP_400_USER				1
    437 #define ISP_MOUT_ISP_266_USER				2
    438 #define ISP_DOUT_SCLK_MPWM				3
    439 #define ISP_DOUT_CA5_PCLKDBG				4
    440 #define ISP_DOUT_CA5_ATCLKIN				5
    441 #define ISP_DOUT_PCLK_ISP_133				6
    442 #define ISP_DOUT_PCLK_ISP_66				7
    443 #define ISP_CLK_GIC					8
    444 #define ISP_CLK_WDT					9
    445 #define ISP_CLK_UART					10
    446 #define ISP_CLK_SPI1					11
    447 #define ISP_CLK_SPI0					12
    448 #define ISP_CLK_SMMU_SCALERP				13
    449 #define ISP_CLK_SMMU_SCALERC				14
    450 #define ISP_CLK_SMMU_ISPCX				15
    451 #define ISP_CLK_SMMU_ISP				16
    452 #define ISP_CLK_SMMU_FD					17
    453 #define ISP_CLK_SMMU_DRC				18
    454 #define ISP_CLK_PWM					19
    455 #define ISP_CLK_MTCADC					20
    456 #define ISP_CLK_MPWM					21
    457 #define ISP_CLK_MCUCTL					22
    458 #define ISP_CLK_I2C1					23
    459 #define ISP_CLK_I2C0					24
    460 #define ISP_CLK_FIMC_SCALERP				25
    461 #define ISP_CLK_FIMC_SCALERC				26
    462 #define ISP_CLK_FIMC					27
    463 #define ISP_CLK_FIMC_FD					28
    464 #define ISP_CLK_FIMC_DRC				29
    465 #define ISP_CLK_CA5					30
    466 #define ISP_SCLK_SPI0_EXT				31
    467 #define ISP_SCLK_SPI1_EXT				32
    468 #define ISP_SCLK_UART_EXT				33
    469 #define ISP_NR_CLK					34
    470 
    471 #endif
    472