Home | History | Annotate | Line # | Download | only in clock
      1      1.1  jmcneill /*	$NetBSD: exynos5433.h,v 1.1.1.3 2019/05/25 11:29:13 jmcneill Exp $	*/
      2      1.1  jmcneill 
      3  1.1.1.2  jmcneill /* SPDX-License-Identifier: GPL-2.0 */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
      6      1.1  jmcneill  * Author: Chanwoo Choi <cw00.choi (at) samsung.com>
      7      1.1  jmcneill  */
      8      1.1  jmcneill 
      9      1.1  jmcneill #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
     10      1.1  jmcneill #define _DT_BINDINGS_CLOCK_EXYNOS5433_H
     11      1.1  jmcneill 
     12      1.1  jmcneill /* CMU_TOP */
     13      1.1  jmcneill #define CLK_FOUT_ISP_PLL		1
     14      1.1  jmcneill #define CLK_FOUT_AUD_PLL		2
     15      1.1  jmcneill 
     16      1.1  jmcneill #define CLK_MOUT_AUD_PLL		10
     17      1.1  jmcneill #define CLK_MOUT_ISP_PLL		11
     18      1.1  jmcneill #define CLK_MOUT_AUD_PLL_USER_T		12
     19      1.1  jmcneill #define CLK_MOUT_MPHY_PLL_USER		13
     20      1.1  jmcneill #define CLK_MOUT_MFC_PLL_USER		14
     21      1.1  jmcneill #define CLK_MOUT_BUS_PLL_USER		15
     22      1.1  jmcneill #define CLK_MOUT_ACLK_HEVC_400		16
     23      1.1  jmcneill #define CLK_MOUT_ACLK_CAM1_333		17
     24      1.1  jmcneill #define CLK_MOUT_ACLK_CAM1_552_B	18
     25      1.1  jmcneill #define CLK_MOUT_ACLK_CAM1_552_A	19
     26      1.1  jmcneill #define CLK_MOUT_ACLK_ISP_DIS_400	20
     27      1.1  jmcneill #define CLK_MOUT_ACLK_ISP_400		21
     28      1.1  jmcneill #define CLK_MOUT_ACLK_BUS0_400		22
     29      1.1  jmcneill #define CLK_MOUT_ACLK_MSCL_400_B	23
     30      1.1  jmcneill #define CLK_MOUT_ACLK_MSCL_400_A	24
     31      1.1  jmcneill #define CLK_MOUT_ACLK_GSCL_333		25
     32      1.1  jmcneill #define CLK_MOUT_ACLK_G2D_400_B		26
     33      1.1  jmcneill #define CLK_MOUT_ACLK_G2D_400_A		27
     34      1.1  jmcneill #define CLK_MOUT_SCLK_JPEG_C		28
     35      1.1  jmcneill #define CLK_MOUT_SCLK_JPEG_B		29
     36      1.1  jmcneill #define CLK_MOUT_SCLK_JPEG_A		30
     37      1.1  jmcneill #define CLK_MOUT_SCLK_MMC2_B		31
     38      1.1  jmcneill #define CLK_MOUT_SCLK_MMC2_A		32
     39      1.1  jmcneill #define CLK_MOUT_SCLK_MMC1_B		33
     40      1.1  jmcneill #define CLK_MOUT_SCLK_MMC1_A		34
     41      1.1  jmcneill #define CLK_MOUT_SCLK_MMC0_D		35
     42      1.1  jmcneill #define CLK_MOUT_SCLK_MMC0_C		36
     43      1.1  jmcneill #define CLK_MOUT_SCLK_MMC0_B		37
     44      1.1  jmcneill #define CLK_MOUT_SCLK_MMC0_A		38
     45      1.1  jmcneill #define CLK_MOUT_SCLK_SPI4		39
     46      1.1  jmcneill #define CLK_MOUT_SCLK_SPI3		40
     47      1.1  jmcneill #define CLK_MOUT_SCLK_UART2		41
     48      1.1  jmcneill #define CLK_MOUT_SCLK_UART1		42
     49      1.1  jmcneill #define CLK_MOUT_SCLK_UART0		43
     50      1.1  jmcneill #define CLK_MOUT_SCLK_SPI2		44
     51      1.1  jmcneill #define CLK_MOUT_SCLK_SPI1		45
     52      1.1  jmcneill #define CLK_MOUT_SCLK_SPI0		46
     53      1.1  jmcneill #define CLK_MOUT_ACLK_MFC_400_C		47
     54      1.1  jmcneill #define CLK_MOUT_ACLK_MFC_400_B		48
     55      1.1  jmcneill #define CLK_MOUT_ACLK_MFC_400_A		49
     56      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_SENSOR2	50
     57      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_SENSOR1	51
     58      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_SENSOR0	52
     59      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_UART		53
     60      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_SPI1		54
     61      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_SPI0		55
     62      1.1  jmcneill #define CLK_MOUT_SCLK_PCIE_100		56
     63      1.1  jmcneill #define CLK_MOUT_SCLK_UFSUNIPRO		57
     64      1.1  jmcneill #define CLK_MOUT_SCLK_USBHOST30		58
     65      1.1  jmcneill #define CLK_MOUT_SCLK_USBDRD30		59
     66      1.1  jmcneill #define CLK_MOUT_SCLK_SLIMBUS		60
     67      1.1  jmcneill #define CLK_MOUT_SCLK_SPDIF		61
     68      1.1  jmcneill #define CLK_MOUT_SCLK_AUDIO1		62
     69      1.1  jmcneill #define CLK_MOUT_SCLK_AUDIO0		63
     70      1.1  jmcneill #define CLK_MOUT_SCLK_HDMI_SPDIF	64
     71      1.1  jmcneill 
     72      1.1  jmcneill #define CLK_DIV_ACLK_FSYS_200		100
     73      1.1  jmcneill #define CLK_DIV_ACLK_IMEM_SSSX_266	101
     74      1.1  jmcneill #define CLK_DIV_ACLK_IMEM_200		102
     75      1.1  jmcneill #define CLK_DIV_ACLK_IMEM_266		103
     76      1.1  jmcneill #define CLK_DIV_ACLK_PERIC_66_B		104
     77      1.1  jmcneill #define CLK_DIV_ACLK_PERIC_66_A		105
     78      1.1  jmcneill #define CLK_DIV_ACLK_PERIS_66_B		106
     79      1.1  jmcneill #define CLK_DIV_ACLK_PERIS_66_A		107
     80      1.1  jmcneill #define CLK_DIV_SCLK_MMC1_B		108
     81      1.1  jmcneill #define CLK_DIV_SCLK_MMC1_A		109
     82      1.1  jmcneill #define CLK_DIV_SCLK_MMC0_B		110
     83      1.1  jmcneill #define CLK_DIV_SCLK_MMC0_A		111
     84      1.1  jmcneill #define CLK_DIV_SCLK_MMC2_B		112
     85      1.1  jmcneill #define CLK_DIV_SCLK_MMC2_A		113
     86      1.1  jmcneill #define CLK_DIV_SCLK_SPI1_B		114
     87      1.1  jmcneill #define CLK_DIV_SCLK_SPI1_A		115
     88      1.1  jmcneill #define CLK_DIV_SCLK_SPI0_B		116
     89      1.1  jmcneill #define CLK_DIV_SCLK_SPI0_A		117
     90      1.1  jmcneill #define CLK_DIV_SCLK_SPI2_B		118
     91      1.1  jmcneill #define CLK_DIV_SCLK_SPI2_A		119
     92      1.1  jmcneill #define CLK_DIV_SCLK_UART2		120
     93      1.1  jmcneill #define CLK_DIV_SCLK_UART1		121
     94      1.1  jmcneill #define CLK_DIV_SCLK_UART0		122
     95      1.1  jmcneill #define CLK_DIV_SCLK_SPI4_B		123
     96      1.1  jmcneill #define CLK_DIV_SCLK_SPI4_A		124
     97      1.1  jmcneill #define CLK_DIV_SCLK_SPI3_B		125
     98      1.1  jmcneill #define CLK_DIV_SCLK_SPI3_A		126
     99      1.1  jmcneill #define CLK_DIV_SCLK_I2S1		127
    100      1.1  jmcneill #define CLK_DIV_SCLK_PCM1		128
    101      1.1  jmcneill #define CLK_DIV_SCLK_AUDIO1		129
    102      1.1  jmcneill #define CLK_DIV_SCLK_AUDIO0		130
    103      1.1  jmcneill #define CLK_DIV_ACLK_GSCL_111		131
    104      1.1  jmcneill #define CLK_DIV_ACLK_GSCL_333		132
    105      1.1  jmcneill #define CLK_DIV_ACLK_HEVC_400		133
    106      1.1  jmcneill #define CLK_DIV_ACLK_MFC_400		134
    107      1.1  jmcneill #define CLK_DIV_ACLK_G2D_266		135
    108      1.1  jmcneill #define CLK_DIV_ACLK_G2D_400		136
    109      1.1  jmcneill #define CLK_DIV_ACLK_G3D_400		137
    110      1.1  jmcneill #define CLK_DIV_ACLK_BUS0_400		138
    111      1.1  jmcneill #define CLK_DIV_ACLK_BUS1_400		139
    112      1.1  jmcneill #define CLK_DIV_SCLK_PCIE_100		140
    113      1.1  jmcneill #define CLK_DIV_SCLK_USBHOST30		141
    114      1.1  jmcneill #define CLK_DIV_SCLK_UFSUNIPRO		142
    115      1.1  jmcneill #define CLK_DIV_SCLK_USBDRD30		143
    116      1.1  jmcneill #define CLK_DIV_SCLK_JPEG		144
    117      1.1  jmcneill #define CLK_DIV_ACLK_MSCL_400		145
    118      1.1  jmcneill #define CLK_DIV_ACLK_ISP_DIS_400	146
    119      1.1  jmcneill #define CLK_DIV_ACLK_ISP_400		147
    120      1.1  jmcneill #define CLK_DIV_ACLK_CAM0_333		148
    121      1.1  jmcneill #define CLK_DIV_ACLK_CAM0_400		149
    122      1.1  jmcneill #define CLK_DIV_ACLK_CAM0_552		150
    123      1.1  jmcneill #define CLK_DIV_ACLK_CAM1_333		151
    124      1.1  jmcneill #define CLK_DIV_ACLK_CAM1_400		152
    125      1.1  jmcneill #define CLK_DIV_ACLK_CAM1_552		153
    126      1.1  jmcneill #define CLK_DIV_SCLK_ISP_UART		154
    127      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SPI1_B		155
    128      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SPI1_A		156
    129      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SPI0_B		157
    130      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SPI0_A		158
    131      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SENSOR2_B	159
    132      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SENSOR2_A	160
    133      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SENSOR1_B	161
    134      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SENSOR1_A	162
    135      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SENSOR0_B	163
    136      1.1  jmcneill #define CLK_DIV_SCLK_ISP_SENSOR0_A	164
    137      1.1  jmcneill 
    138      1.1  jmcneill #define CLK_ACLK_PERIC_66		200
    139      1.1  jmcneill #define CLK_ACLK_PERIS_66		201
    140      1.1  jmcneill #define CLK_ACLK_FSYS_200		202
    141      1.1  jmcneill #define CLK_SCLK_MMC2_FSYS		203
    142      1.1  jmcneill #define CLK_SCLK_MMC1_FSYS		204
    143      1.1  jmcneill #define CLK_SCLK_MMC0_FSYS		205
    144      1.1  jmcneill #define CLK_SCLK_SPI4_PERIC		206
    145      1.1  jmcneill #define CLK_SCLK_SPI3_PERIC		207
    146      1.1  jmcneill #define CLK_SCLK_UART2_PERIC		208
    147      1.1  jmcneill #define CLK_SCLK_UART1_PERIC		209
    148      1.1  jmcneill #define CLK_SCLK_UART0_PERIC		210
    149      1.1  jmcneill #define CLK_SCLK_SPI2_PERIC		211
    150      1.1  jmcneill #define CLK_SCLK_SPI1_PERIC		212
    151      1.1  jmcneill #define CLK_SCLK_SPI0_PERIC		213
    152      1.1  jmcneill #define CLK_SCLK_SPDIF_PERIC		214
    153      1.1  jmcneill #define CLK_SCLK_I2S1_PERIC		215
    154      1.1  jmcneill #define CLK_SCLK_PCM1_PERIC		216
    155      1.1  jmcneill #define CLK_SCLK_SLIMBUS		217
    156      1.1  jmcneill #define CLK_SCLK_AUDIO1			218
    157      1.1  jmcneill #define CLK_SCLK_AUDIO0			219
    158      1.1  jmcneill #define CLK_ACLK_G2D_266		220
    159      1.1  jmcneill #define CLK_ACLK_G2D_400		221
    160      1.1  jmcneill #define CLK_ACLK_G3D_400		222
    161  1.1.1.3  jmcneill #define CLK_ACLK_IMEM_SSSX_266		223
    162      1.1  jmcneill #define CLK_ACLK_BUS0_400		224
    163      1.1  jmcneill #define CLK_ACLK_BUS1_400		225
    164      1.1  jmcneill #define CLK_ACLK_IMEM_200		226
    165      1.1  jmcneill #define CLK_ACLK_IMEM_266		227
    166      1.1  jmcneill #define CLK_SCLK_PCIE_100_FSYS		228
    167      1.1  jmcneill #define CLK_SCLK_UFSUNIPRO_FSYS		229
    168      1.1  jmcneill #define CLK_SCLK_USBHOST30_FSYS		230
    169      1.1  jmcneill #define CLK_SCLK_USBDRD30_FSYS		231
    170      1.1  jmcneill #define CLK_ACLK_GSCL_111		232
    171      1.1  jmcneill #define CLK_ACLK_GSCL_333		233
    172      1.1  jmcneill #define CLK_SCLK_JPEG_MSCL		234
    173      1.1  jmcneill #define CLK_ACLK_MSCL_400		235
    174      1.1  jmcneill #define CLK_ACLK_MFC_400		236
    175      1.1  jmcneill #define CLK_ACLK_HEVC_400		237
    176      1.1  jmcneill #define CLK_ACLK_ISP_DIS_400		238
    177      1.1  jmcneill #define CLK_ACLK_ISP_400		239
    178      1.1  jmcneill #define CLK_ACLK_CAM0_333		240
    179      1.1  jmcneill #define CLK_ACLK_CAM0_400		241
    180      1.1  jmcneill #define CLK_ACLK_CAM0_552		242
    181      1.1  jmcneill #define CLK_ACLK_CAM1_333		243
    182      1.1  jmcneill #define CLK_ACLK_CAM1_400		244
    183      1.1  jmcneill #define CLK_ACLK_CAM1_552		245
    184      1.1  jmcneill #define CLK_SCLK_ISP_SENSOR2		246
    185      1.1  jmcneill #define CLK_SCLK_ISP_SENSOR1		247
    186      1.1  jmcneill #define CLK_SCLK_ISP_SENSOR0		248
    187      1.1  jmcneill #define CLK_SCLK_ISP_MCTADC_CAM1	249
    188      1.1  jmcneill #define CLK_SCLK_ISP_UART_CAM1		250
    189      1.1  jmcneill #define CLK_SCLK_ISP_SPI1_CAM1		251
    190      1.1  jmcneill #define CLK_SCLK_ISP_SPI0_CAM1		252
    191      1.1  jmcneill #define CLK_SCLK_HDMI_SPDIF_DISP	253
    192      1.1  jmcneill 
    193      1.1  jmcneill #define TOP_NR_CLK			254
    194      1.1  jmcneill 
    195      1.1  jmcneill /* CMU_CPIF */
    196      1.1  jmcneill #define CLK_FOUT_MPHY_PLL		1
    197      1.1  jmcneill 
    198      1.1  jmcneill #define CLK_MOUT_MPHY_PLL		2
    199      1.1  jmcneill 
    200      1.1  jmcneill #define CLK_DIV_SCLK_MPHY		10
    201      1.1  jmcneill 
    202      1.1  jmcneill #define CLK_SCLK_MPHY_PLL		11
    203      1.1  jmcneill #define CLK_SCLK_UFS_MPHY		11
    204      1.1  jmcneill 
    205      1.1  jmcneill #define CPIF_NR_CLK			12
    206      1.1  jmcneill 
    207      1.1  jmcneill /* CMU_MIF */
    208      1.1  jmcneill #define CLK_FOUT_MEM0_PLL		1
    209      1.1  jmcneill #define CLK_FOUT_MEM1_PLL		2
    210      1.1  jmcneill #define CLK_FOUT_BUS_PLL		3
    211      1.1  jmcneill #define CLK_FOUT_MFC_PLL		4
    212      1.1  jmcneill #define CLK_DOUT_MFC_PLL		5
    213      1.1  jmcneill #define CLK_DOUT_BUS_PLL		6
    214      1.1  jmcneill #define CLK_DOUT_MEM1_PLL		7
    215      1.1  jmcneill #define CLK_DOUT_MEM0_PLL		8
    216      1.1  jmcneill 
    217      1.1  jmcneill #define CLK_MOUT_MFC_PLL_DIV2		10
    218      1.1  jmcneill #define CLK_MOUT_BUS_PLL_DIV2		11
    219      1.1  jmcneill #define CLK_MOUT_MEM1_PLL_DIV2		12
    220      1.1  jmcneill #define CLK_MOUT_MEM0_PLL_DIV2		13
    221      1.1  jmcneill #define CLK_MOUT_MFC_PLL		14
    222      1.1  jmcneill #define CLK_MOUT_BUS_PLL		15
    223      1.1  jmcneill #define CLK_MOUT_MEM1_PLL		16
    224      1.1  jmcneill #define CLK_MOUT_MEM0_PLL		17
    225      1.1  jmcneill #define CLK_MOUT_CLK2X_PHY_C		18
    226      1.1  jmcneill #define CLK_MOUT_CLK2X_PHY_B		19
    227      1.1  jmcneill #define CLK_MOUT_CLK2X_PHY_A		20
    228      1.1  jmcneill #define CLK_MOUT_CLKM_PHY_C		21
    229      1.1  jmcneill #define CLK_MOUT_CLKM_PHY_B		22
    230      1.1  jmcneill #define CLK_MOUT_CLKM_PHY_A		23
    231      1.1  jmcneill #define CLK_MOUT_ACLK_MIFNM_200		24
    232      1.1  jmcneill #define CLK_MOUT_ACLK_MIFNM_400		25
    233      1.1  jmcneill #define CLK_MOUT_ACLK_DISP_333_B	26
    234      1.1  jmcneill #define CLK_MOUT_ACLK_DISP_333_A	27
    235      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_VCLK_C	28
    236      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_VCLK_B	29
    237      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_VCLK_A	30
    238      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_ECLK_C	31
    239      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_ECLK_B	32
    240      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_ECLK_A	33
    241      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_ECLK_C	34
    242      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_ECLK_B	35
    243      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_ECLK_A	36
    244      1.1  jmcneill #define CLK_MOUT_SCLK_DSD_C		37
    245      1.1  jmcneill #define CLK_MOUT_SCLK_DSD_B		38
    246      1.1  jmcneill #define CLK_MOUT_SCLK_DSD_A		39
    247      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM0_C		40
    248      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM0_B		41
    249      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM0_A		42
    250      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_VCLK_C	46
    251      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_VCLK_B	47
    252      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_VCLK_A	48
    253      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM1_C		49
    254      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM1_B		50
    255      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM1_A		51
    256      1.1  jmcneill 
    257      1.1  jmcneill #define CLK_DIV_SCLK_HPM_MIF		55
    258      1.1  jmcneill #define CLK_DIV_ACLK_DREX1		56
    259      1.1  jmcneill #define CLK_DIV_ACLK_DREX0		57
    260      1.1  jmcneill #define CLK_DIV_CLK2XPHY		58
    261      1.1  jmcneill #define CLK_DIV_ACLK_MIF_266		59
    262      1.1  jmcneill #define CLK_DIV_ACLK_MIFND_133		60
    263      1.1  jmcneill #define CLK_DIV_ACLK_MIF_133		61
    264      1.1  jmcneill #define CLK_DIV_ACLK_MIFNM_200		62
    265      1.1  jmcneill #define CLK_DIV_ACLK_MIF_200		63
    266      1.1  jmcneill #define CLK_DIV_ACLK_MIF_400		64
    267      1.1  jmcneill #define CLK_DIV_ACLK_BUS2_400		65
    268      1.1  jmcneill #define CLK_DIV_ACLK_DISP_333		66
    269      1.1  jmcneill #define CLK_DIV_ACLK_CPIF_200		67
    270      1.1  jmcneill #define CLK_DIV_SCLK_DSIM1		68
    271      1.1  jmcneill #define CLK_DIV_SCLK_DECON_TV_VCLK	69
    272      1.1  jmcneill #define CLK_DIV_SCLK_DSIM0		70
    273      1.1  jmcneill #define CLK_DIV_SCLK_DSD		71
    274      1.1  jmcneill #define CLK_DIV_SCLK_DECON_TV_ECLK	72
    275      1.1  jmcneill #define CLK_DIV_SCLK_DECON_VCLK		73
    276      1.1  jmcneill #define CLK_DIV_SCLK_DECON_ECLK		74
    277      1.1  jmcneill #define CLK_DIV_MIF_PRE			75
    278      1.1  jmcneill 
    279      1.1  jmcneill #define CLK_CLK2X_PHY1			80
    280      1.1  jmcneill #define CLK_CLK2X_PHY0			81
    281      1.1  jmcneill #define CLK_CLKM_PHY1			82
    282      1.1  jmcneill #define CLK_CLKM_PHY0			83
    283      1.1  jmcneill #define CLK_RCLK_DREX1			84
    284      1.1  jmcneill #define CLK_RCLK_DREX0			85
    285      1.1  jmcneill #define CLK_ACLK_DREX1_TZ		86
    286      1.1  jmcneill #define CLK_ACLK_DREX0_TZ		87
    287      1.1  jmcneill #define CLK_ACLK_DREX1_PEREV		88
    288      1.1  jmcneill #define CLK_ACLK_DREX0_PEREV		89
    289      1.1  jmcneill #define CLK_ACLK_DREX1_MEMIF		90
    290      1.1  jmcneill #define CLK_ACLK_DREX0_MEMIF		91
    291      1.1  jmcneill #define CLK_ACLK_DREX1_SCH		92
    292      1.1  jmcneill #define CLK_ACLK_DREX0_SCH		93
    293      1.1  jmcneill #define CLK_ACLK_DREX1_BUSIF		94
    294      1.1  jmcneill #define CLK_ACLK_DREX0_BUSIF		95
    295      1.1  jmcneill #define CLK_ACLK_DREX1_BUSIF_RD		96
    296      1.1  jmcneill #define CLK_ACLK_DREX0_BUSIF_RD		97
    297      1.1  jmcneill #define CLK_ACLK_DREX1			98
    298      1.1  jmcneill #define CLK_ACLK_DREX0			99
    299      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX	100
    300      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF	101
    301      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF	102
    302      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_MIF_IMEM	103
    303      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI	104
    304      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI	105
    305      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_CP1		106
    306      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_CP1		107
    307      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_CP0		108
    308      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_CP0		109
    309      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DREX1_3	110
    310      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DREX1_3	111
    311      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DREX1_1	112
    312      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DREX1_1	113
    313      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DREX1_0	114
    314      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DREX1_0	115
    315      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DREX0_3	116
    316      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DREX0_3	117
    317      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DREX0_1	118
    318      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DREX0_1	119
    319      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DREX0_0	120
    320      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DREX0_0	121
    321      1.1  jmcneill #define CLK_ACLK_AHB2APB_MIF2P		122
    322      1.1  jmcneill #define CLK_ACLK_AHB2APB_MIF1P		123
    323      1.1  jmcneill #define CLK_ACLK_AHB2APB_MIF0P		124
    324      1.1  jmcneill #define CLK_ACLK_IXIU_CCI		125
    325      1.1  jmcneill #define CLK_ACLK_XIU_MIFSFRX		126
    326      1.1  jmcneill #define CLK_ACLK_MIFNP_133		127
    327      1.1  jmcneill #define CLK_ACLK_MIFNM_200		128
    328      1.1  jmcneill #define CLK_ACLK_MIFND_133		129
    329      1.1  jmcneill #define CLK_ACLK_MIFND_400		130
    330      1.1  jmcneill #define CLK_ACLK_CCI			131
    331      1.1  jmcneill #define CLK_ACLK_MIFND_266		132
    332      1.1  jmcneill #define CLK_ACLK_PPMU_DREX1S3		133
    333      1.1  jmcneill #define CLK_ACLK_PPMU_DREX1S1		134
    334      1.1  jmcneill #define CLK_ACLK_PPMU_DREX1S0		135
    335      1.1  jmcneill #define CLK_ACLK_PPMU_DREX0S3		136
    336      1.1  jmcneill #define CLK_ACLK_PPMU_DREX0S1		137
    337      1.1  jmcneill #define CLK_ACLK_PPMU_DREX0S0		138
    338      1.1  jmcneill #define CLK_ACLK_BTS_APOLLO		139
    339      1.1  jmcneill #define CLK_ACLK_BTS_ATLAS		140
    340      1.1  jmcneill #define CLK_ACLK_ACE_SEL_APOLL		141
    341      1.1  jmcneill #define CLK_ACLK_ACE_SEL_ATLAS		142
    342      1.1  jmcneill #define CLK_ACLK_AXIDS_CCI_MIFSFRX	143
    343      1.1  jmcneill #define CLK_ACLK_AXIUS_ATLAS_CCI	144
    344      1.1  jmcneill #define CLK_ACLK_AXISYNCDNS_CCI		145
    345      1.1  jmcneill #define CLK_ACLK_AXISYNCDN_CCI		146
    346      1.1  jmcneill #define CLK_ACLK_AXISYNCDN_NOC_D	147
    347      1.1  jmcneill #define CLK_ACLK_ASYNCACEM_APOLLO_CCI	148
    348      1.1  jmcneill #define CLK_ACLK_ASYNCACEM_ATLAS_CCI	149
    349      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS	150
    350      1.1  jmcneill #define CLK_ACLK_BUS2_400		151
    351      1.1  jmcneill #define CLK_ACLK_DISP_333		152
    352      1.1  jmcneill #define CLK_ACLK_CPIF_200		153
    353      1.1  jmcneill #define CLK_PCLK_PPMU_DREX1S3		154
    354      1.1  jmcneill #define CLK_PCLK_PPMU_DREX1S1		155
    355      1.1  jmcneill #define CLK_PCLK_PPMU_DREX1S0		156
    356      1.1  jmcneill #define CLK_PCLK_PPMU_DREX0S3		157
    357      1.1  jmcneill #define CLK_PCLK_PPMU_DREX0S1		158
    358      1.1  jmcneill #define CLK_PCLK_PPMU_DREX0S0		159
    359      1.1  jmcneill #define CLK_PCLK_BTS_APOLLO		160
    360      1.1  jmcneill #define CLK_PCLK_BTS_ATLAS		161
    361      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_NOC_P_CCI	162
    362      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_CP1		163
    363      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_CP0		164
    364      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DREX1_3	165
    365      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DREX1_1	166
    366      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DREX1_0	167
    367      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DREX0_3	168
    368      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DREX0_1	169
    369      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DREX0_0	170
    370      1.1  jmcneill #define CLK_PCLK_MIFSRVND_133		171
    371      1.1  jmcneill #define CLK_PCLK_PMU_MIF		172
    372      1.1  jmcneill #define CLK_PCLK_SYSREG_MIF		173
    373      1.1  jmcneill #define CLK_PCLK_GPIO_ALIVE		174
    374      1.1  jmcneill #define CLK_PCLK_ABB			175
    375      1.1  jmcneill #define CLK_PCLK_PMU_APBIF		176
    376      1.1  jmcneill #define CLK_PCLK_DDR_PHY1		177
    377      1.1  jmcneill #define CLK_PCLK_DREX1			178
    378      1.1  jmcneill #define CLK_PCLK_DDR_PHY0		179
    379      1.1  jmcneill #define CLK_PCLK_DREX0			180
    380      1.1  jmcneill #define CLK_PCLK_DREX0_TZ		181
    381      1.1  jmcneill #define CLK_PCLK_DREX1_TZ		182
    382      1.1  jmcneill #define CLK_PCLK_MONOTONIC_CNT		183
    383      1.1  jmcneill #define CLK_PCLK_RTC			184
    384      1.1  jmcneill #define CLK_SCLK_DSIM1_DISP		185
    385      1.1  jmcneill #define CLK_SCLK_DECON_TV_VCLK_DISP	186
    386      1.1  jmcneill #define CLK_SCLK_FREQ_DET_BUS_PLL	187
    387      1.1  jmcneill #define CLK_SCLK_FREQ_DET_MFC_PLL	188
    388      1.1  jmcneill #define CLK_SCLK_FREQ_DET_MEM0_PLL	189
    389      1.1  jmcneill #define CLK_SCLK_FREQ_DET_MEM1_PLL	190
    390      1.1  jmcneill #define CLK_SCLK_DSIM0_DISP		191
    391      1.1  jmcneill #define CLK_SCLK_DSD_DISP		192
    392      1.1  jmcneill #define CLK_SCLK_DECON_TV_ECLK_DISP	193
    393      1.1  jmcneill #define CLK_SCLK_DECON_VCLK_DISP	194
    394      1.1  jmcneill #define CLK_SCLK_DECON_ECLK_DISP	195
    395      1.1  jmcneill #define CLK_SCLK_HPM_MIF		196
    396      1.1  jmcneill #define CLK_SCLK_MFC_PLL		197
    397      1.1  jmcneill #define CLK_SCLK_BUS_PLL		198
    398      1.1  jmcneill #define CLK_SCLK_BUS_PLL_APOLLO		199
    399      1.1  jmcneill #define CLK_SCLK_BUS_PLL_ATLAS		200
    400      1.1  jmcneill 
    401      1.1  jmcneill #define MIF_NR_CLK			201
    402      1.1  jmcneill 
    403      1.1  jmcneill /* CMU_PERIC */
    404      1.1  jmcneill #define CLK_PCLK_SPI2			1
    405      1.1  jmcneill #define CLK_PCLK_SPI1			2
    406      1.1  jmcneill #define CLK_PCLK_SPI0			3
    407      1.1  jmcneill #define CLK_PCLK_UART2			4
    408      1.1  jmcneill #define CLK_PCLK_UART1			5
    409      1.1  jmcneill #define CLK_PCLK_UART0			6
    410      1.1  jmcneill #define CLK_PCLK_HSI2C3			7
    411      1.1  jmcneill #define CLK_PCLK_HSI2C2			8
    412      1.1  jmcneill #define CLK_PCLK_HSI2C1			9
    413      1.1  jmcneill #define CLK_PCLK_HSI2C0			10
    414      1.1  jmcneill #define CLK_PCLK_I2C7			11
    415      1.1  jmcneill #define CLK_PCLK_I2C6			12
    416      1.1  jmcneill #define CLK_PCLK_I2C5			13
    417      1.1  jmcneill #define CLK_PCLK_I2C4			14
    418      1.1  jmcneill #define CLK_PCLK_I2C3			15
    419      1.1  jmcneill #define CLK_PCLK_I2C2			16
    420      1.1  jmcneill #define CLK_PCLK_I2C1			17
    421      1.1  jmcneill #define CLK_PCLK_I2C0			18
    422      1.1  jmcneill #define CLK_PCLK_SPI4			19
    423      1.1  jmcneill #define CLK_PCLK_SPI3			20
    424      1.1  jmcneill #define CLK_PCLK_HSI2C11		21
    425      1.1  jmcneill #define CLK_PCLK_HSI2C10		22
    426      1.1  jmcneill #define CLK_PCLK_HSI2C9			23
    427      1.1  jmcneill #define CLK_PCLK_HSI2C8			24
    428      1.1  jmcneill #define CLK_PCLK_HSI2C7			25
    429      1.1  jmcneill #define CLK_PCLK_HSI2C6			26
    430      1.1  jmcneill #define CLK_PCLK_HSI2C5			27
    431      1.1  jmcneill #define CLK_PCLK_HSI2C4			28
    432      1.1  jmcneill #define CLK_SCLK_SPI4			29
    433      1.1  jmcneill #define CLK_SCLK_SPI3			30
    434      1.1  jmcneill #define CLK_SCLK_SPI2			31
    435      1.1  jmcneill #define CLK_SCLK_SPI1			32
    436      1.1  jmcneill #define CLK_SCLK_SPI0			33
    437      1.1  jmcneill #define CLK_SCLK_UART2			34
    438      1.1  jmcneill #define CLK_SCLK_UART1			35
    439      1.1  jmcneill #define CLK_SCLK_UART0			36
    440      1.1  jmcneill #define CLK_ACLK_AHB2APB_PERIC2P	37
    441      1.1  jmcneill #define CLK_ACLK_AHB2APB_PERIC1P	38
    442      1.1  jmcneill #define CLK_ACLK_AHB2APB_PERIC0P	39
    443      1.1  jmcneill #define CLK_ACLK_PERICNP_66		40
    444      1.1  jmcneill #define CLK_PCLK_SCI			41
    445      1.1  jmcneill #define CLK_PCLK_GPIO_FINGER		42
    446      1.1  jmcneill #define CLK_PCLK_GPIO_ESE		43
    447      1.1  jmcneill #define CLK_PCLK_PWM			44
    448      1.1  jmcneill #define CLK_PCLK_SPDIF			45
    449      1.1  jmcneill #define CLK_PCLK_PCM1			46
    450      1.1  jmcneill #define CLK_PCLK_I2S1			47
    451      1.1  jmcneill #define CLK_PCLK_ADCIF			48
    452      1.1  jmcneill #define CLK_PCLK_GPIO_TOUCH		49
    453      1.1  jmcneill #define CLK_PCLK_GPIO_NFC		50
    454      1.1  jmcneill #define CLK_PCLK_GPIO_PERIC		51
    455      1.1  jmcneill #define CLK_PCLK_PMU_PERIC		52
    456      1.1  jmcneill #define CLK_PCLK_SYSREG_PERIC		53
    457      1.1  jmcneill #define CLK_SCLK_IOCLK_SPI4		54
    458      1.1  jmcneill #define CLK_SCLK_IOCLK_SPI3		55
    459      1.1  jmcneill #define CLK_SCLK_SCI			56
    460      1.1  jmcneill #define CLK_SCLK_SC_IN			57
    461      1.1  jmcneill #define CLK_SCLK_PWM			58
    462      1.1  jmcneill #define CLK_SCLK_IOCLK_SPI2		59
    463      1.1  jmcneill #define CLK_SCLK_IOCLK_SPI1		60
    464      1.1  jmcneill #define CLK_SCLK_IOCLK_SPI0		61
    465      1.1  jmcneill #define CLK_SCLK_IOCLK_I2S1_BCLK	62
    466      1.1  jmcneill #define CLK_SCLK_SPDIF			63
    467      1.1  jmcneill #define CLK_SCLK_PCM1			64
    468      1.1  jmcneill #define CLK_SCLK_I2S1			65
    469      1.1  jmcneill 
    470      1.1  jmcneill #define CLK_DIV_SCLK_SCI		70
    471      1.1  jmcneill #define CLK_DIV_SCLK_SC_IN		71
    472      1.1  jmcneill 
    473      1.1  jmcneill #define PERIC_NR_CLK			72
    474      1.1  jmcneill 
    475      1.1  jmcneill /* CMU_PERIS */
    476      1.1  jmcneill #define CLK_PCLK_HPM_APBIF		1
    477      1.1  jmcneill #define CLK_PCLK_TMU1_APBIF		2
    478      1.1  jmcneill #define CLK_PCLK_TMU0_APBIF		3
    479      1.1  jmcneill #define CLK_PCLK_PMU_PERIS		4
    480      1.1  jmcneill #define CLK_PCLK_SYSREG_PERIS		5
    481      1.1  jmcneill #define CLK_PCLK_CMU_TOP_APBIF		6
    482      1.1  jmcneill #define CLK_PCLK_WDT_APOLLO		7
    483      1.1  jmcneill #define CLK_PCLK_WDT_ATLAS		8
    484      1.1  jmcneill #define CLK_PCLK_MCT			9
    485      1.1  jmcneill #define CLK_PCLK_HDMI_CEC		10
    486      1.1  jmcneill #define CLK_ACLK_AHB2APB_PERIS1P	11
    487      1.1  jmcneill #define CLK_ACLK_AHB2APB_PERIS0P	12
    488      1.1  jmcneill #define CLK_ACLK_PERISNP_66		13
    489      1.1  jmcneill #define CLK_PCLK_TZPC12			14
    490      1.1  jmcneill #define CLK_PCLK_TZPC11			15
    491      1.1  jmcneill #define CLK_PCLK_TZPC10			16
    492      1.1  jmcneill #define CLK_PCLK_TZPC9			17
    493      1.1  jmcneill #define CLK_PCLK_TZPC8			18
    494      1.1  jmcneill #define CLK_PCLK_TZPC7			19
    495      1.1  jmcneill #define CLK_PCLK_TZPC6			20
    496      1.1  jmcneill #define CLK_PCLK_TZPC5			21
    497      1.1  jmcneill #define CLK_PCLK_TZPC4			22
    498      1.1  jmcneill #define CLK_PCLK_TZPC3			23
    499      1.1  jmcneill #define CLK_PCLK_TZPC2			24
    500      1.1  jmcneill #define CLK_PCLK_TZPC1			25
    501      1.1  jmcneill #define CLK_PCLK_TZPC0			26
    502      1.1  jmcneill #define CLK_PCLK_SECKEY_APBIF		27
    503      1.1  jmcneill #define CLK_PCLK_CHIPID_APBIF		28
    504      1.1  jmcneill #define CLK_PCLK_TOPRTC			29
    505      1.1  jmcneill #define CLK_PCLK_CUSTOM_EFUSE_APBIF	30
    506      1.1  jmcneill #define CLK_PCLK_ANTIRBK_CNT_APBIF	31
    507      1.1  jmcneill #define CLK_PCLK_OTP_CON_APBIF		32
    508      1.1  jmcneill #define CLK_SCLK_ASV_TB			33
    509      1.1  jmcneill #define CLK_SCLK_TMU1			34
    510      1.1  jmcneill #define CLK_SCLK_TMU0			35
    511      1.1  jmcneill #define CLK_SCLK_SECKEY			36
    512      1.1  jmcneill #define CLK_SCLK_CHIPID			37
    513      1.1  jmcneill #define CLK_SCLK_TOPRTC			38
    514      1.1  jmcneill #define CLK_SCLK_CUSTOM_EFUSE		39
    515      1.1  jmcneill #define CLK_SCLK_ANTIRBK_CNT		40
    516      1.1  jmcneill #define CLK_SCLK_OTP_CON		41
    517      1.1  jmcneill 
    518      1.1  jmcneill #define PERIS_NR_CLK			42
    519      1.1  jmcneill 
    520      1.1  jmcneill /* CMU_FSYS */
    521      1.1  jmcneill #define CLK_MOUT_ACLK_FSYS_200_USER	1
    522      1.1  jmcneill #define CLK_MOUT_SCLK_MMC2_USER		2
    523      1.1  jmcneill #define CLK_MOUT_SCLK_MMC1_USER		3
    524      1.1  jmcneill #define CLK_MOUT_SCLK_MMC0_USER		4
    525      1.1  jmcneill #define CLK_MOUT_SCLK_UFS_MPHY_USER	5
    526      1.1  jmcneill #define CLK_MOUT_SCLK_PCIE_100_USER	6
    527      1.1  jmcneill #define CLK_MOUT_SCLK_UFSUNIPRO_USER	7
    528      1.1  jmcneill #define CLK_MOUT_SCLK_USBHOST30_USER	8
    529      1.1  jmcneill #define CLK_MOUT_SCLK_USBDRD30_USER	9
    530      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER	10
    531      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER		11
    532      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER		12
    533      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER		13
    534      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER		14
    535      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER		15
    536      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER		16
    537      1.1  jmcneill #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER		17
    538      1.1  jmcneill #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER			18
    539      1.1  jmcneill #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER			19
    540      1.1  jmcneill #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER			20
    541      1.1  jmcneill #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER			21
    542      1.1  jmcneill #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER			22
    543      1.1  jmcneill #define CLK_MOUT_SCLK_MPHY					23
    544      1.1  jmcneill 
    545      1.1  jmcneill #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY			25
    546      1.1  jmcneill #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY		26
    547      1.1  jmcneill #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY		27
    548      1.1  jmcneill #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY		28
    549      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY			29
    550      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY			30
    551      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY			31
    552      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY			32
    553      1.1  jmcneill #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY				33
    554      1.1  jmcneill #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY				34
    555      1.1  jmcneill #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY				35
    556      1.1  jmcneill #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY				36
    557      1.1  jmcneill #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY				37
    558      1.1  jmcneill 
    559      1.1  jmcneill #define CLK_ACLK_PCIE			50
    560      1.1  jmcneill #define CLK_ACLK_PDMA1			51
    561      1.1  jmcneill #define CLK_ACLK_TSI			52
    562      1.1  jmcneill #define CLK_ACLK_MMC2			53
    563      1.1  jmcneill #define CLK_ACLK_MMC1			54
    564      1.1  jmcneill #define CLK_ACLK_MMC0			55
    565      1.1  jmcneill #define CLK_ACLK_UFS			56
    566      1.1  jmcneill #define CLK_ACLK_USBHOST20		57
    567      1.1  jmcneill #define CLK_ACLK_USBHOST30		58
    568      1.1  jmcneill #define CLK_ACLK_USBDRD30		59
    569      1.1  jmcneill #define CLK_ACLK_PDMA0			60
    570      1.1  jmcneill #define CLK_SCLK_MMC2			61
    571      1.1  jmcneill #define CLK_SCLK_MMC1			62
    572      1.1  jmcneill #define CLK_SCLK_MMC0			63
    573      1.1  jmcneill #define CLK_PDMA1			64
    574      1.1  jmcneill #define CLK_PDMA0			65
    575      1.1  jmcneill #define CLK_ACLK_XIU_FSYSPX		66
    576      1.1  jmcneill #define CLK_ACLK_AHB_USBLINKH1		67
    577      1.1  jmcneill #define CLK_ACLK_SMMU_PDMA1		68
    578      1.1  jmcneill #define CLK_ACLK_BTS_PCIE		69
    579      1.1  jmcneill #define CLK_ACLK_AXIUS_PDMA1		70
    580      1.1  jmcneill #define CLK_ACLK_SMMU_PDMA0		71
    581      1.1  jmcneill #define CLK_ACLK_BTS_UFS		72
    582      1.1  jmcneill #define CLK_ACLK_BTS_USBHOST30		73
    583      1.1  jmcneill #define CLK_ACLK_BTS_USBDRD30		74
    584      1.1  jmcneill #define CLK_ACLK_AXIUS_PDMA0		75
    585      1.1  jmcneill #define CLK_ACLK_AXIUS_USBHS		76
    586      1.1  jmcneill #define CLK_ACLK_AXIUS_FSYSSX		77
    587      1.1  jmcneill #define CLK_ACLK_AHB2APB_FSYSP		78
    588      1.1  jmcneill #define CLK_ACLK_AHB2AXI_USBHS		79
    589      1.1  jmcneill #define CLK_ACLK_AHB_USBLINKH0		80
    590      1.1  jmcneill #define CLK_ACLK_AHB_USBHS		81
    591      1.1  jmcneill #define CLK_ACLK_AHB_FSYSH		82
    592      1.1  jmcneill #define CLK_ACLK_XIU_FSYSX		83
    593      1.1  jmcneill #define CLK_ACLK_XIU_FSYSSX		84
    594      1.1  jmcneill #define CLK_ACLK_FSYSNP_200		85
    595      1.1  jmcneill #define CLK_ACLK_FSYSND_200		86
    596      1.1  jmcneill #define CLK_PCLK_PCIE_CTRL		87
    597      1.1  jmcneill #define CLK_PCLK_SMMU_PDMA1		88
    598      1.1  jmcneill #define CLK_PCLK_PCIE_PHY		89
    599      1.1  jmcneill #define CLK_PCLK_BTS_PCIE		90
    600      1.1  jmcneill #define CLK_PCLK_SMMU_PDMA0		91
    601      1.1  jmcneill #define CLK_PCLK_BTS_UFS		92
    602      1.1  jmcneill #define CLK_PCLK_BTS_USBHOST30		93
    603      1.1  jmcneill #define CLK_PCLK_BTS_USBDRD30		94
    604      1.1  jmcneill #define CLK_PCLK_GPIO_FSYS		95
    605      1.1  jmcneill #define CLK_PCLK_PMU_FSYS		96
    606      1.1  jmcneill #define CLK_PCLK_SYSREG_FSYS		97
    607      1.1  jmcneill #define CLK_SCLK_PCIE_100		98
    608      1.1  jmcneill #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK	99
    609      1.1  jmcneill #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK	100
    610      1.1  jmcneill #define CLK_PHYCLK_UFS_RX1_SYMBOL		101
    611      1.1  jmcneill #define CLK_PHYCLK_UFS_RX0_SYMBOL		102
    612      1.1  jmcneill #define CLK_PHYCLK_UFS_TX1_SYMBOL		103
    613      1.1  jmcneill #define CLK_PHYCLK_UFS_TX0_SYMBOL		104
    614      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_HSIC1		105
    615      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI	106
    616      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK	107
    617      1.1  jmcneill #define CLK_PHYCLK_USBHOST20_PHY_FREECLK	108
    618      1.1  jmcneill #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK	109
    619      1.1  jmcneill #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK	110
    620      1.1  jmcneill #define CLK_SCLK_MPHY			111
    621      1.1  jmcneill #define CLK_SCLK_UFSUNIPRO		112
    622      1.1  jmcneill #define CLK_SCLK_USBHOST30		113
    623      1.1  jmcneill #define CLK_SCLK_USBDRD30		114
    624      1.1  jmcneill #define CLK_PCIE			115
    625      1.1  jmcneill 
    626      1.1  jmcneill #define FSYS_NR_CLK			116
    627      1.1  jmcneill 
    628      1.1  jmcneill /* CMU_G2D */
    629      1.1  jmcneill #define CLK_MUX_ACLK_G2D_266_USER	1
    630      1.1  jmcneill #define CLK_MUX_ACLK_G2D_400_USER	2
    631      1.1  jmcneill 
    632      1.1  jmcneill #define CLK_DIV_PCLK_G2D		3
    633      1.1  jmcneill 
    634      1.1  jmcneill #define CLK_ACLK_SMMU_MDMA1		4
    635      1.1  jmcneill #define CLK_ACLK_BTS_MDMA1		5
    636      1.1  jmcneill #define CLK_ACLK_BTS_G2D		6
    637      1.1  jmcneill #define CLK_ACLK_ALB_G2D		7
    638      1.1  jmcneill #define CLK_ACLK_AXIUS_G2DX		8
    639      1.1  jmcneill #define CLK_ACLK_ASYNCAXI_SYSX		9
    640      1.1  jmcneill #define CLK_ACLK_AHB2APB_G2D1P		10
    641      1.1  jmcneill #define CLK_ACLK_AHB2APB_G2D0P		11
    642      1.1  jmcneill #define CLK_ACLK_XIU_G2DX		12
    643      1.1  jmcneill #define CLK_ACLK_G2DNP_133		13
    644      1.1  jmcneill #define CLK_ACLK_G2DND_400		14
    645      1.1  jmcneill #define CLK_ACLK_MDMA1			15
    646      1.1  jmcneill #define CLK_ACLK_G2D			16
    647      1.1  jmcneill #define CLK_ACLK_SMMU_G2D		17
    648      1.1  jmcneill #define CLK_PCLK_SMMU_MDMA1		18
    649      1.1  jmcneill #define CLK_PCLK_BTS_MDMA1		19
    650      1.1  jmcneill #define CLK_PCLK_BTS_G2D		20
    651      1.1  jmcneill #define CLK_PCLK_ALB_G2D		21
    652      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_SYSX		22
    653      1.1  jmcneill #define CLK_PCLK_PMU_G2D		23
    654      1.1  jmcneill #define CLK_PCLK_SYSREG_G2D		24
    655      1.1  jmcneill #define CLK_PCLK_G2D			25
    656      1.1  jmcneill #define CLK_PCLK_SMMU_G2D		26
    657      1.1  jmcneill 
    658      1.1  jmcneill #define G2D_NR_CLK			27
    659      1.1  jmcneill 
    660      1.1  jmcneill /* CMU_DISP */
    661      1.1  jmcneill #define CLK_FOUT_DISP_PLL				1
    662      1.1  jmcneill 
    663      1.1  jmcneill #define CLK_MOUT_DISP_PLL				2
    664      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM1_USER			3
    665      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM0_USER			4
    666      1.1  jmcneill #define CLK_MOUT_SCLK_DSD_USER				5
    667      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER		6
    668      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_VCLK_USER			7
    669      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_ECLK_USER			8
    670      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER		9
    671      1.1  jmcneill #define CLK_MOUT_ACLK_DISP_333_USER			10
    672      1.1  jmcneill #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER	11
    673      1.1  jmcneill #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER	12
    674      1.1  jmcneill #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER	13
    675      1.1  jmcneill #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER	14
    676      1.1  jmcneill #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER		15
    677      1.1  jmcneill #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER		16
    678      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM0				17
    679      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_ECLK			18
    680      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_VCLK			19
    681      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_ECLK			20
    682      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM1_B_DISP			21
    683      1.1  jmcneill #define CLK_MOUT_SCLK_DSIM1_A_DISP			22
    684      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP		23
    685      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP		24
    686      1.1  jmcneill #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP		25
    687      1.1  jmcneill 
    688      1.1  jmcneill #define CLK_DIV_SCLK_DSIM1_DISP				30
    689      1.1  jmcneill #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP			31
    690      1.1  jmcneill #define CLK_DIV_SCLK_DSIM0_DISP				32
    691      1.1  jmcneill #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP			33
    692      1.1  jmcneill #define CLK_DIV_SCLK_DECON_VCLK_DISP			34
    693      1.1  jmcneill #define CLK_DIV_SCLK_DECON_ECLK_DISP			35
    694      1.1  jmcneill #define CLK_DIV_PCLK_DISP				36
    695      1.1  jmcneill 
    696      1.1  jmcneill #define CLK_ACLK_DECON_TV				40
    697      1.1  jmcneill #define CLK_ACLK_DECON					41
    698      1.1  jmcneill #define CLK_ACLK_SMMU_TV1X				42
    699      1.1  jmcneill #define CLK_ACLK_SMMU_TV0X				43
    700      1.1  jmcneill #define CLK_ACLK_SMMU_DECON1X				44
    701      1.1  jmcneill #define CLK_ACLK_SMMU_DECON0X				45
    702      1.1  jmcneill #define CLK_ACLK_BTS_DECON_TV_M3			46
    703      1.1  jmcneill #define CLK_ACLK_BTS_DECON_TV_M2			47
    704      1.1  jmcneill #define CLK_ACLK_BTS_DECON_TV_M1			48
    705      1.1  jmcneill #define CLK_ACLK_BTS_DECON_TV_M0			49
    706      1.1  jmcneill #define CLK_ACLK_BTS_DECON_NM4				50
    707      1.1  jmcneill #define CLK_ACLK_BTS_DECON_NM3				51
    708      1.1  jmcneill #define CLK_ACLK_BTS_DECON_NM2				52
    709      1.1  jmcneill #define CLK_ACLK_BTS_DECON_NM1				53
    710      1.1  jmcneill #define CLK_ACLK_BTS_DECON_NM0				54
    711      1.1  jmcneill #define CLK_ACLK_AHB2APB_DISPSFR2P			55
    712      1.1  jmcneill #define CLK_ACLK_AHB2APB_DISPSFR1P			56
    713      1.1  jmcneill #define CLK_ACLK_AHB2APB_DISPSFR0P			57
    714      1.1  jmcneill #define CLK_ACLK_AHB_DISPH				58
    715      1.1  jmcneill #define CLK_ACLK_XIU_TV1X				59
    716      1.1  jmcneill #define CLK_ACLK_XIU_TV0X				60
    717      1.1  jmcneill #define CLK_ACLK_XIU_DECON1X				61
    718      1.1  jmcneill #define CLK_ACLK_XIU_DECON0X				62
    719      1.1  jmcneill #define CLK_ACLK_XIU_DISP1X				63
    720      1.1  jmcneill #define CLK_ACLK_XIU_DISPNP_100				64
    721      1.1  jmcneill #define CLK_ACLK_DISP1ND_333				65
    722      1.1  jmcneill #define CLK_ACLK_DISP0ND_333				66
    723      1.1  jmcneill #define CLK_PCLK_SMMU_TV1X				67
    724      1.1  jmcneill #define CLK_PCLK_SMMU_TV0X				68
    725      1.1  jmcneill #define CLK_PCLK_SMMU_DECON1X				69
    726      1.1  jmcneill #define CLK_PCLK_SMMU_DECON0X				70
    727      1.1  jmcneill #define CLK_PCLK_BTS_DECON_TV_M3			71
    728      1.1  jmcneill #define CLK_PCLK_BTS_DECON_TV_M2			72
    729      1.1  jmcneill #define CLK_PCLK_BTS_DECON_TV_M1			73
    730      1.1  jmcneill #define CLK_PCLK_BTS_DECON_TV_M0			74
    731      1.1  jmcneill #define CLK_PCLK_BTS_DECONM4				75
    732      1.1  jmcneill #define CLK_PCLK_BTS_DECONM3				76
    733      1.1  jmcneill #define CLK_PCLK_BTS_DECONM2				77
    734      1.1  jmcneill #define CLK_PCLK_BTS_DECONM1				78
    735      1.1  jmcneill #define CLK_PCLK_BTS_DECONM0				79
    736      1.1  jmcneill #define CLK_PCLK_MIC1					80
    737      1.1  jmcneill #define CLK_PCLK_PMU_DISP				81
    738      1.1  jmcneill #define CLK_PCLK_SYSREG_DISP				82
    739      1.1  jmcneill #define CLK_PCLK_HDMIPHY				83
    740      1.1  jmcneill #define CLK_PCLK_HDMI					84
    741      1.1  jmcneill #define CLK_PCLK_MIC0					85
    742      1.1  jmcneill #define CLK_PCLK_DSIM1					86
    743      1.1  jmcneill #define CLK_PCLK_DSIM0					87
    744      1.1  jmcneill #define CLK_PCLK_DECON_TV				88
    745      1.1  jmcneill #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8			89
    746      1.1  jmcneill #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0			90
    747      1.1  jmcneill #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1			91
    748      1.1  jmcneill #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1			92
    749      1.1  jmcneill #define CLK_SCLK_DSIM1					93
    750      1.1  jmcneill #define CLK_SCLK_DECON_TV_VCLK				94
    751      1.1  jmcneill #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8			95
    752      1.1  jmcneill #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0			96
    753      1.1  jmcneill #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO			97
    754      1.1  jmcneill #define CLK_PHYCLK_HDMI_PIXEL				98
    755      1.1  jmcneill #define CLK_SCLK_RGB_VCLK_TO_SMIES			99
    756      1.1  jmcneill #define CLK_SCLK_FREQ_DET_DISP_PLL			100
    757      1.1  jmcneill #define CLK_SCLK_RGB_VCLK_TO_DSIM0			101
    758      1.1  jmcneill #define CLK_SCLK_RGB_VCLK_TO_MIC0			102
    759      1.1  jmcneill #define CLK_SCLK_DSD					103
    760      1.1  jmcneill #define CLK_SCLK_HDMI_SPDIF				104
    761      1.1  jmcneill #define CLK_SCLK_DSIM0					105
    762      1.1  jmcneill #define CLK_SCLK_DECON_TV_ECLK				106
    763      1.1  jmcneill #define CLK_SCLK_DECON_VCLK				107
    764      1.1  jmcneill #define CLK_SCLK_DECON_ECLK				108
    765      1.1  jmcneill #define CLK_SCLK_RGB_VCLK				109
    766      1.1  jmcneill #define CLK_SCLK_RGB_TV_VCLK				110
    767      1.1  jmcneill 
    768      1.1  jmcneill #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY		111
    769      1.1  jmcneill #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY		112
    770      1.1  jmcneill 
    771      1.1  jmcneill #define CLK_PCLK_DECON					113
    772      1.1  jmcneill 
    773      1.1  jmcneill #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY		114
    774      1.1  jmcneill #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY		115
    775      1.1  jmcneill 
    776      1.1  jmcneill #define DISP_NR_CLK					116
    777      1.1  jmcneill 
    778      1.1  jmcneill /* CMU_AUD */
    779      1.1  jmcneill #define CLK_MOUT_AUD_PLL_USER				1
    780      1.1  jmcneill #define CLK_MOUT_SCLK_AUD_PCM				2
    781      1.1  jmcneill #define CLK_MOUT_SCLK_AUD_I2S				3
    782      1.1  jmcneill 
    783      1.1  jmcneill #define CLK_DIV_ATCLK_AUD				4
    784      1.1  jmcneill #define CLK_DIV_PCLK_DBG_AUD				5
    785      1.1  jmcneill #define CLK_DIV_ACLK_AUD				6
    786      1.1  jmcneill #define CLK_DIV_AUD_CA5					7
    787      1.1  jmcneill #define CLK_DIV_SCLK_AUD_SLIMBUS			8
    788      1.1  jmcneill #define CLK_DIV_SCLK_AUD_UART				9
    789      1.1  jmcneill #define CLK_DIV_SCLK_AUD_PCM				10
    790      1.1  jmcneill #define CLK_DIV_SCLK_AUD_I2S				11
    791      1.1  jmcneill 
    792      1.1  jmcneill #define CLK_ACLK_INTR_CTRL				12
    793      1.1  jmcneill #define CLK_ACLK_AXIDS2_LPASSP				13
    794      1.1  jmcneill #define CLK_ACLK_AXIDS1_LPASSP				14
    795      1.1  jmcneill #define CLK_ACLK_AXI2APB1_LPASSP			15
    796      1.1  jmcneill #define CLK_ACLK_AXI2APH_LPASSP				16
    797      1.1  jmcneill #define CLK_ACLK_SMMU_LPASSX				17
    798      1.1  jmcneill #define CLK_ACLK_AXIDS0_LPASSP				18
    799      1.1  jmcneill #define CLK_ACLK_AXI2APB0_LPASSP			19
    800      1.1  jmcneill #define CLK_ACLK_XIU_LPASSX				20
    801      1.1  jmcneill #define CLK_ACLK_AUDNP_133				21
    802      1.1  jmcneill #define CLK_ACLK_AUDND_133				22
    803      1.1  jmcneill #define CLK_ACLK_SRAMC					23
    804      1.1  jmcneill #define CLK_ACLK_DMAC					24
    805      1.1  jmcneill #define CLK_PCLK_WDT1					25
    806      1.1  jmcneill #define CLK_PCLK_WDT0					26
    807      1.1  jmcneill #define CLK_PCLK_SFR1					27
    808      1.1  jmcneill #define CLK_PCLK_SMMU_LPASSX				28
    809      1.1  jmcneill #define CLK_PCLK_GPIO_AUD				29
    810      1.1  jmcneill #define CLK_PCLK_PMU_AUD				30
    811      1.1  jmcneill #define CLK_PCLK_SYSREG_AUD				31
    812      1.1  jmcneill #define CLK_PCLK_AUD_SLIMBUS				32
    813      1.1  jmcneill #define CLK_PCLK_AUD_UART				33
    814      1.1  jmcneill #define CLK_PCLK_AUD_PCM				34
    815      1.1  jmcneill #define CLK_PCLK_AUD_I2S				35
    816      1.1  jmcneill #define CLK_PCLK_TIMER					36
    817      1.1  jmcneill #define CLK_PCLK_SFR0_CTRL				37
    818      1.1  jmcneill #define CLK_ATCLK_AUD					38
    819      1.1  jmcneill #define CLK_PCLK_DBG_AUD				39
    820      1.1  jmcneill #define CLK_SCLK_AUD_CA5				40
    821      1.1  jmcneill #define CLK_SCLK_JTAG_TCK				41
    822      1.1  jmcneill #define CLK_SCLK_SLIMBUS_CLKIN				42
    823      1.1  jmcneill #define CLK_SCLK_AUD_SLIMBUS				43
    824      1.1  jmcneill #define CLK_SCLK_AUD_UART				44
    825      1.1  jmcneill #define CLK_SCLK_AUD_PCM				45
    826      1.1  jmcneill #define CLK_SCLK_I2S_BCLK				46
    827      1.1  jmcneill #define CLK_SCLK_AUD_I2S				47
    828      1.1  jmcneill 
    829      1.1  jmcneill #define AUD_NR_CLK					48
    830      1.1  jmcneill 
    831      1.1  jmcneill /* CMU_BUS{0|1|2} */
    832      1.1  jmcneill #define CLK_DIV_PCLK_BUS_133				1
    833      1.1  jmcneill 
    834      1.1  jmcneill #define CLK_ACLK_AHB2APB_BUSP				2
    835      1.1  jmcneill #define CLK_ACLK_BUSNP_133				3
    836      1.1  jmcneill #define CLK_ACLK_BUSND_400				4
    837      1.1  jmcneill #define CLK_PCLK_BUSSRVND_133				5
    838      1.1  jmcneill #define CLK_PCLK_PMU_BUS				6
    839      1.1  jmcneill #define CLK_PCLK_SYSREG_BUS				7
    840      1.1  jmcneill 
    841      1.1  jmcneill #define CLK_MOUT_ACLK_BUS2_400_USER			8  /* Only CMU_BUS2 */
    842      1.1  jmcneill #define CLK_ACLK_BUS2BEND_400				9  /* Only CMU_BUS2 */
    843      1.1  jmcneill #define CLK_ACLK_BUS2RTND_400				10 /* Only CMU_BUS2 */
    844      1.1  jmcneill 
    845      1.1  jmcneill #define BUSx_NR_CLK					11
    846      1.1  jmcneill 
    847      1.1  jmcneill /* CMU_G3D */
    848      1.1  jmcneill #define CLK_FOUT_G3D_PLL				1
    849      1.1  jmcneill 
    850      1.1  jmcneill #define CLK_MOUT_ACLK_G3D_400				2
    851      1.1  jmcneill #define CLK_MOUT_G3D_PLL				3
    852      1.1  jmcneill 
    853      1.1  jmcneill #define CLK_DIV_SCLK_HPM_G3D				4
    854      1.1  jmcneill #define CLK_DIV_PCLK_G3D				5
    855      1.1  jmcneill #define CLK_DIV_ACLK_G3D				6
    856      1.1  jmcneill #define CLK_ACLK_BTS_G3D1				7
    857      1.1  jmcneill #define CLK_ACLK_BTS_G3D0				8
    858      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_G3D				9
    859      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_G3D				10
    860      1.1  jmcneill #define CLK_ACLK_AHB2APB_G3DP				11
    861      1.1  jmcneill #define CLK_ACLK_G3DNP_150				12
    862      1.1  jmcneill #define CLK_ACLK_G3DND_600				13
    863      1.1  jmcneill #define CLK_ACLK_G3D					14
    864      1.1  jmcneill #define CLK_PCLK_BTS_G3D1				15
    865      1.1  jmcneill #define CLK_PCLK_BTS_G3D0				16
    866      1.1  jmcneill #define CLK_PCLK_PMU_G3D				17
    867      1.1  jmcneill #define CLK_PCLK_SYSREG_G3D				18
    868      1.1  jmcneill #define CLK_SCLK_HPM_G3D				19
    869      1.1  jmcneill 
    870      1.1  jmcneill #define G3D_NR_CLK					20
    871      1.1  jmcneill 
    872      1.1  jmcneill /* CMU_GSCL */
    873      1.1  jmcneill #define CLK_MOUT_ACLK_GSCL_111_USER			1
    874      1.1  jmcneill #define CLK_MOUT_ACLK_GSCL_333_USER			2
    875      1.1  jmcneill 
    876      1.1  jmcneill #define CLK_ACLK_BTS_GSCL2				3
    877      1.1  jmcneill #define CLK_ACLK_BTS_GSCL1				4
    878      1.1  jmcneill #define CLK_ACLK_BTS_GSCL0				5
    879      1.1  jmcneill #define CLK_ACLK_AHB2APB_GSCLP				6
    880      1.1  jmcneill #define CLK_ACLK_XIU_GSCLX				7
    881      1.1  jmcneill #define CLK_ACLK_GSCLNP_111				8
    882      1.1  jmcneill #define CLK_ACLK_GSCLRTND_333				9
    883      1.1  jmcneill #define CLK_ACLK_GSCLBEND_333				10
    884      1.1  jmcneill #define CLK_ACLK_GSD					11
    885      1.1  jmcneill #define CLK_ACLK_GSCL2					12
    886      1.1  jmcneill #define CLK_ACLK_GSCL1					13
    887      1.1  jmcneill #define CLK_ACLK_GSCL0					14
    888      1.1  jmcneill #define CLK_ACLK_SMMU_GSCL0				15
    889      1.1  jmcneill #define CLK_ACLK_SMMU_GSCL1				16
    890      1.1  jmcneill #define CLK_ACLK_SMMU_GSCL2				17
    891      1.1  jmcneill #define CLK_PCLK_BTS_GSCL2				18
    892      1.1  jmcneill #define CLK_PCLK_BTS_GSCL1				19
    893      1.1  jmcneill #define CLK_PCLK_BTS_GSCL0				20
    894      1.1  jmcneill #define CLK_PCLK_PMU_GSCL				21
    895      1.1  jmcneill #define CLK_PCLK_SYSREG_GSCL				22
    896      1.1  jmcneill #define CLK_PCLK_GSCL2					23
    897      1.1  jmcneill #define CLK_PCLK_GSCL1					24
    898      1.1  jmcneill #define CLK_PCLK_GSCL0					25
    899      1.1  jmcneill #define CLK_PCLK_SMMU_GSCL0				26
    900      1.1  jmcneill #define CLK_PCLK_SMMU_GSCL1				27
    901      1.1  jmcneill #define CLK_PCLK_SMMU_GSCL2				28
    902      1.1  jmcneill 
    903      1.1  jmcneill #define GSCL_NR_CLK					29
    904      1.1  jmcneill 
    905      1.1  jmcneill /* CMU_APOLLO */
    906      1.1  jmcneill #define CLK_FOUT_APOLLO_PLL				1
    907      1.1  jmcneill 
    908      1.1  jmcneill #define CLK_MOUT_APOLLO_PLL				2
    909      1.1  jmcneill #define CLK_MOUT_BUS_PLL_APOLLO_USER			3
    910      1.1  jmcneill #define CLK_MOUT_APOLLO					4
    911      1.1  jmcneill 
    912      1.1  jmcneill #define CLK_DIV_CNTCLK_APOLLO				5
    913      1.1  jmcneill #define CLK_DIV_PCLK_DBG_APOLLO				6
    914      1.1  jmcneill #define CLK_DIV_ATCLK_APOLLO				7
    915      1.1  jmcneill #define CLK_DIV_PCLK_APOLLO				8
    916      1.1  jmcneill #define CLK_DIV_ACLK_APOLLO				9
    917      1.1  jmcneill #define CLK_DIV_APOLLO2					10
    918      1.1  jmcneill #define CLK_DIV_APOLLO1					11
    919      1.1  jmcneill #define CLK_DIV_SCLK_HPM_APOLLO				12
    920      1.1  jmcneill #define CLK_DIV_APOLLO_PLL				13
    921      1.1  jmcneill 
    922      1.1  jmcneill #define CLK_ACLK_ATBDS_APOLLO_3				14
    923      1.1  jmcneill #define CLK_ACLK_ATBDS_APOLLO_2				15
    924      1.1  jmcneill #define CLK_ACLK_ATBDS_APOLLO_1				16
    925      1.1  jmcneill #define CLK_ACLK_ATBDS_APOLLO_0				17
    926      1.1  jmcneill #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS		18
    927      1.1  jmcneill #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS		19
    928      1.1  jmcneill #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS		20
    929      1.1  jmcneill #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS		21
    930      1.1  jmcneill #define CLK_ACLK_ASYNCACES_APOLLO_CCI			22
    931      1.1  jmcneill #define CLK_ACLK_AHB2APB_APOLLOP			23
    932      1.1  jmcneill #define CLK_ACLK_APOLLONP_200				24
    933      1.1  jmcneill #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO			25
    934      1.1  jmcneill #define CLK_PCLK_PMU_APOLLO				26
    935      1.1  jmcneill #define CLK_PCLK_SYSREG_APOLLO				27
    936      1.1  jmcneill #define CLK_CNTCLK_APOLLO				28
    937      1.1  jmcneill #define CLK_SCLK_HPM_APOLLO				29
    938      1.1  jmcneill #define CLK_SCLK_APOLLO					30
    939      1.1  jmcneill 
    940      1.1  jmcneill #define APOLLO_NR_CLK					31
    941      1.1  jmcneill 
    942      1.1  jmcneill /* CMU_ATLAS */
    943      1.1  jmcneill #define CLK_FOUT_ATLAS_PLL				1
    944      1.1  jmcneill 
    945      1.1  jmcneill #define CLK_MOUT_ATLAS_PLL				2
    946      1.1  jmcneill #define CLK_MOUT_BUS_PLL_ATLAS_USER			3
    947      1.1  jmcneill #define CLK_MOUT_ATLAS					4
    948      1.1  jmcneill 
    949      1.1  jmcneill #define CLK_DIV_CNTCLK_ATLAS				5
    950      1.1  jmcneill #define CLK_DIV_PCLK_DBG_ATLAS				6
    951      1.1  jmcneill #define CLK_DIV_ATCLK_ATLASO				7
    952      1.1  jmcneill #define CLK_DIV_PCLK_ATLAS				8
    953      1.1  jmcneill #define CLK_DIV_ACLK_ATLAS				9
    954      1.1  jmcneill #define CLK_DIV_ATLAS2					10
    955      1.1  jmcneill #define CLK_DIV_ATLAS1					11
    956      1.1  jmcneill #define CLK_DIV_SCLK_HPM_ATLAS				12
    957      1.1  jmcneill #define CLK_DIV_ATLAS_PLL				13
    958      1.1  jmcneill 
    959      1.1  jmcneill #define CLK_ACLK_ATB_AUD_CSSYS				14
    960      1.1  jmcneill #define CLK_ACLK_ATB_APOLLO3_CSSYS			15
    961      1.1  jmcneill #define CLK_ACLK_ATB_APOLLO2_CSSYS			16
    962      1.1  jmcneill #define CLK_ACLK_ATB_APOLLO1_CSSYS			17
    963      1.1  jmcneill #define CLK_ACLK_ATB_APOLLO0_CSSYS			18
    964      1.1  jmcneill #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS			19
    965      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX			20
    966      1.1  jmcneill #define CLK_ACLK_ASYNCACES_ATLAS_CCI			21
    967      1.1  jmcneill #define CLK_ACLK_AHB2APB_ATLASP				22
    968      1.1  jmcneill #define CLK_ACLK_ATLASNP_200				23
    969      1.1  jmcneill #define CLK_PCLK_ASYNCAPB_AUD_CSSYS			24
    970      1.1  jmcneill #define CLK_PCLK_ASYNCAPB_ISP_CSSYS			25
    971      1.1  jmcneill #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS			26
    972      1.1  jmcneill #define CLK_PCLK_PMU_ATLAS				27
    973      1.1  jmcneill #define CLK_PCLK_SYSREG_ATLAS				28
    974      1.1  jmcneill #define CLK_PCLK_SECJTAG				29
    975      1.1  jmcneill #define CLK_CNTCLK_ATLAS				30
    976      1.1  jmcneill #define CLK_SCLK_FREQ_DET_ATLAS_PLL			31
    977      1.1  jmcneill #define CLK_SCLK_HPM_ATLAS				32
    978      1.1  jmcneill #define CLK_TRACECLK					33
    979      1.1  jmcneill #define CLK_CTMCLK					34
    980      1.1  jmcneill #define CLK_HCLK_CSSYS					35
    981      1.1  jmcneill #define CLK_PCLK_DBG_CSSYS				36
    982      1.1  jmcneill #define CLK_PCLK_DBG					37
    983      1.1  jmcneill #define CLK_ATCLK					38
    984      1.1  jmcneill #define CLK_SCLK_ATLAS					39
    985      1.1  jmcneill 
    986      1.1  jmcneill #define ATLAS_NR_CLK					40
    987      1.1  jmcneill 
    988      1.1  jmcneill /* CMU_MSCL */
    989      1.1  jmcneill #define CLK_MOUT_SCLK_JPEG_USER				1
    990      1.1  jmcneill #define CLK_MOUT_ACLK_MSCL_400_USER			2
    991      1.1  jmcneill #define CLK_MOUT_SCLK_JPEG				3
    992      1.1  jmcneill 
    993      1.1  jmcneill #define CLK_DIV_PCLK_MSCL				4
    994      1.1  jmcneill 
    995      1.1  jmcneill #define CLK_ACLK_BTS_JPEG				5
    996      1.1  jmcneill #define CLK_ACLK_BTS_M2MSCALER1				6
    997      1.1  jmcneill #define CLK_ACLK_BTS_M2MSCALER0				7
    998      1.1  jmcneill #define CLK_ACLK_AHB2APB_MSCL0P				8
    999      1.1  jmcneill #define CLK_ACLK_XIU_MSCLX				9
   1000      1.1  jmcneill #define CLK_ACLK_MSCLNP_100				10
   1001      1.1  jmcneill #define CLK_ACLK_MSCLND_400				11
   1002      1.1  jmcneill #define CLK_ACLK_JPEG					12
   1003      1.1  jmcneill #define CLK_ACLK_M2MSCALER1				13
   1004      1.1  jmcneill #define CLK_ACLK_M2MSCALER0				14
   1005      1.1  jmcneill #define CLK_ACLK_SMMU_M2MSCALER0			15
   1006      1.1  jmcneill #define CLK_ACLK_SMMU_M2MSCALER1			16
   1007      1.1  jmcneill #define CLK_ACLK_SMMU_JPEG				17
   1008      1.1  jmcneill #define CLK_PCLK_BTS_JPEG				18
   1009      1.1  jmcneill #define CLK_PCLK_BTS_M2MSCALER1				19
   1010      1.1  jmcneill #define CLK_PCLK_BTS_M2MSCALER0				20
   1011      1.1  jmcneill #define CLK_PCLK_PMU_MSCL				21
   1012      1.1  jmcneill #define CLK_PCLK_SYSREG_MSCL				22
   1013      1.1  jmcneill #define CLK_PCLK_JPEG					23
   1014      1.1  jmcneill #define CLK_PCLK_M2MSCALER1				24
   1015      1.1  jmcneill #define CLK_PCLK_M2MSCALER0				25
   1016      1.1  jmcneill #define CLK_PCLK_SMMU_M2MSCALER0			26
   1017      1.1  jmcneill #define CLK_PCLK_SMMU_M2MSCALER1			27
   1018      1.1  jmcneill #define CLK_PCLK_SMMU_JPEG				28
   1019      1.1  jmcneill #define CLK_SCLK_JPEG					29
   1020      1.1  jmcneill 
   1021      1.1  jmcneill #define MSCL_NR_CLK					30
   1022      1.1  jmcneill 
   1023      1.1  jmcneill /* CMU_MFC */
   1024      1.1  jmcneill #define CLK_MOUT_ACLK_MFC_400_USER			1
   1025      1.1  jmcneill 
   1026      1.1  jmcneill #define CLK_DIV_PCLK_MFC				2
   1027      1.1  jmcneill 
   1028      1.1  jmcneill #define CLK_ACLK_BTS_MFC_1				3
   1029      1.1  jmcneill #define CLK_ACLK_BTS_MFC_0				4
   1030      1.1  jmcneill #define CLK_ACLK_AHB2APB_MFCP				5
   1031      1.1  jmcneill #define CLK_ACLK_XIU_MFCX				6
   1032      1.1  jmcneill #define CLK_ACLK_MFCNP_100				7
   1033      1.1  jmcneill #define CLK_ACLK_MFCND_400				8
   1034      1.1  jmcneill #define CLK_ACLK_MFC					9
   1035      1.1  jmcneill #define CLK_ACLK_SMMU_MFC_1				10
   1036      1.1  jmcneill #define CLK_ACLK_SMMU_MFC_0				11
   1037      1.1  jmcneill #define CLK_PCLK_BTS_MFC_1				12
   1038      1.1  jmcneill #define CLK_PCLK_BTS_MFC_0				13
   1039      1.1  jmcneill #define CLK_PCLK_PMU_MFC				14
   1040      1.1  jmcneill #define CLK_PCLK_SYSREG_MFC				15
   1041      1.1  jmcneill #define CLK_PCLK_MFC					16
   1042      1.1  jmcneill #define CLK_PCLK_SMMU_MFC_1				17
   1043      1.1  jmcneill #define CLK_PCLK_SMMU_MFC_0				18
   1044      1.1  jmcneill 
   1045      1.1  jmcneill #define MFC_NR_CLK					19
   1046      1.1  jmcneill 
   1047      1.1  jmcneill /* CMU_HEVC */
   1048      1.1  jmcneill #define CLK_MOUT_ACLK_HEVC_400_USER			1
   1049      1.1  jmcneill 
   1050      1.1  jmcneill #define CLK_DIV_PCLK_HEVC				2
   1051      1.1  jmcneill 
   1052      1.1  jmcneill #define CLK_ACLK_BTS_HEVC_1				3
   1053      1.1  jmcneill #define CLK_ACLK_BTS_HEVC_0				4
   1054      1.1  jmcneill #define CLK_ACLK_AHB2APB_HEVCP				5
   1055      1.1  jmcneill #define CLK_ACLK_XIU_HEVCX				6
   1056      1.1  jmcneill #define CLK_ACLK_HEVCNP_100				7
   1057      1.1  jmcneill #define CLK_ACLK_HEVCND_400				8
   1058      1.1  jmcneill #define CLK_ACLK_HEVC					9
   1059      1.1  jmcneill #define CLK_ACLK_SMMU_HEVC_1				10
   1060      1.1  jmcneill #define CLK_ACLK_SMMU_HEVC_0				11
   1061      1.1  jmcneill #define CLK_PCLK_BTS_HEVC_1				12
   1062      1.1  jmcneill #define CLK_PCLK_BTS_HEVC_0				13
   1063      1.1  jmcneill #define CLK_PCLK_PMU_HEVC				14
   1064      1.1  jmcneill #define CLK_PCLK_SYSREG_HEVC				15
   1065      1.1  jmcneill #define CLK_PCLK_HEVC					16
   1066      1.1  jmcneill #define CLK_PCLK_SMMU_HEVC_1				17
   1067      1.1  jmcneill #define CLK_PCLK_SMMU_HEVC_0				18
   1068      1.1  jmcneill 
   1069      1.1  jmcneill #define HEVC_NR_CLK					19
   1070      1.1  jmcneill 
   1071      1.1  jmcneill /* CMU_ISP */
   1072      1.1  jmcneill #define CLK_MOUT_ACLK_ISP_DIS_400_USER			1
   1073      1.1  jmcneill #define CLK_MOUT_ACLK_ISP_400_USER			2
   1074      1.1  jmcneill 
   1075      1.1  jmcneill #define CLK_DIV_PCLK_ISP_DIS				3
   1076      1.1  jmcneill #define CLK_DIV_PCLK_ISP				4
   1077      1.1  jmcneill #define CLK_DIV_ACLK_ISP_D_200				5
   1078      1.1  jmcneill #define CLK_DIV_ACLK_ISP_C_200				6
   1079      1.1  jmcneill 
   1080      1.1  jmcneill #define CLK_ACLK_ISP_D_GLUE				7
   1081      1.1  jmcneill #define CLK_ACLK_SCALERP				8
   1082      1.1  jmcneill #define CLK_ACLK_3DNR					9
   1083      1.1  jmcneill #define CLK_ACLK_DIS					10
   1084      1.1  jmcneill #define CLK_ACLK_SCALERC				11
   1085      1.1  jmcneill #define CLK_ACLK_DRC					12
   1086      1.1  jmcneill #define CLK_ACLK_ISP					13
   1087      1.1  jmcneill #define CLK_ACLK_AXIUS_SCALERP				14
   1088      1.1  jmcneill #define CLK_ACLK_AXIUS_SCALERC				15
   1089      1.1  jmcneill #define CLK_ACLK_AXIUS_DRC				16
   1090      1.1  jmcneill #define CLK_ACLK_ASYNCAHBM_ISP2P			17
   1091      1.1  jmcneill #define CLK_ACLK_ASYNCAHBM_ISP1P			18
   1092      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DIS1				19
   1093      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_DIS0				20
   1094      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DIS1				21
   1095      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_DIS0				22
   1096      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_ISP2P			23
   1097      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_ISP1P			24
   1098      1.1  jmcneill #define CLK_ACLK_AHB2APB_ISP2P				25
   1099      1.1  jmcneill #define CLK_ACLK_AHB2APB_ISP1P				26
   1100      1.1  jmcneill #define CLK_ACLK_AXI2APB_ISP2P				27
   1101      1.1  jmcneill #define CLK_ACLK_AXI2APB_ISP1P				28
   1102      1.1  jmcneill #define CLK_ACLK_XIU_ISPEX1				29
   1103      1.1  jmcneill #define CLK_ACLK_XIU_ISPEX0				30
   1104      1.1  jmcneill #define CLK_ACLK_ISPND_400				31
   1105      1.1  jmcneill #define CLK_ACLK_SMMU_SCALERP				32
   1106      1.1  jmcneill #define CLK_ACLK_SMMU_3DNR				33
   1107      1.1  jmcneill #define CLK_ACLK_SMMU_DIS1				34
   1108      1.1  jmcneill #define CLK_ACLK_SMMU_DIS0				35
   1109      1.1  jmcneill #define CLK_ACLK_SMMU_SCALERC				36
   1110      1.1  jmcneill #define CLK_ACLK_SMMU_DRC				37
   1111      1.1  jmcneill #define CLK_ACLK_SMMU_ISP				38
   1112      1.1  jmcneill #define CLK_ACLK_BTS_SCALERP				39
   1113      1.1  jmcneill #define CLK_ACLK_BTS_3DR				40
   1114      1.1  jmcneill #define CLK_ACLK_BTS_DIS1				41
   1115      1.1  jmcneill #define CLK_ACLK_BTS_DIS0				42
   1116      1.1  jmcneill #define CLK_ACLK_BTS_SCALERC				43
   1117      1.1  jmcneill #define CLK_ACLK_BTS_DRC				44
   1118      1.1  jmcneill #define CLK_ACLK_BTS_ISP				45
   1119      1.1  jmcneill #define CLK_PCLK_SMMU_SCALERP				46
   1120      1.1  jmcneill #define CLK_PCLK_SMMU_3DNR				47
   1121      1.1  jmcneill #define CLK_PCLK_SMMU_DIS1				48
   1122      1.1  jmcneill #define CLK_PCLK_SMMU_DIS0				49
   1123      1.1  jmcneill #define CLK_PCLK_SMMU_SCALERC				50
   1124      1.1  jmcneill #define CLK_PCLK_SMMU_DRC				51
   1125      1.1  jmcneill #define CLK_PCLK_SMMU_ISP				52
   1126      1.1  jmcneill #define CLK_PCLK_BTS_SCALERP				53
   1127      1.1  jmcneill #define CLK_PCLK_BTS_3DNR				54
   1128      1.1  jmcneill #define CLK_PCLK_BTS_DIS1				55
   1129      1.1  jmcneill #define CLK_PCLK_BTS_DIS0				56
   1130      1.1  jmcneill #define CLK_PCLK_BTS_SCALERC				57
   1131      1.1  jmcneill #define CLK_PCLK_BTS_DRC				58
   1132      1.1  jmcneill #define CLK_PCLK_BTS_ISP				59
   1133      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DIS1				60
   1134      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_DIS0				61
   1135      1.1  jmcneill #define CLK_PCLK_PMU_ISP				62
   1136      1.1  jmcneill #define CLK_PCLK_SYSREG_ISP				63
   1137      1.1  jmcneill #define CLK_PCLK_CMU_ISP_LOCAL				64
   1138      1.1  jmcneill #define CLK_PCLK_SCALERP				65
   1139      1.1  jmcneill #define CLK_PCLK_3DNR					66
   1140      1.1  jmcneill #define CLK_PCLK_DIS_CORE				67
   1141      1.1  jmcneill #define CLK_PCLK_DIS					68
   1142      1.1  jmcneill #define CLK_PCLK_SCALERC				69
   1143      1.1  jmcneill #define CLK_PCLK_DRC					70
   1144      1.1  jmcneill #define CLK_PCLK_ISP					71
   1145      1.1  jmcneill #define CLK_SCLK_PIXELASYNCS_DIS			72
   1146      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_DIS			73
   1147      1.1  jmcneill #define CLK_SCLK_PIXELASYNCS_SCALERP			74
   1148      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_ISPD			75
   1149      1.1  jmcneill #define CLK_SCLK_PIXELASYNCS_ISPC			76
   1150      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_ISPC			77
   1151      1.1  jmcneill 
   1152      1.1  jmcneill #define ISP_NR_CLK					78
   1153      1.1  jmcneill 
   1154      1.1  jmcneill /* CMU_CAM0 */
   1155      1.1  jmcneill #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY			1
   1156      1.1  jmcneill #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY		2
   1157      1.1  jmcneill 
   1158      1.1  jmcneill #define CLK_MOUT_ACLK_CAM0_333_USER			3
   1159      1.1  jmcneill #define CLK_MOUT_ACLK_CAM0_400_USER			4
   1160      1.1  jmcneill #define CLK_MOUT_ACLK_CAM0_552_USER			5
   1161      1.1  jmcneill #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER		6
   1162      1.1  jmcneill #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER		7
   1163      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_D_B				8
   1164      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_D_A				9
   1165      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_B_B				10
   1166      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_B_A				11
   1167      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_A_B				12
   1168      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_A_A				13
   1169      1.1  jmcneill #define CLK_MOUT_ACLK_CAM0_400				14
   1170      1.1  jmcneill #define CLK_MOUT_ACLK_CSIS1_B				15
   1171      1.1  jmcneill #define CLK_MOUT_ACLK_CSIS1_A				16
   1172      1.1  jmcneill #define CLK_MOUT_ACLK_CSIS0_B				17
   1173      1.1  jmcneill #define CLK_MOUT_ACLK_CSIS0_A				18
   1174      1.1  jmcneill #define CLK_MOUT_ACLK_3AA1_B				19
   1175      1.1  jmcneill #define CLK_MOUT_ACLK_3AA1_A				20
   1176      1.1  jmcneill #define CLK_MOUT_ACLK_3AA0_B				21
   1177      1.1  jmcneill #define CLK_MOUT_ACLK_3AA0_A				22
   1178      1.1  jmcneill #define CLK_MOUT_SCLK_LITE_FREECNT_C			23
   1179      1.1  jmcneill #define CLK_MOUT_SCLK_LITE_FREECNT_B			24
   1180      1.1  jmcneill #define CLK_MOUT_SCLK_LITE_FREECNT_A			25
   1181      1.1  jmcneill #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B		26
   1182      1.1  jmcneill #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A		27
   1183      1.1  jmcneill #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B		28
   1184      1.1  jmcneill #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A		29
   1185      1.1  jmcneill 
   1186      1.1  jmcneill #define CLK_DIV_PCLK_CAM0_50				30
   1187      1.1  jmcneill #define CLK_DIV_ACLK_CAM0_200				31
   1188      1.1  jmcneill #define CLK_DIV_ACLK_CAM0_BUS_400			32
   1189      1.1  jmcneill #define CLK_DIV_PCLK_LITE_D				33
   1190      1.1  jmcneill #define CLK_DIV_ACLK_LITE_D				34
   1191      1.1  jmcneill #define CLK_DIV_PCLK_LITE_B				35
   1192      1.1  jmcneill #define CLK_DIV_ACLK_LITE_B				36
   1193      1.1  jmcneill #define CLK_DIV_PCLK_LITE_A				37
   1194      1.1  jmcneill #define CLK_DIV_ACLK_LITE_A				38
   1195      1.1  jmcneill #define CLK_DIV_ACLK_CSIS1				39
   1196      1.1  jmcneill #define CLK_DIV_ACLK_CSIS0				40
   1197      1.1  jmcneill #define CLK_DIV_PCLK_3AA1				41
   1198      1.1  jmcneill #define CLK_DIV_ACLK_3AA1				42
   1199      1.1  jmcneill #define CLK_DIV_PCLK_3AA0				43
   1200      1.1  jmcneill #define CLK_DIV_ACLK_3AA0				44
   1201      1.1  jmcneill #define CLK_DIV_SCLK_PIXELASYNC_LITE_C			45
   1202      1.1  jmcneill #define CLK_DIV_PCLK_PIXELASYNC_LITE_C			46
   1203      1.1  jmcneill #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT		47
   1204      1.1  jmcneill 
   1205      1.1  jmcneill #define CLK_ACLK_CSIS1					50
   1206      1.1  jmcneill #define CLK_ACLK_CSIS0					51
   1207      1.1  jmcneill #define CLK_ACLK_3AA1					52
   1208      1.1  jmcneill #define CLK_ACLK_3AA0					53
   1209      1.1  jmcneill #define CLK_ACLK_LITE_D					54
   1210      1.1  jmcneill #define CLK_ACLK_LITE_B					55
   1211      1.1  jmcneill #define CLK_ACLK_LITE_A					56
   1212      1.1  jmcneill #define CLK_ACLK_AHBSYNCDN				57
   1213      1.1  jmcneill #define CLK_ACLK_AXIUS_LITE_D				58
   1214      1.1  jmcneill #define CLK_ACLK_AXIUS_LITE_B				59
   1215      1.1  jmcneill #define CLK_ACLK_AXIUS_LITE_A				60
   1216      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_3AA1				61
   1217      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_3AA1				62
   1218      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_3AA0				63
   1219      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_3AA0				64
   1220      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_LITE_D			65
   1221      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_LITE_D			66
   1222      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_LITE_B			67
   1223      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_LITE_B			68
   1224      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_LITE_A			69
   1225      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_LITE_A			70
   1226      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_ISP0P			71
   1227      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_3AA1				72
   1228      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_3AA1				73
   1229      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_3AA0				74
   1230      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_3AA0				75
   1231      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_LITE_D			76
   1232      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_LITE_D			77
   1233      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_LITE_B			78
   1234      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_LITE_B			79
   1235      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_LITE_A			80
   1236      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_LITE_A			81
   1237      1.1  jmcneill #define CLK_ACLK_AHB2APB_ISPSFRP			82
   1238      1.1  jmcneill #define CLK_ACLK_AXI2APB_ISP0P				83
   1239      1.1  jmcneill #define CLK_ACLK_AXI2AHB_ISP0P				84
   1240      1.1  jmcneill #define CLK_ACLK_XIU_IS0X				85
   1241      1.1  jmcneill #define CLK_ACLK_XIU_ISP0EX				86
   1242      1.1  jmcneill #define CLK_ACLK_CAM0NP_276				87
   1243      1.1  jmcneill #define CLK_ACLK_CAM0ND_400				88
   1244      1.1  jmcneill #define CLK_ACLK_SMMU_3AA1				89
   1245      1.1  jmcneill #define CLK_ACLK_SMMU_3AA0				90
   1246      1.1  jmcneill #define CLK_ACLK_SMMU_LITE_D				91
   1247      1.1  jmcneill #define CLK_ACLK_SMMU_LITE_B				92
   1248      1.1  jmcneill #define CLK_ACLK_SMMU_LITE_A				93
   1249      1.1  jmcneill #define CLK_ACLK_BTS_3AA1				94
   1250      1.1  jmcneill #define CLK_ACLK_BTS_3AA0				95
   1251      1.1  jmcneill #define CLK_ACLK_BTS_LITE_D				96
   1252      1.1  jmcneill #define CLK_ACLK_BTS_LITE_B				97
   1253      1.1  jmcneill #define CLK_ACLK_BTS_LITE_A				98
   1254      1.1  jmcneill #define CLK_PCLK_SMMU_3AA1				99
   1255      1.1  jmcneill #define CLK_PCLK_SMMU_3AA0				100
   1256      1.1  jmcneill #define CLK_PCLK_SMMU_LITE_D				101
   1257      1.1  jmcneill #define CLK_PCLK_SMMU_LITE_B				102
   1258      1.1  jmcneill #define CLK_PCLK_SMMU_LITE_A				103
   1259      1.1  jmcneill #define CLK_PCLK_BTS_3AA1				104
   1260      1.1  jmcneill #define CLK_PCLK_BTS_3AA0				105
   1261      1.1  jmcneill #define CLK_PCLK_BTS_LITE_D				106
   1262      1.1  jmcneill #define CLK_PCLK_BTS_LITE_B				107
   1263      1.1  jmcneill #define CLK_PCLK_BTS_LITE_A				108
   1264      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_CAM1				109
   1265      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_3AA1				110
   1266      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_3AA0				111
   1267      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_LITE_D			112
   1268      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_LITE_B			113
   1269      1.1  jmcneill #define CLK_PCLK_ASYNCAXI_LITE_A			114
   1270      1.1  jmcneill #define CLK_PCLK_PMU_CAM0				115
   1271      1.1  jmcneill #define CLK_PCLK_SYSREG_CAM0				116
   1272      1.1  jmcneill #define CLK_PCLK_CMU_CAM0_LOCAL				117
   1273      1.1  jmcneill #define CLK_PCLK_CSIS1					118
   1274      1.1  jmcneill #define CLK_PCLK_CSIS0					119
   1275      1.1  jmcneill #define CLK_PCLK_3AA1					120
   1276      1.1  jmcneill #define CLK_PCLK_3AA0					121
   1277      1.1  jmcneill #define CLK_PCLK_LITE_D					122
   1278      1.1  jmcneill #define CLK_PCLK_LITE_B					123
   1279      1.1  jmcneill #define CLK_PCLK_LITE_A					124
   1280      1.1  jmcneill #define CLK_PHYCLK_RXBYTECLKHS0_S4			125
   1281      1.1  jmcneill #define CLK_PHYCLK_RXBYTECLKHS0_S2A			126
   1282      1.1  jmcneill #define CLK_SCLK_LITE_FREECNT				127
   1283      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_3AA1			128
   1284      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_3AA0			129
   1285      1.1  jmcneill #define CLK_SCLK_PIXELASYNCS_3AA0			130
   1286      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_LITE_C			131
   1287      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT		132
   1288      1.1  jmcneill #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT		133
   1289      1.1  jmcneill 
   1290      1.1  jmcneill #define CAM0_NR_CLK					134
   1291      1.1  jmcneill 
   1292      1.1  jmcneill /* CMU_CAM1 */
   1293      1.1  jmcneill #define CLK_PHYCLK_RXBYTEECLKHS0_S2B			1
   1294      1.1  jmcneill 
   1295      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_UART_USER			2
   1296      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_SPI1_USER			3
   1297      1.1  jmcneill #define CLK_MOUT_SCLK_ISP_SPI0_USER			4
   1298      1.1  jmcneill #define CLK_MOUT_ACLK_CAM1_333_USER			5
   1299      1.1  jmcneill #define CLK_MOUT_ACLK_CAM1_400_USER			6
   1300      1.1  jmcneill #define CLK_MOUT_ACLK_CAM1_552_USER			7
   1301      1.1  jmcneill #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER		8
   1302      1.1  jmcneill #define CLK_MOUT_ACLK_CSIS2_B				9
   1303      1.1  jmcneill #define CLK_MOUT_ACLK_CSIS2_A				10
   1304      1.1  jmcneill #define CLK_MOUT_ACLK_FD_B				11
   1305      1.1  jmcneill #define CLK_MOUT_ACLK_FD_A				12
   1306      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_C_B				13
   1307      1.1  jmcneill #define CLK_MOUT_ACLK_LITE_C_A				14
   1308      1.1  jmcneill 
   1309      1.1  jmcneill #define CLK_DIV_SCLK_ISP_MPWM				15
   1310      1.1  jmcneill #define CLK_DIV_PCLK_CAM1_83				16
   1311      1.1  jmcneill #define CLK_DIV_PCLK_CAM1_166				17
   1312      1.1  jmcneill #define CLK_DIV_PCLK_DBG_CAM1				18
   1313      1.1  jmcneill #define CLK_DIV_ATCLK_CAM1				19
   1314      1.1  jmcneill #define CLK_DIV_ACLK_CSIS2				20
   1315      1.1  jmcneill #define CLK_DIV_PCLK_FD					21
   1316      1.1  jmcneill #define CLK_DIV_ACLK_FD					22
   1317      1.1  jmcneill #define CLK_DIV_PCLK_LITE_C				23
   1318      1.1  jmcneill #define CLK_DIV_ACLK_LITE_C				24
   1319      1.1  jmcneill 
   1320      1.1  jmcneill #define CLK_ACLK_ISP_GIC				25
   1321      1.1  jmcneill #define CLK_ACLK_FD					26
   1322      1.1  jmcneill #define CLK_ACLK_LITE_C					27
   1323      1.1  jmcneill #define CLK_ACLK_CSIS2					28
   1324      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_FD				29
   1325      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_FD				30
   1326      1.1  jmcneill #define CLK_ACLK_ASYNCAPBM_LITE_C			31
   1327      1.1  jmcneill #define CLK_ACLK_ASYNCAPBS_LITE_C			32
   1328      1.1  jmcneill #define CLK_ACLK_ASYNCAHBS_SFRISP2H2			33
   1329      1.1  jmcneill #define CLK_ACLK_ASYNCAHBS_SFRISP2H1			34
   1330      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_CA5				35
   1331      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_CA5				36
   1332      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_ISPX2			37
   1333      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_ISPX1			38
   1334      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_ISPX0			39
   1335      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_ISPEX			40
   1336      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_ISP3P			41
   1337      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_ISP3P			42
   1338      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_FD				43
   1339      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_FD				44
   1340      1.1  jmcneill #define CLK_ACLK_ASYNCAXIM_LITE_C			45
   1341      1.1  jmcneill #define CLK_ACLK_ASYNCAXIS_LITE_C			46
   1342      1.1  jmcneill #define CLK_ACLK_AHB2APB_ISP5P				47
   1343      1.1  jmcneill #define CLK_ACLK_AHB2APB_ISP3P				48
   1344      1.1  jmcneill #define CLK_ACLK_AXI2APB_ISP3P				49
   1345      1.1  jmcneill #define CLK_ACLK_AHB_SFRISP2H				50
   1346      1.1  jmcneill #define CLK_ACLK_AXI_ISP_HX_R				51
   1347      1.1  jmcneill #define CLK_ACLK_AXI_ISP_CX_R				52
   1348      1.1  jmcneill #define CLK_ACLK_AXI_ISP_HX				53
   1349      1.1  jmcneill #define CLK_ACLK_AXI_ISP_CX				54
   1350      1.1  jmcneill #define CLK_ACLK_XIU_ISPX				55
   1351      1.1  jmcneill #define CLK_ACLK_XIU_ISPEX				56
   1352      1.1  jmcneill #define CLK_ACLK_CAM1NP_333				57
   1353      1.1  jmcneill #define CLK_ACLK_CAM1ND_400				58
   1354      1.1  jmcneill #define CLK_ACLK_SMMU_ISPCPU				59
   1355      1.1  jmcneill #define CLK_ACLK_SMMU_FD				60
   1356      1.1  jmcneill #define CLK_ACLK_SMMU_LITE_C				61
   1357      1.1  jmcneill #define CLK_ACLK_BTS_ISP3P				62
   1358      1.1  jmcneill #define CLK_ACLK_BTS_FD					63
   1359      1.1  jmcneill #define CLK_ACLK_BTS_LITE_C				64
   1360      1.1  jmcneill #define CLK_ACLK_AHBDN_SFRISP2H				65
   1361      1.1  jmcneill #define CLK_ACLK_AHBDN_ISP5P				66
   1362      1.1  jmcneill #define CLK_ACLK_AXIUS_ISP3P				67
   1363      1.1  jmcneill #define CLK_ACLK_AXIUS_FD				68
   1364      1.1  jmcneill #define CLK_ACLK_AXIUS_LITE_C				69
   1365      1.1  jmcneill #define CLK_PCLK_SMMU_ISPCPU				70
   1366      1.1  jmcneill #define CLK_PCLK_SMMU_FD				71
   1367      1.1  jmcneill #define CLK_PCLK_SMMU_LITE_C				72
   1368      1.1  jmcneill #define CLK_PCLK_BTS_ISP3P				73
   1369      1.1  jmcneill #define CLK_PCLK_BTS_FD					74
   1370      1.1  jmcneill #define CLK_PCLK_BTS_LITE_C				75
   1371      1.1  jmcneill #define CLK_PCLK_ASYNCAXIM_CA5				76
   1372      1.1  jmcneill #define CLK_PCLK_ASYNCAXIM_ISPEX			77
   1373      1.1  jmcneill #define CLK_PCLK_ASYNCAXIM_ISP3P			78
   1374      1.1  jmcneill #define CLK_PCLK_ASYNCAXIM_FD				79
   1375      1.1  jmcneill #define CLK_PCLK_ASYNCAXIM_LITE_C			80
   1376      1.1  jmcneill #define CLK_PCLK_PMU_CAM1				81
   1377      1.1  jmcneill #define CLK_PCLK_SYSREG_CAM1				82
   1378      1.1  jmcneill #define CLK_PCLK_CMU_CAM1_LOCAL				83
   1379      1.1  jmcneill #define CLK_PCLK_ISP_MCTADC				84
   1380      1.1  jmcneill #define CLK_PCLK_ISP_WDT				85
   1381      1.1  jmcneill #define CLK_PCLK_ISP_PWM				86
   1382      1.1  jmcneill #define CLK_PCLK_ISP_UART				87
   1383      1.1  jmcneill #define CLK_PCLK_ISP_MCUCTL				88
   1384      1.1  jmcneill #define CLK_PCLK_ISP_SPI1				89
   1385      1.1  jmcneill #define CLK_PCLK_ISP_SPI0				90
   1386      1.1  jmcneill #define CLK_PCLK_ISP_I2C2				91
   1387      1.1  jmcneill #define CLK_PCLK_ISP_I2C1				92
   1388      1.1  jmcneill #define CLK_PCLK_ISP_I2C0				93
   1389      1.1  jmcneill #define CLK_PCLK_ISP_MPWM				94
   1390      1.1  jmcneill #define CLK_PCLK_FD					95
   1391      1.1  jmcneill #define CLK_PCLK_LITE_C					96
   1392      1.1  jmcneill #define CLK_PCLK_CSIS2					97
   1393      1.1  jmcneill #define CLK_SCLK_ISP_I2C2				98
   1394      1.1  jmcneill #define CLK_SCLK_ISP_I2C1				99
   1395      1.1  jmcneill #define CLK_SCLK_ISP_I2C0				100
   1396      1.1  jmcneill #define CLK_SCLK_ISP_PWM				101
   1397      1.1  jmcneill #define CLK_PHYCLK_RXBYTECLKHS0_S2B			102
   1398      1.1  jmcneill #define CLK_SCLK_LITE_C_FREECNT				103
   1399      1.1  jmcneill #define CLK_SCLK_PIXELASYNCM_FD				104
   1400      1.1  jmcneill #define CLK_SCLK_ISP_MCTADC				105
   1401      1.1  jmcneill #define CLK_SCLK_ISP_UART				106
   1402      1.1  jmcneill #define CLK_SCLK_ISP_SPI1				107
   1403      1.1  jmcneill #define CLK_SCLK_ISP_SPI0				108
   1404      1.1  jmcneill #define CLK_SCLK_ISP_MPWM				109
   1405      1.1  jmcneill #define CLK_PCLK_DBG_ISP				110
   1406      1.1  jmcneill #define CLK_ATCLK_ISP					111
   1407      1.1  jmcneill #define CLK_SCLK_ISP_CA5				112
   1408      1.1  jmcneill 
   1409      1.1  jmcneill #define CAM1_NR_CLK					113
   1410      1.1  jmcneill 
   1411  1.1.1.3  jmcneill /* CMU_IMEM */
   1412  1.1.1.3  jmcneill #define CLK_ACLK_SLIMSSS		2
   1413  1.1.1.3  jmcneill #define CLK_PCLK_SLIMSSS		35
   1414  1.1.1.3  jmcneill 
   1415  1.1.1.3  jmcneill #define IMEM_NR_CLK			36
   1416  1.1.1.3  jmcneill 
   1417      1.1  jmcneill #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
   1418