hi3559av100-clock.h revision 1.1.1.1
1/* $NetBSD: hi3559av100-clock.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-2-Clause */ 4/* 5 * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd. 6 * 7 * Author: Dongjiu Geng <gengdongjiu@huawei.com> 8 */ 9 10#ifndef __DTS_HI3559AV100_CLOCK_H 11#define __DTS_HI3559AV100_CLOCK_H 12 13/* fixed rate */ 14#define HI3559AV100_FIXED_1188M 1 15#define HI3559AV100_FIXED_1000M 2 16#define HI3559AV100_FIXED_842M 3 17#define HI3559AV100_FIXED_792M 4 18#define HI3559AV100_FIXED_750M 5 19#define HI3559AV100_FIXED_710M 6 20#define HI3559AV100_FIXED_680M 7 21#define HI3559AV100_FIXED_667M 8 22#define HI3559AV100_FIXED_631M 9 23#define HI3559AV100_FIXED_600M 10 24#define HI3559AV100_FIXED_568M 11 25#define HI3559AV100_FIXED_500M 12 26#define HI3559AV100_FIXED_475M 13 27#define HI3559AV100_FIXED_428M 14 28#define HI3559AV100_FIXED_400M 15 29#define HI3559AV100_FIXED_396M 16 30#define HI3559AV100_FIXED_300M 17 31#define HI3559AV100_FIXED_250M 18 32#define HI3559AV100_FIXED_198M 19 33#define HI3559AV100_FIXED_187p5M 20 34#define HI3559AV100_FIXED_150M 21 35#define HI3559AV100_FIXED_148p5M 22 36#define HI3559AV100_FIXED_125M 23 37#define HI3559AV100_FIXED_107M 24 38#define HI3559AV100_FIXED_100M 25 39#define HI3559AV100_FIXED_99M 26 40#define HI3559AV100_FIXED_74p25M 27 41#define HI3559AV100_FIXED_72M 28 42#define HI3559AV100_FIXED_60M 29 43#define HI3559AV100_FIXED_54M 30 44#define HI3559AV100_FIXED_50M 31 45#define HI3559AV100_FIXED_49p5M 32 46#define HI3559AV100_FIXED_37p125M 33 47#define HI3559AV100_FIXED_36M 34 48#define HI3559AV100_FIXED_32p4M 35 49#define HI3559AV100_FIXED_27M 36 50#define HI3559AV100_FIXED_25M 37 51#define HI3559AV100_FIXED_24M 38 52#define HI3559AV100_FIXED_12M 39 53#define HI3559AV100_FIXED_3M 40 54#define HI3559AV100_FIXED_1p6M 41 55#define HI3559AV100_FIXED_400K 42 56#define HI3559AV100_FIXED_100K 43 57#define HI3559AV100_FIXED_200M 44 58#define HI3559AV100_FIXED_75M 75 59 60#define HI3559AV100_I2C0_CLK 50 61#define HI3559AV100_I2C1_CLK 51 62#define HI3559AV100_I2C2_CLK 52 63#define HI3559AV100_I2C3_CLK 53 64#define HI3559AV100_I2C4_CLK 54 65#define HI3559AV100_I2C5_CLK 55 66#define HI3559AV100_I2C6_CLK 56 67#define HI3559AV100_I2C7_CLK 57 68#define HI3559AV100_I2C8_CLK 58 69#define HI3559AV100_I2C9_CLK 59 70#define HI3559AV100_I2C10_CLK 60 71#define HI3559AV100_I2C11_CLK 61 72 73#define HI3559AV100_SPI0_CLK 62 74#define HI3559AV100_SPI1_CLK 63 75#define HI3559AV100_SPI2_CLK 64 76#define HI3559AV100_SPI3_CLK 65 77#define HI3559AV100_SPI4_CLK 66 78#define HI3559AV100_SPI5_CLK 67 79#define HI3559AV100_SPI6_CLK 68 80 81#define HI3559AV100_EDMAC_CLK 69 82#define HI3559AV100_EDMAC_AXICLK 70 83#define HI3559AV100_EDMAC1_CLK 71 84#define HI3559AV100_EDMAC1_AXICLK 72 85#define HI3559AV100_VDMAC_CLK 73 86 87/* mux clocks */ 88#define HI3559AV100_FMC_MUX 80 89#define HI3559AV100_SYSAPB_MUX 81 90#define HI3559AV100_UART_MUX 82 91#define HI3559AV100_SYSBUS_MUX 83 92#define HI3559AV100_A73_MUX 84 93#define HI3559AV100_MMC0_MUX 85 94#define HI3559AV100_MMC1_MUX 86 95#define HI3559AV100_MMC2_MUX 87 96#define HI3559AV100_MMC3_MUX 88 97 98/* gate clocks */ 99#define HI3559AV100_FMC_CLK 90 100#define HI3559AV100_UART0_CLK 91 101#define HI3559AV100_UART1_CLK 92 102#define HI3559AV100_UART2_CLK 93 103#define HI3559AV100_UART3_CLK 94 104#define HI3559AV100_UART4_CLK 95 105#define HI3559AV100_MMC0_CLK 96 106#define HI3559AV100_MMC1_CLK 97 107#define HI3559AV100_MMC2_CLK 98 108#define HI3559AV100_MMC3_CLK 99 109 110#define HI3559AV100_ETH_CLK 100 111#define HI3559AV100_ETH_MACIF_CLK 101 112#define HI3559AV100_ETH1_CLK 102 113#define HI3559AV100_ETH1_MACIF_CLK 103 114 115/* complex */ 116#define HI3559AV100_MAC0_CLK 110 117#define HI3559AV100_MAC1_CLK 111 118#define HI3559AV100_SATA_CLK 112 119#define HI3559AV100_USB_CLK 113 120#define HI3559AV100_USB1_CLK 114 121 122/* pll clocks */ 123#define HI3559AV100_APLL_CLK 250 124#define HI3559AV100_GPLL_CLK 251 125 126#define HI3559AV100_CRG_NR_CLKS 256 127 128#define HI3559AV100_SHUB_SOURCE_SOC_24M 0 129#define HI3559AV100_SHUB_SOURCE_SOC_200M 1 130#define HI3559AV100_SHUB_SOURCE_SOC_300M 2 131#define HI3559AV100_SHUB_SOURCE_PLL 3 132#define HI3559AV100_SHUB_SOURCE_CLK 4 133 134#define HI3559AV100_SHUB_I2C0_CLK 10 135#define HI3559AV100_SHUB_I2C1_CLK 11 136#define HI3559AV100_SHUB_I2C2_CLK 12 137#define HI3559AV100_SHUB_I2C3_CLK 13 138#define HI3559AV100_SHUB_I2C4_CLK 14 139#define HI3559AV100_SHUB_I2C5_CLK 15 140#define HI3559AV100_SHUB_I2C6_CLK 16 141#define HI3559AV100_SHUB_I2C7_CLK 17 142 143#define HI3559AV100_SHUB_SPI_SOURCE_CLK 20 144#define HI3559AV100_SHUB_SPI4_SOURCE_CLK 21 145#define HI3559AV100_SHUB_SPI0_CLK 22 146#define HI3559AV100_SHUB_SPI1_CLK 23 147#define HI3559AV100_SHUB_SPI2_CLK 24 148#define HI3559AV100_SHUB_SPI3_CLK 25 149#define HI3559AV100_SHUB_SPI4_CLK 26 150 151#define HI3559AV100_SHUB_UART_CLK_32K 30 152#define HI3559AV100_SHUB_UART_SOURCE_CLK 31 153#define HI3559AV100_SHUB_UART_DIV_CLK 32 154#define HI3559AV100_SHUB_UART0_CLK 33 155#define HI3559AV100_SHUB_UART1_CLK 34 156#define HI3559AV100_SHUB_UART2_CLK 35 157#define HI3559AV100_SHUB_UART3_CLK 36 158#define HI3559AV100_SHUB_UART4_CLK 37 159#define HI3559AV100_SHUB_UART5_CLK 38 160#define HI3559AV100_SHUB_UART6_CLK 39 161 162#define HI3559AV100_SHUB_EDMAC_CLK 40 163 164#define HI3559AV100_SHUB_NR_CLKS 50 165 166#endif /* __DTS_HI3559AV100_CLOCK_H */ 167 168