1 1.1 jmcneill /* $NetBSD: hi3670-clock.h,v 1.1.1.1 2019/01/22 14:57:01 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Device Tree binding constants for HiSilicon Hi3670 SoC 6 1.1 jmcneill * 7 1.1 jmcneill * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. 8 1.1 jmcneill * Copyright (c) 2018 Linaro Ltd. 9 1.1 jmcneill */ 10 1.1 jmcneill 11 1.1 jmcneill #ifndef __DT_BINDINGS_CLOCK_HI3670_H 12 1.1 jmcneill #define __DT_BINDINGS_CLOCK_HI3670_H 13 1.1 jmcneill 14 1.1 jmcneill /* clk in stub clock */ 15 1.1 jmcneill #define HI3670_CLK_STUB_CLUSTER0 0 16 1.1 jmcneill #define HI3670_CLK_STUB_CLUSTER1 1 17 1.1 jmcneill #define HI3670_CLK_STUB_GPU 2 18 1.1 jmcneill #define HI3670_CLK_STUB_DDR 3 19 1.1 jmcneill #define HI3670_CLK_STUB_DDR_VOTE 4 20 1.1 jmcneill #define HI3670_CLK_STUB_DDR_LIMIT 5 21 1.1 jmcneill #define HI3670_CLK_STUB_NUM 6 22 1.1 jmcneill 23 1.1 jmcneill /* clk in crg clock */ 24 1.1 jmcneill #define HI3670_CLKIN_SYS 0 25 1.1 jmcneill #define HI3670_CLKIN_REF 1 26 1.1 jmcneill #define HI3670_CLK_FLL_SRC 2 27 1.1 jmcneill #define HI3670_CLK_PPLL0 3 28 1.1 jmcneill #define HI3670_CLK_PPLL1 4 29 1.1 jmcneill #define HI3670_CLK_PPLL2 5 30 1.1 jmcneill #define HI3670_CLK_PPLL3 6 31 1.1 jmcneill #define HI3670_CLK_PPLL4 7 32 1.1 jmcneill #define HI3670_CLK_PPLL6 8 33 1.1 jmcneill #define HI3670_CLK_PPLL7 9 34 1.1 jmcneill #define HI3670_CLK_PPLL_PCIE 10 35 1.1 jmcneill #define HI3670_CLK_PCIEPLL_REV 11 36 1.1 jmcneill #define HI3670_CLK_SCPLL 12 37 1.1 jmcneill #define HI3670_PCLK 13 38 1.1 jmcneill #define HI3670_CLK_UART0_DBG 14 39 1.1 jmcneill #define HI3670_CLK_UART6 15 40 1.1 jmcneill #define HI3670_OSC32K 16 41 1.1 jmcneill #define HI3670_OSC19M 17 42 1.1 jmcneill #define HI3670_CLK_480M 18 43 1.1 jmcneill #define HI3670_CLK_INVALID 19 44 1.1 jmcneill #define HI3670_CLK_DIV_SYSBUS 20 45 1.1 jmcneill #define HI3670_CLK_FACTOR_MMC 21 46 1.1 jmcneill #define HI3670_CLK_SD_SYS 22 47 1.1 jmcneill #define HI3670_CLK_SDIO_SYS 23 48 1.1 jmcneill #define HI3670_CLK_DIV_A53HPM 24 49 1.1 jmcneill #define HI3670_CLK_DIV_320M 25 50 1.1 jmcneill #define HI3670_PCLK_GATE_UART0 26 51 1.1 jmcneill #define HI3670_CLK_FACTOR_UART0 27 52 1.1 jmcneill #define HI3670_CLK_FACTOR_USB3PHY_PLL 28 53 1.1 jmcneill #define HI3670_CLK_GATE_ABB_USB 29 54 1.1 jmcneill #define HI3670_CLK_GATE_UFSPHY_REF 30 55 1.1 jmcneill #define HI3670_ICS_VOLT_HIGH 31 56 1.1 jmcneill #define HI3670_ICS_VOLT_MIDDLE 32 57 1.1 jmcneill #define HI3670_VENC_VOLT_HOLD 33 58 1.1 jmcneill #define HI3670_VDEC_VOLT_HOLD 34 59 1.1 jmcneill #define HI3670_EDC_VOLT_HOLD 35 60 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_FAC 36 61 1.1 jmcneill #define HI3670_CLK_FACTOR_RXDPHY 37 62 1.1 jmcneill #define HI3670_AUTODIV_SYSBUS 38 63 1.1 jmcneill #define HI3670_AUTODIV_EMMC0BUS 39 64 1.1 jmcneill #define HI3670_PCLK_ANDGT_MMC1_PCIE 40 65 1.1 jmcneill #define HI3670_CLK_GATE_VCODECBUS_GT 41 66 1.1 jmcneill #define HI3670_CLK_ANDGT_SD 42 67 1.1 jmcneill #define HI3670_CLK_SD_SYS_GT 43 68 1.1 jmcneill #define HI3670_CLK_ANDGT_SDIO 44 69 1.1 jmcneill #define HI3670_CLK_SDIO_SYS_GT 45 70 1.1 jmcneill #define HI3670_CLK_A53HPM_ANDGT 46 71 1.1 jmcneill #define HI3670_CLK_320M_PLL_GT 47 72 1.1 jmcneill #define HI3670_CLK_ANDGT_UARTH 48 73 1.1 jmcneill #define HI3670_CLK_ANDGT_UARTL 49 74 1.1 jmcneill #define HI3670_CLK_ANDGT_UART0 50 75 1.1 jmcneill #define HI3670_CLK_ANDGT_SPI 51 76 1.1 jmcneill #define HI3670_CLK_ANDGT_PCIEAXI 52 77 1.1 jmcneill #define HI3670_CLK_DIV_AO_ASP_GT 53 78 1.1 jmcneill #define HI3670_CLK_GATE_CSI_TRANS 54 79 1.1 jmcneill #define HI3670_CLK_GATE_DSI_TRANS 55 80 1.1 jmcneill #define HI3670_CLK_ANDGT_PTP 56 81 1.1 jmcneill #define HI3670_CLK_ANDGT_OUT0 57 82 1.1 jmcneill #define HI3670_CLK_ANDGT_OUT1 58 83 1.1 jmcneill #define HI3670_CLKGT_DP_AUDIO_PLL_AO 59 84 1.1 jmcneill #define HI3670_CLK_ANDGT_VDEC 60 85 1.1 jmcneill #define HI3670_CLK_ANDGT_VENC 61 86 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_ANGT 62 87 1.1 jmcneill #define HI3670_CLK_ANDGT_RXDPHY 63 88 1.1 jmcneill #define HI3670_CLK_ANDGT_ICS 64 89 1.1 jmcneill #define HI3670_AUTODIV_DMABUS 65 90 1.1 jmcneill #define HI3670_CLK_MUX_SYSBUS 66 91 1.1 jmcneill #define HI3670_CLK_MUX_VCODECBUS 67 92 1.1 jmcneill #define HI3670_CLK_MUX_SD_SYS 68 93 1.1 jmcneill #define HI3670_CLK_MUX_SD_PLL 69 94 1.1 jmcneill #define HI3670_CLK_MUX_SDIO_SYS 70 95 1.1 jmcneill #define HI3670_CLK_MUX_SDIO_PLL 71 96 1.1 jmcneill #define HI3670_CLK_MUX_A53HPM 72 97 1.1 jmcneill #define HI3670_CLK_MUX_320M 73 98 1.1 jmcneill #define HI3670_CLK_MUX_UARTH 74 99 1.1 jmcneill #define HI3670_CLK_MUX_UARTL 75 100 1.1 jmcneill #define HI3670_CLK_MUX_UART0 76 101 1.1 jmcneill #define HI3670_CLK_MUX_I2C 77 102 1.1 jmcneill #define HI3670_CLK_MUX_SPI 78 103 1.1 jmcneill #define HI3670_CLK_MUX_PCIEAXI 79 104 1.1 jmcneill #define HI3670_CLK_MUX_AO_ASP 80 105 1.1 jmcneill #define HI3670_CLK_MUX_VDEC 81 106 1.1 jmcneill #define HI3670_CLK_MUX_VENC 82 107 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_MUX0 83 108 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_MUX1 84 109 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_MUX2 85 110 1.1 jmcneill #define HI3670_CLK_MUX_RXDPHY_CFG 86 111 1.1 jmcneill #define HI3670_CLK_MUX_ICS 87 112 1.1 jmcneill #define HI3670_CLK_DIV_CFGBUS 88 113 1.1 jmcneill #define HI3670_CLK_DIV_MMC0BUS 89 114 1.1 jmcneill #define HI3670_CLK_DIV_MMC1BUS 90 115 1.1 jmcneill #define HI3670_PCLK_DIV_MMC1_PCIE 91 116 1.1 jmcneill #define HI3670_CLK_DIV_VCODECBUS 92 117 1.1 jmcneill #define HI3670_CLK_DIV_SD 93 118 1.1 jmcneill #define HI3670_CLK_DIV_SDIO 94 119 1.1 jmcneill #define HI3670_CLK_DIV_UARTH 95 120 1.1 jmcneill #define HI3670_CLK_DIV_UARTL 96 121 1.1 jmcneill #define HI3670_CLK_DIV_UART0 97 122 1.1 jmcneill #define HI3670_CLK_DIV_I2C 98 123 1.1 jmcneill #define HI3670_CLK_DIV_SPI 99 124 1.1 jmcneill #define HI3670_CLK_DIV_PCIEAXI 100 125 1.1 jmcneill #define HI3670_CLK_DIV_AO_ASP 101 126 1.1 jmcneill #define HI3670_CLK_DIV_CSI_TRANS 102 127 1.1 jmcneill #define HI3670_CLK_DIV_DSI_TRANS 103 128 1.1 jmcneill #define HI3670_CLK_DIV_PTP 104 129 1.1 jmcneill #define HI3670_CLK_DIV_CLKOUT0_PLL 105 130 1.1 jmcneill #define HI3670_CLK_DIV_CLKOUT1_PLL 106 131 1.1 jmcneill #define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107 132 1.1 jmcneill #define HI3670_CLK_DIV_VDEC 108 133 1.1 jmcneill #define HI3670_CLK_DIV_VENC 109 134 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_DIV0 110 135 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_DIV1 111 136 1.1 jmcneill #define HI3670_CLK_ISP_SNCLK_DIV2 112 137 1.1 jmcneill #define HI3670_CLK_DIV_ICS 113 138 1.1 jmcneill #define HI3670_PPLL1_EN_ACPU 114 139 1.1 jmcneill #define HI3670_PPLL2_EN_ACPU 115 140 1.1 jmcneill #define HI3670_PPLL3_EN_ACPU 116 141 1.1 jmcneill #define HI3670_PPLL1_GT_CPU 117 142 1.1 jmcneill #define HI3670_PPLL2_GT_CPU 118 143 1.1 jmcneill #define HI3670_PPLL3_GT_CPU 119 144 1.1 jmcneill #define HI3670_CLK_GATE_PPLL2_MEDIA 120 145 1.1 jmcneill #define HI3670_CLK_GATE_PPLL3_MEDIA 121 146 1.1 jmcneill #define HI3670_CLK_GATE_PPLL4_MEDIA 122 147 1.1 jmcneill #define HI3670_CLK_GATE_PPLL6_MEDIA 123 148 1.1 jmcneill #define HI3670_CLK_GATE_PPLL7_MEDIA 124 149 1.1 jmcneill #define HI3670_PCLK_GPIO0 125 150 1.1 jmcneill #define HI3670_PCLK_GPIO1 126 151 1.1 jmcneill #define HI3670_PCLK_GPIO2 127 152 1.1 jmcneill #define HI3670_PCLK_GPIO3 128 153 1.1 jmcneill #define HI3670_PCLK_GPIO4 129 154 1.1 jmcneill #define HI3670_PCLK_GPIO5 130 155 1.1 jmcneill #define HI3670_PCLK_GPIO6 131 156 1.1 jmcneill #define HI3670_PCLK_GPIO7 132 157 1.1 jmcneill #define HI3670_PCLK_GPIO8 133 158 1.1 jmcneill #define HI3670_PCLK_GPIO9 134 159 1.1 jmcneill #define HI3670_PCLK_GPIO10 135 160 1.1 jmcneill #define HI3670_PCLK_GPIO11 136 161 1.1 jmcneill #define HI3670_PCLK_GPIO12 137 162 1.1 jmcneill #define HI3670_PCLK_GPIO13 138 163 1.1 jmcneill #define HI3670_PCLK_GPIO14 139 164 1.1 jmcneill #define HI3670_PCLK_GPIO15 140 165 1.1 jmcneill #define HI3670_PCLK_GPIO16 141 166 1.1 jmcneill #define HI3670_PCLK_GPIO17 142 167 1.1 jmcneill #define HI3670_PCLK_GPIO20 143 168 1.1 jmcneill #define HI3670_PCLK_GPIO21 144 169 1.1 jmcneill #define HI3670_PCLK_GATE_DSI0 145 170 1.1 jmcneill #define HI3670_PCLK_GATE_DSI1 146 171 1.1 jmcneill #define HI3670_HCLK_GATE_USB3OTG 147 172 1.1 jmcneill #define HI3670_ACLK_GATE_USB3DVFS 148 173 1.1 jmcneill #define HI3670_HCLK_GATE_SDIO 149 174 1.1 jmcneill #define HI3670_PCLK_GATE_PCIE_SYS 150 175 1.1 jmcneill #define HI3670_PCLK_GATE_PCIE_PHY 151 176 1.1 jmcneill #define HI3670_PCLK_GATE_MMC1_PCIE 152 177 1.1 jmcneill #define HI3670_PCLK_GATE_MMC0_IOC 153 178 1.1 jmcneill #define HI3670_PCLK_GATE_MMC1_IOC 154 179 1.1 jmcneill #define HI3670_CLK_GATE_DMAC 155 180 1.1 jmcneill #define HI3670_CLK_GATE_VCODECBUS2DDR 156 181 1.1 jmcneill #define HI3670_CLK_CCI400_BYPASS 157 182 1.1 jmcneill #define HI3670_CLK_GATE_CCI400 158 183 1.1 jmcneill #define HI3670_CLK_GATE_SD 159 184 1.1 jmcneill #define HI3670_HCLK_GATE_SD 160 185 1.1 jmcneill #define HI3670_CLK_GATE_SDIO 161 186 1.1 jmcneill #define HI3670_CLK_GATE_A57HPM 162 187 1.1 jmcneill #define HI3670_CLK_GATE_A53HPM 163 188 1.1 jmcneill #define HI3670_CLK_GATE_PA_A53 164 189 1.1 jmcneill #define HI3670_CLK_GATE_PA_A57 165 190 1.1 jmcneill #define HI3670_CLK_GATE_PA_G3D 166 191 1.1 jmcneill #define HI3670_CLK_GATE_GPUHPM 167 192 1.1 jmcneill #define HI3670_CLK_GATE_PERIHPM 168 193 1.1 jmcneill #define HI3670_CLK_GATE_AOHPM 169 194 1.1 jmcneill #define HI3670_CLK_GATE_UART1 170 195 1.1 jmcneill #define HI3670_CLK_GATE_UART4 171 196 1.1 jmcneill #define HI3670_PCLK_GATE_UART1 172 197 1.1 jmcneill #define HI3670_PCLK_GATE_UART4 173 198 1.1 jmcneill #define HI3670_CLK_GATE_UART2 174 199 1.1 jmcneill #define HI3670_CLK_GATE_UART5 175 200 1.1 jmcneill #define HI3670_PCLK_GATE_UART2 176 201 1.1 jmcneill #define HI3670_PCLK_GATE_UART5 177 202 1.1 jmcneill #define HI3670_CLK_GATE_UART0 178 203 1.1 jmcneill #define HI3670_CLK_GATE_I2C3 179 204 1.1 jmcneill #define HI3670_CLK_GATE_I2C4 180 205 1.1 jmcneill #define HI3670_CLK_GATE_I2C7 181 206 1.1 jmcneill #define HI3670_PCLK_GATE_I2C3 182 207 1.1 jmcneill #define HI3670_PCLK_GATE_I2C4 183 208 1.1 jmcneill #define HI3670_PCLK_GATE_I2C7 184 209 1.1 jmcneill #define HI3670_CLK_GATE_SPI1 185 210 1.1 jmcneill #define HI3670_CLK_GATE_SPI4 186 211 1.1 jmcneill #define HI3670_PCLK_GATE_SPI1 187 212 1.1 jmcneill #define HI3670_PCLK_GATE_SPI4 188 213 1.1 jmcneill #define HI3670_CLK_GATE_USB3OTG_REF 189 214 1.1 jmcneill #define HI3670_CLK_GATE_USB2PHY_REF 190 215 1.1 jmcneill #define HI3670_CLK_GATE_PCIEAUX 191 216 1.1 jmcneill #define HI3670_ACLK_GATE_PCIE 192 217 1.1 jmcneill #define HI3670_CLK_GATE_MMC1_PCIEAXI 193 218 1.1 jmcneill #define HI3670_CLK_GATE_PCIEPHY_REF 194 219 1.1 jmcneill #define HI3670_CLK_GATE_PCIE_DEBOUNCE 195 220 1.1 jmcneill #define HI3670_CLK_GATE_PCIEIO 196 221 1.1 jmcneill #define HI3670_CLK_GATE_PCIE_HP 197 222 1.1 jmcneill #define HI3670_CLK_GATE_AO_ASP 198 223 1.1 jmcneill #define HI3670_PCLK_GATE_PCTRL 199 224 1.1 jmcneill #define HI3670_CLK_CSI_TRANS_GT 200 225 1.1 jmcneill #define HI3670_CLK_DSI_TRANS_GT 201 226 1.1 jmcneill #define HI3670_CLK_GATE_PWM 202 227 1.1 jmcneill #define HI3670_ABB_AUDIO_EN0 203 228 1.1 jmcneill #define HI3670_ABB_AUDIO_EN1 204 229 1.1 jmcneill #define HI3670_ABB_AUDIO_GT_EN0 205 230 1.1 jmcneill #define HI3670_ABB_AUDIO_GT_EN1 206 231 1.1 jmcneill #define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207 232 1.1 jmcneill #define HI3670_PERI_VOLT_HOLD 208 233 1.1 jmcneill #define HI3670_PERI_VOLT_MIDDLE 209 234 1.1 jmcneill #define HI3670_CLK_GATE_ISP_SNCLK0 210 235 1.1 jmcneill #define HI3670_CLK_GATE_ISP_SNCLK1 211 236 1.1 jmcneill #define HI3670_CLK_GATE_ISP_SNCLK2 212 237 1.1 jmcneill #define HI3670_CLK_GATE_RXDPHY0_CFG 213 238 1.1 jmcneill #define HI3670_CLK_GATE_RXDPHY1_CFG 214 239 1.1 jmcneill #define HI3670_CLK_GATE_RXDPHY2_CFG 215 240 1.1 jmcneill #define HI3670_CLK_GATE_TXDPHY0_CFG 216 241 1.1 jmcneill #define HI3670_CLK_GATE_TXDPHY0_REF 217 242 1.1 jmcneill #define HI3670_CLK_GATE_TXDPHY1_CFG 218 243 1.1 jmcneill #define HI3670_CLK_GATE_TXDPHY1_REF 219 244 1.1 jmcneill #define HI3670_CLK_GATE_MEDIA_TCXO 220 245 1.1 jmcneill 246 1.1 jmcneill /* clk in sctrl */ 247 1.1 jmcneill #define HI3670_CLK_ANDGT_IOPERI 0 248 1.1 jmcneill #define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1 249 1.1 jmcneill #define HI3670_CLK_ANGT_ASP_SUBSYS 2 250 1.1 jmcneill #define HI3670_CLK_MUX_UFS_SUBSYS 3 251 1.1 jmcneill #define HI3670_CLK_MUX_CLKOUT0 4 252 1.1 jmcneill #define HI3670_CLK_MUX_CLKOUT1 5 253 1.1 jmcneill #define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6 254 1.1 jmcneill #define HI3670_CLK_MUX_ASP_PLL 7 255 1.1 jmcneill #define HI3670_CLK_DIV_AOBUS 8 256 1.1 jmcneill #define HI3670_CLK_DIV_UFS_SUBSYS 9 257 1.1 jmcneill #define HI3670_CLK_DIV_IOPERI 10 258 1.1 jmcneill #define HI3670_CLK_DIV_CLKOUT0_TCXO 11 259 1.1 jmcneill #define HI3670_CLK_DIV_CLKOUT1_TCXO 12 260 1.1 jmcneill #define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13 261 1.1 jmcneill #define HI3670_CLK_DIV_ASP_SUBSYS 14 262 1.1 jmcneill #define HI3670_PPLL0_EN_ACPU 15 263 1.1 jmcneill #define HI3670_PPLL0_GT_CPU 16 264 1.1 jmcneill #define HI3670_CLK_GATE_PPLL0_MEDIA 17 265 1.1 jmcneill #define HI3670_PCLK_GPIO18 18 266 1.1 jmcneill #define HI3670_PCLK_GPIO19 19 267 1.1 jmcneill #define HI3670_CLK_GATE_SPI 20 268 1.1 jmcneill #define HI3670_PCLK_GATE_SPI 21 269 1.1 jmcneill #define HI3670_CLK_GATE_UFS_SUBSYS 22 270 1.1 jmcneill #define HI3670_CLK_GATE_UFSIO_REF 23 271 1.1 jmcneill #define HI3670_PCLK_AO_GPIO0 24 272 1.1 jmcneill #define HI3670_PCLK_AO_GPIO1 25 273 1.1 jmcneill #define HI3670_PCLK_AO_GPIO2 26 274 1.1 jmcneill #define HI3670_PCLK_AO_GPIO3 27 275 1.1 jmcneill #define HI3670_PCLK_AO_GPIO4 28 276 1.1 jmcneill #define HI3670_PCLK_AO_GPIO5 29 277 1.1 jmcneill #define HI3670_PCLK_AO_GPIO6 30 278 1.1 jmcneill #define HI3670_CLK_GATE_OUT0 31 279 1.1 jmcneill #define HI3670_CLK_GATE_OUT1 32 280 1.1 jmcneill #define HI3670_PCLK_GATE_SYSCNT 33 281 1.1 jmcneill #define HI3670_CLK_GATE_SYSCNT 34 282 1.1 jmcneill #define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35 283 1.1 jmcneill #define HI3670_CLK_GATE_ASP_SUBSYS 36 284 1.1 jmcneill #define HI3670_CLK_GATE_ASP_TCXO 37 285 1.1 jmcneill #define HI3670_CLK_GATE_DP_AUDIO_PLL 38 286 1.1 jmcneill 287 1.1 jmcneill /* clk in pmuctrl */ 288 1.1 jmcneill #define HI3670_GATE_ABB_192 0 289 1.1 jmcneill 290 1.1 jmcneill /* clk in pctrl */ 291 1.1 jmcneill #define HI3670_GATE_UFS_TCXO_EN 0 292 1.1 jmcneill #define HI3670_GATE_USB_TCXO_EN 1 293 1.1 jmcneill 294 1.1 jmcneill /* clk in iomcu */ 295 1.1 jmcneill #define HI3670_CLK_GATE_I2C0 0 296 1.1 jmcneill #define HI3670_CLK_GATE_I2C1 1 297 1.1 jmcneill #define HI3670_CLK_GATE_I2C2 2 298 1.1 jmcneill #define HI3670_CLK_GATE_SPI0 3 299 1.1 jmcneill #define HI3670_CLK_GATE_SPI2 4 300 1.1 jmcneill #define HI3670_CLK_GATE_UART3 5 301 1.1 jmcneill #define HI3670_CLK_I2C0_GATE_IOMCU 6 302 1.1 jmcneill #define HI3670_CLK_I2C1_GATE_IOMCU 7 303 1.1 jmcneill #define HI3670_CLK_I2C2_GATE_IOMCU 8 304 1.1 jmcneill #define HI3670_CLK_SPI0_GATE_IOMCU 9 305 1.1 jmcneill #define HI3670_CLK_SPI2_GATE_IOMCU 10 306 1.1 jmcneill #define HI3670_CLK_UART3_GATE_IOMCU 11 307 1.1 jmcneill #define HI3670_CLK_GATE_PERI0_IOMCU 12 308 1.1 jmcneill 309 1.1 jmcneill /* clk in media1 */ 310 1.1 jmcneill #define HI3670_CLK_GATE_VIVOBUS_ANDGT 0 311 1.1 jmcneill #define HI3670_CLK_ANDGT_EDC0 1 312 1.1 jmcneill #define HI3670_CLK_ANDGT_LDI0 2 313 1.1 jmcneill #define HI3670_CLK_ANDGT_LDI1 3 314 1.1 jmcneill #define HI3670_CLK_MMBUF_PLL_ANDGT 4 315 1.1 jmcneill #define HI3670_PCLK_MMBUF_ANDGT 5 316 1.1 jmcneill #define HI3670_CLK_MUX_VIVOBUS 6 317 1.1 jmcneill #define HI3670_CLK_MUX_EDC0 7 318 1.1 jmcneill #define HI3670_CLK_MUX_LDI0 8 319 1.1 jmcneill #define HI3670_CLK_MUX_LDI1 9 320 1.1 jmcneill #define HI3670_CLK_SW_MMBUF 10 321 1.1 jmcneill #define HI3670_CLK_DIV_VIVOBUS 11 322 1.1 jmcneill #define HI3670_CLK_DIV_EDC0 12 323 1.1 jmcneill #define HI3670_CLK_DIV_LDI0 13 324 1.1 jmcneill #define HI3670_CLK_DIV_LDI1 14 325 1.1 jmcneill #define HI3670_ACLK_DIV_MMBUF 15 326 1.1 jmcneill #define HI3670_PCLK_DIV_MMBUF 16 327 1.1 jmcneill #define HI3670_ACLK_GATE_NOC_DSS 17 328 1.1 jmcneill #define HI3670_PCLK_GATE_NOC_DSS_CFG 18 329 1.1 jmcneill #define HI3670_PCLK_GATE_MMBUF_CFG 19 330 1.1 jmcneill #define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20 331 1.1 jmcneill #define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21 332 1.1 jmcneill #define HI3670_PCLK_GATE_DSS 22 333 1.1 jmcneill #define HI3670_ACLK_GATE_DSS 23 334 1.1 jmcneill #define HI3670_CLK_GATE_VIVOBUSFREQ 24 335 1.1 jmcneill #define HI3670_CLK_GATE_EDC0 25 336 1.1 jmcneill #define HI3670_CLK_GATE_LDI0 26 337 1.1 jmcneill #define HI3670_CLK_GATE_LDI1FREQ 27 338 1.1 jmcneill #define HI3670_CLK_GATE_BRG 28 339 1.1 jmcneill #define HI3670_ACLK_GATE_ASC 29 340 1.1 jmcneill #define HI3670_CLK_GATE_DSS_AXI_MM 30 341 1.1 jmcneill #define HI3670_CLK_GATE_MMBUF 31 342 1.1 jmcneill #define HI3670_PCLK_GATE_MMBUF 32 343 1.1 jmcneill #define HI3670_CLK_GATE_ATDIV_VIVO 33 344 1.1 jmcneill 345 1.1 jmcneill /* clk in media2 */ 346 1.1 jmcneill #define HI3670_CLK_GATE_VDECFREQ 0 347 1.1 jmcneill #define HI3670_CLK_GATE_VENCFREQ 1 348 1.1 jmcneill #define HI3670_CLK_GATE_ICSFREQ 2 349 1.1 jmcneill 350 1.1 jmcneill #endif /* __DT_BINDINGS_CLOCK_HI3670_H */ 351