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      1      1.1  jmcneill /*	$NetBSD: imx21-clock.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $	*/
      2      1.1  jmcneill 
      3  1.1.1.2     skrll /* SPDX-License-Identifier: GPL-2.0-only */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * Copyright (C) 2014 Alexander Shiyan <shc_work (at) mail.ru>
      6      1.1  jmcneill  */
      7      1.1  jmcneill 
      8      1.1  jmcneill #ifndef __DT_BINDINGS_CLOCK_IMX21_H
      9      1.1  jmcneill #define __DT_BINDINGS_CLOCK_IMX21_H
     10      1.1  jmcneill 
     11      1.1  jmcneill #define IMX21_CLK_DUMMY			0
     12      1.1  jmcneill #define IMX21_CLK_CKIL			1
     13      1.1  jmcneill #define IMX21_CLK_CKIH			2
     14      1.1  jmcneill #define IMX21_CLK_FPM			3
     15      1.1  jmcneill #define IMX21_CLK_CKIH_DIV1P5		4
     16      1.1  jmcneill #define IMX21_CLK_MPLL_GATE		5
     17      1.1  jmcneill #define IMX21_CLK_SPLL_GATE		6
     18      1.1  jmcneill #define IMX21_CLK_FPM_GATE		7
     19      1.1  jmcneill #define IMX21_CLK_CKIH_GATE		8
     20      1.1  jmcneill #define IMX21_CLK_MPLL_OSC_SEL		9
     21      1.1  jmcneill #define IMX21_CLK_IPG			10
     22      1.1  jmcneill #define IMX21_CLK_HCLK			11
     23      1.1  jmcneill #define IMX21_CLK_MPLL_SEL		12
     24      1.1  jmcneill #define IMX21_CLK_SPLL_SEL		13
     25      1.1  jmcneill #define IMX21_CLK_SSI1_SEL		14
     26      1.1  jmcneill #define IMX21_CLK_SSI2_SEL		15
     27      1.1  jmcneill #define IMX21_CLK_USB_DIV		16
     28      1.1  jmcneill #define IMX21_CLK_FCLK			17
     29      1.1  jmcneill #define IMX21_CLK_MPLL			18
     30      1.1  jmcneill #define IMX21_CLK_SPLL			19
     31      1.1  jmcneill #define IMX21_CLK_NFC_DIV		20
     32      1.1  jmcneill #define IMX21_CLK_SSI1_DIV		21
     33      1.1  jmcneill #define IMX21_CLK_SSI2_DIV		22
     34      1.1  jmcneill #define IMX21_CLK_PER1			23
     35      1.1  jmcneill #define IMX21_CLK_PER2			24
     36      1.1  jmcneill #define IMX21_CLK_PER3			25
     37      1.1  jmcneill #define IMX21_CLK_PER4			26
     38      1.1  jmcneill #define IMX21_CLK_UART1_IPG_GATE	27
     39      1.1  jmcneill #define IMX21_CLK_UART2_IPG_GATE	28
     40      1.1  jmcneill #define IMX21_CLK_UART3_IPG_GATE	29
     41      1.1  jmcneill #define IMX21_CLK_UART4_IPG_GATE	30
     42      1.1  jmcneill #define IMX21_CLK_CSPI1_IPG_GATE	31
     43      1.1  jmcneill #define IMX21_CLK_CSPI2_IPG_GATE	32
     44      1.1  jmcneill #define IMX21_CLK_SSI1_GATE		33
     45      1.1  jmcneill #define IMX21_CLK_SSI2_GATE		34
     46      1.1  jmcneill #define IMX21_CLK_SDHC1_IPG_GATE	35
     47      1.1  jmcneill #define IMX21_CLK_SDHC2_IPG_GATE	36
     48      1.1  jmcneill #define IMX21_CLK_GPIO_GATE		37
     49      1.1  jmcneill #define IMX21_CLK_I2C_GATE		38
     50      1.1  jmcneill #define IMX21_CLK_DMA_GATE		39
     51      1.1  jmcneill #define IMX21_CLK_USB_GATE		40
     52      1.1  jmcneill #define IMX21_CLK_EMMA_GATE		41
     53      1.1  jmcneill #define IMX21_CLK_SSI2_BAUD_GATE	42
     54      1.1  jmcneill #define IMX21_CLK_SSI1_BAUD_GATE	43
     55      1.1  jmcneill #define IMX21_CLK_LCDC_IPG_GATE		44
     56      1.1  jmcneill #define IMX21_CLK_NFC_GATE		45
     57      1.1  jmcneill #define IMX21_CLK_LCDC_HCLK_GATE	46
     58      1.1  jmcneill #define IMX21_CLK_PER4_GATE		47
     59      1.1  jmcneill #define IMX21_CLK_BMI_GATE		48
     60      1.1  jmcneill #define IMX21_CLK_USB_HCLK_GATE		49
     61      1.1  jmcneill #define IMX21_CLK_SLCDC_GATE		50
     62      1.1  jmcneill #define IMX21_CLK_SLCDC_HCLK_GATE	51
     63      1.1  jmcneill #define IMX21_CLK_EMMA_HCLK_GATE	52
     64      1.1  jmcneill #define IMX21_CLK_BROM_GATE		53
     65      1.1  jmcneill #define IMX21_CLK_DMA_HCLK_GATE		54
     66      1.1  jmcneill #define IMX21_CLK_CSI_HCLK_GATE		55
     67      1.1  jmcneill #define IMX21_CLK_CSPI3_IPG_GATE	56
     68      1.1  jmcneill #define IMX21_CLK_WDOG_GATE		57
     69      1.1  jmcneill #define IMX21_CLK_GPT1_IPG_GATE		58
     70      1.1  jmcneill #define IMX21_CLK_GPT2_IPG_GATE		59
     71      1.1  jmcneill #define IMX21_CLK_GPT3_IPG_GATE		60
     72      1.1  jmcneill #define IMX21_CLK_PWM_IPG_GATE		61
     73      1.1  jmcneill #define IMX21_CLK_RTC_GATE		62
     74      1.1  jmcneill #define IMX21_CLK_KPP_GATE		63
     75      1.1  jmcneill #define IMX21_CLK_OWIRE_GATE		64
     76      1.1  jmcneill #define IMX21_CLK_MAX			65
     77      1.1  jmcneill 
     78      1.1  jmcneill #endif
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