1 1.1 jmcneill /* $NetBSD: imx7d-clock.h,v 1.1.1.7 2021/11/07 16:50:00 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1.1.6 skrll /* SPDX-License-Identifier: GPL-2.0-only */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 6 1.1 jmcneill */ 7 1.1 jmcneill 8 1.1 jmcneill #ifndef __DT_BINDINGS_CLOCK_IMX7D_H 9 1.1 jmcneill #define __DT_BINDINGS_CLOCK_IMX7D_H 10 1.1 jmcneill 11 1.1 jmcneill #define IMX7D_OSC_24M_CLK 0 12 1.1 jmcneill #define IMX7D_PLL_ARM_MAIN 1 13 1.1 jmcneill #define IMX7D_PLL_ARM_MAIN_CLK 2 14 1.1 jmcneill #define IMX7D_PLL_ARM_MAIN_SRC 3 15 1.1 jmcneill #define IMX7D_PLL_ARM_MAIN_BYPASS 4 16 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN 5 17 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_CLK 6 18 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_SRC 7 19 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_BYPASS 8 20 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_480M 9 21 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_240M 10 22 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_120M 11 23 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_480M_CLK 12 24 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_240M_CLK 13 25 1.1 jmcneill #define IMX7D_PLL_SYS_MAIN_120M_CLK 14 26 1.1 jmcneill #define IMX7D_PLL_SYS_PFD0_392M_CLK 15 27 1.1 jmcneill #define IMX7D_PLL_SYS_PFD0_196M 16 28 1.1 jmcneill #define IMX7D_PLL_SYS_PFD0_196M_CLK 17 29 1.1 jmcneill #define IMX7D_PLL_SYS_PFD1_332M_CLK 18 30 1.1 jmcneill #define IMX7D_PLL_SYS_PFD1_166M 19 31 1.1 jmcneill #define IMX7D_PLL_SYS_PFD1_166M_CLK 20 32 1.1 jmcneill #define IMX7D_PLL_SYS_PFD2_270M_CLK 21 33 1.1 jmcneill #define IMX7D_PLL_SYS_PFD2_135M 22 34 1.1 jmcneill #define IMX7D_PLL_SYS_PFD2_135M_CLK 23 35 1.1 jmcneill #define IMX7D_PLL_SYS_PFD3_CLK 24 36 1.1 jmcneill #define IMX7D_PLL_SYS_PFD4_CLK 25 37 1.1 jmcneill #define IMX7D_PLL_SYS_PFD5_CLK 26 38 1.1 jmcneill #define IMX7D_PLL_SYS_PFD6_CLK 27 39 1.1 jmcneill #define IMX7D_PLL_SYS_PFD7_CLK 28 40 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN 29 41 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_CLK 30 42 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_SRC 31 43 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_BYPASS 32 44 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_500M 33 45 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_250M 34 46 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_125M 35 47 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_100M 36 48 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_50M 37 49 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_40M 38 50 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_25M 39 51 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_500M_CLK 40 52 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_250M_CLK 41 53 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_125M_CLK 42 54 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 55 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_50M_CLK 44 56 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_40M_CLK 45 57 1.1 jmcneill #define IMX7D_PLL_ENET_MAIN_25M_CLK 46 58 1.1 jmcneill #define IMX7D_PLL_DRAM_MAIN 47 59 1.1 jmcneill #define IMX7D_PLL_DRAM_MAIN_CLK 48 60 1.1 jmcneill #define IMX7D_PLL_DRAM_MAIN_SRC 49 61 1.1 jmcneill #define IMX7D_PLL_DRAM_MAIN_BYPASS 50 62 1.1 jmcneill #define IMX7D_PLL_DRAM_MAIN_533M 51 63 1.1 jmcneill #define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 64 1.1 jmcneill #define IMX7D_PLL_AUDIO_MAIN 53 65 1.1 jmcneill #define IMX7D_PLL_AUDIO_MAIN_CLK 54 66 1.1 jmcneill #define IMX7D_PLL_AUDIO_MAIN_SRC 55 67 1.1 jmcneill #define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 68 1.1 jmcneill #define IMX7D_PLL_VIDEO_MAIN_CLK 57 69 1.1 jmcneill #define IMX7D_PLL_VIDEO_MAIN 58 70 1.1 jmcneill #define IMX7D_PLL_VIDEO_MAIN_SRC 59 71 1.1 jmcneill #define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 72 1.1 jmcneill #define IMX7D_USB_MAIN_480M_CLK 61 73 1.1 jmcneill #define IMX7D_ARM_A7_ROOT_CLK 62 74 1.1 jmcneill #define IMX7D_ARM_A7_ROOT_SRC 63 75 1.1 jmcneill #define IMX7D_ARM_A7_ROOT_CG 64 76 1.1 jmcneill #define IMX7D_ARM_A7_ROOT_DIV 65 77 1.1 jmcneill #define IMX7D_ARM_M4_ROOT_CLK 66 78 1.1 jmcneill #define IMX7D_ARM_M4_ROOT_SRC 67 79 1.1 jmcneill #define IMX7D_ARM_M4_ROOT_CG 68 80 1.1 jmcneill #define IMX7D_ARM_M4_ROOT_DIV 69 81 1.1.1.3 jmcneill #define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ 82 1.1.1.3 jmcneill #define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ 83 1.1.1.3 jmcneill #define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ 84 1.1.1.3 jmcneill #define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ 85 1.1 jmcneill #define IMX7D_MAIN_AXI_ROOT_CLK 74 86 1.1 jmcneill #define IMX7D_MAIN_AXI_ROOT_SRC 75 87 1.1 jmcneill #define IMX7D_MAIN_AXI_ROOT_CG 76 88 1.1 jmcneill #define IMX7D_MAIN_AXI_ROOT_DIV 77 89 1.1 jmcneill #define IMX7D_DISP_AXI_ROOT_CLK 78 90 1.1 jmcneill #define IMX7D_DISP_AXI_ROOT_SRC 79 91 1.1 jmcneill #define IMX7D_DISP_AXI_ROOT_CG 80 92 1.1 jmcneill #define IMX7D_DISP_AXI_ROOT_DIV 81 93 1.1 jmcneill #define IMX7D_ENET_AXI_ROOT_CLK 82 94 1.1 jmcneill #define IMX7D_ENET_AXI_ROOT_SRC 83 95 1.1 jmcneill #define IMX7D_ENET_AXI_ROOT_CG 84 96 1.1 jmcneill #define IMX7D_ENET_AXI_ROOT_DIV 85 97 1.1 jmcneill #define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 98 1.1 jmcneill #define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 99 1.1 jmcneill #define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 100 1.1 jmcneill #define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 101 1.1 jmcneill #define IMX7D_AHB_CHANNEL_ROOT_CLK 90 102 1.1 jmcneill #define IMX7D_AHB_CHANNEL_ROOT_SRC 91 103 1.1 jmcneill #define IMX7D_AHB_CHANNEL_ROOT_CG 92 104 1.1 jmcneill #define IMX7D_AHB_CHANNEL_ROOT_DIV 93 105 1.1 jmcneill #define IMX7D_DRAM_PHYM_ROOT_CLK 94 106 1.1 jmcneill #define IMX7D_DRAM_PHYM_ROOT_SRC 95 107 1.1 jmcneill #define IMX7D_DRAM_PHYM_ROOT_CG 96 108 1.1 jmcneill #define IMX7D_DRAM_PHYM_ROOT_DIV 97 109 1.1 jmcneill #define IMX7D_DRAM_ROOT_CLK 98 110 1.1 jmcneill #define IMX7D_DRAM_ROOT_SRC 99 111 1.1 jmcneill #define IMX7D_DRAM_ROOT_CG 100 112 1.1 jmcneill #define IMX7D_DRAM_ROOT_DIV 101 113 1.1 jmcneill #define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 114 1.1 jmcneill #define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 115 1.1 jmcneill #define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 116 1.1 jmcneill #define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 117 1.1 jmcneill #define IMX7D_DRAM_ALT_ROOT_CLK 106 118 1.1 jmcneill #define IMX7D_DRAM_ALT_ROOT_SRC 107 119 1.1 jmcneill #define IMX7D_DRAM_ALT_ROOT_CG 108 120 1.1 jmcneill #define IMX7D_DRAM_ALT_ROOT_DIV 109 121 1.1 jmcneill #define IMX7D_USB_HSIC_ROOT_CLK 110 122 1.1 jmcneill #define IMX7D_USB_HSIC_ROOT_SRC 111 123 1.1 jmcneill #define IMX7D_USB_HSIC_ROOT_CG 112 124 1.1 jmcneill #define IMX7D_USB_HSIC_ROOT_DIV 113 125 1.1 jmcneill #define IMX7D_PCIE_CTRL_ROOT_CLK 114 126 1.1 jmcneill #define IMX7D_PCIE_CTRL_ROOT_SRC 115 127 1.1 jmcneill #define IMX7D_PCIE_CTRL_ROOT_CG 116 128 1.1 jmcneill #define IMX7D_PCIE_CTRL_ROOT_DIV 117 129 1.1 jmcneill #define IMX7D_PCIE_PHY_ROOT_CLK 118 130 1.1 jmcneill #define IMX7D_PCIE_PHY_ROOT_SRC 119 131 1.1 jmcneill #define IMX7D_PCIE_PHY_ROOT_CG 120 132 1.1 jmcneill #define IMX7D_PCIE_PHY_ROOT_DIV 121 133 1.1 jmcneill #define IMX7D_EPDC_PIXEL_ROOT_CLK 122 134 1.1 jmcneill #define IMX7D_EPDC_PIXEL_ROOT_SRC 123 135 1.1 jmcneill #define IMX7D_EPDC_PIXEL_ROOT_CG 124 136 1.1 jmcneill #define IMX7D_EPDC_PIXEL_ROOT_DIV 125 137 1.1 jmcneill #define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 138 1.1 jmcneill #define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 139 1.1 jmcneill #define IMX7D_LCDIF_PIXEL_ROOT_CG 128 140 1.1 jmcneill #define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 141 1.1 jmcneill #define IMX7D_MIPI_DSI_ROOT_CLK 130 142 1.1 jmcneill #define IMX7D_MIPI_DSI_ROOT_SRC 131 143 1.1 jmcneill #define IMX7D_MIPI_DSI_ROOT_CG 132 144 1.1 jmcneill #define IMX7D_MIPI_DSI_ROOT_DIV 133 145 1.1 jmcneill #define IMX7D_MIPI_CSI_ROOT_CLK 134 146 1.1 jmcneill #define IMX7D_MIPI_CSI_ROOT_SRC 135 147 1.1 jmcneill #define IMX7D_MIPI_CSI_ROOT_CG 136 148 1.1 jmcneill #define IMX7D_MIPI_CSI_ROOT_DIV 137 149 1.1 jmcneill #define IMX7D_MIPI_DPHY_ROOT_CLK 138 150 1.1 jmcneill #define IMX7D_MIPI_DPHY_ROOT_SRC 139 151 1.1 jmcneill #define IMX7D_MIPI_DPHY_ROOT_CG 140 152 1.1 jmcneill #define IMX7D_MIPI_DPHY_ROOT_DIV 141 153 1.1 jmcneill #define IMX7D_SAI1_ROOT_CLK 142 154 1.1 jmcneill #define IMX7D_SAI1_ROOT_SRC 143 155 1.1 jmcneill #define IMX7D_SAI1_ROOT_CG 144 156 1.1 jmcneill #define IMX7D_SAI1_ROOT_DIV 145 157 1.1 jmcneill #define IMX7D_SAI2_ROOT_CLK 146 158 1.1 jmcneill #define IMX7D_SAI2_ROOT_SRC 147 159 1.1 jmcneill #define IMX7D_SAI2_ROOT_CG 148 160 1.1 jmcneill #define IMX7D_SAI2_ROOT_DIV 149 161 1.1 jmcneill #define IMX7D_SAI3_ROOT_CLK 150 162 1.1 jmcneill #define IMX7D_SAI3_ROOT_SRC 151 163 1.1 jmcneill #define IMX7D_SAI3_ROOT_CG 152 164 1.1 jmcneill #define IMX7D_SAI3_ROOT_DIV 153 165 1.1 jmcneill #define IMX7D_SPDIF_ROOT_CLK 154 166 1.1 jmcneill #define IMX7D_SPDIF_ROOT_SRC 155 167 1.1 jmcneill #define IMX7D_SPDIF_ROOT_CG 156 168 1.1 jmcneill #define IMX7D_SPDIF_ROOT_DIV 157 169 1.1.1.5 jmcneill #define IMX7D_ENET1_IPG_ROOT_CLK 158 170 1.1 jmcneill #define IMX7D_ENET1_REF_ROOT_SRC 159 171 1.1 jmcneill #define IMX7D_ENET1_REF_ROOT_CG 160 172 1.1 jmcneill #define IMX7D_ENET1_REF_ROOT_DIV 161 173 1.1 jmcneill #define IMX7D_ENET1_TIME_ROOT_CLK 162 174 1.1 jmcneill #define IMX7D_ENET1_TIME_ROOT_SRC 163 175 1.1 jmcneill #define IMX7D_ENET1_TIME_ROOT_CG 164 176 1.1 jmcneill #define IMX7D_ENET1_TIME_ROOT_DIV 165 177 1.1.1.5 jmcneill #define IMX7D_ENET2_IPG_ROOT_CLK 166 178 1.1 jmcneill #define IMX7D_ENET2_REF_ROOT_SRC 167 179 1.1 jmcneill #define IMX7D_ENET2_REF_ROOT_CG 168 180 1.1 jmcneill #define IMX7D_ENET2_REF_ROOT_DIV 169 181 1.1 jmcneill #define IMX7D_ENET2_TIME_ROOT_CLK 170 182 1.1 jmcneill #define IMX7D_ENET2_TIME_ROOT_SRC 171 183 1.1 jmcneill #define IMX7D_ENET2_TIME_ROOT_CG 172 184 1.1 jmcneill #define IMX7D_ENET2_TIME_ROOT_DIV 173 185 1.1 jmcneill #define IMX7D_ENET_PHY_REF_ROOT_CLK 174 186 1.1 jmcneill #define IMX7D_ENET_PHY_REF_ROOT_SRC 175 187 1.1 jmcneill #define IMX7D_ENET_PHY_REF_ROOT_CG 176 188 1.1 jmcneill #define IMX7D_ENET_PHY_REF_ROOT_DIV 177 189 1.1 jmcneill #define IMX7D_EIM_ROOT_CLK 178 190 1.1 jmcneill #define IMX7D_EIM_ROOT_SRC 179 191 1.1 jmcneill #define IMX7D_EIM_ROOT_CG 180 192 1.1 jmcneill #define IMX7D_EIM_ROOT_DIV 181 193 1.1 jmcneill #define IMX7D_NAND_ROOT_CLK 182 194 1.1 jmcneill #define IMX7D_NAND_ROOT_SRC 183 195 1.1 jmcneill #define IMX7D_NAND_ROOT_CG 184 196 1.1 jmcneill #define IMX7D_NAND_ROOT_DIV 185 197 1.1 jmcneill #define IMX7D_QSPI_ROOT_CLK 186 198 1.1 jmcneill #define IMX7D_QSPI_ROOT_SRC 187 199 1.1 jmcneill #define IMX7D_QSPI_ROOT_CG 188 200 1.1 jmcneill #define IMX7D_QSPI_ROOT_DIV 189 201 1.1 jmcneill #define IMX7D_USDHC1_ROOT_CLK 190 202 1.1 jmcneill #define IMX7D_USDHC1_ROOT_SRC 191 203 1.1 jmcneill #define IMX7D_USDHC1_ROOT_CG 192 204 1.1 jmcneill #define IMX7D_USDHC1_ROOT_DIV 193 205 1.1 jmcneill #define IMX7D_USDHC2_ROOT_CLK 194 206 1.1 jmcneill #define IMX7D_USDHC2_ROOT_SRC 195 207 1.1 jmcneill #define IMX7D_USDHC2_ROOT_CG 196 208 1.1 jmcneill #define IMX7D_USDHC2_ROOT_DIV 197 209 1.1 jmcneill #define IMX7D_USDHC3_ROOT_CLK 198 210 1.1 jmcneill #define IMX7D_USDHC3_ROOT_SRC 199 211 1.1 jmcneill #define IMX7D_USDHC3_ROOT_CG 200 212 1.1 jmcneill #define IMX7D_USDHC3_ROOT_DIV 201 213 1.1 jmcneill #define IMX7D_CAN1_ROOT_CLK 202 214 1.1 jmcneill #define IMX7D_CAN1_ROOT_SRC 203 215 1.1 jmcneill #define IMX7D_CAN1_ROOT_CG 204 216 1.1 jmcneill #define IMX7D_CAN1_ROOT_DIV 205 217 1.1 jmcneill #define IMX7D_CAN2_ROOT_CLK 206 218 1.1 jmcneill #define IMX7D_CAN2_ROOT_SRC 207 219 1.1 jmcneill #define IMX7D_CAN2_ROOT_CG 208 220 1.1 jmcneill #define IMX7D_CAN2_ROOT_DIV 209 221 1.1 jmcneill #define IMX7D_I2C1_ROOT_CLK 210 222 1.1 jmcneill #define IMX7D_I2C1_ROOT_SRC 211 223 1.1 jmcneill #define IMX7D_I2C1_ROOT_CG 212 224 1.1 jmcneill #define IMX7D_I2C1_ROOT_DIV 213 225 1.1 jmcneill #define IMX7D_I2C2_ROOT_CLK 214 226 1.1 jmcneill #define IMX7D_I2C2_ROOT_SRC 215 227 1.1 jmcneill #define IMX7D_I2C2_ROOT_CG 216 228 1.1 jmcneill #define IMX7D_I2C2_ROOT_DIV 217 229 1.1 jmcneill #define IMX7D_I2C3_ROOT_CLK 218 230 1.1 jmcneill #define IMX7D_I2C3_ROOT_SRC 219 231 1.1 jmcneill #define IMX7D_I2C3_ROOT_CG 220 232 1.1 jmcneill #define IMX7D_I2C3_ROOT_DIV 221 233 1.1 jmcneill #define IMX7D_I2C4_ROOT_CLK 222 234 1.1 jmcneill #define IMX7D_I2C4_ROOT_SRC 223 235 1.1 jmcneill #define IMX7D_I2C4_ROOT_CG 224 236 1.1 jmcneill #define IMX7D_I2C4_ROOT_DIV 225 237 1.1 jmcneill #define IMX7D_UART1_ROOT_CLK 226 238 1.1 jmcneill #define IMX7D_UART1_ROOT_SRC 227 239 1.1 jmcneill #define IMX7D_UART1_ROOT_CG 228 240 1.1 jmcneill #define IMX7D_UART1_ROOT_DIV 229 241 1.1 jmcneill #define IMX7D_UART2_ROOT_CLK 230 242 1.1 jmcneill #define IMX7D_UART2_ROOT_SRC 231 243 1.1 jmcneill #define IMX7D_UART2_ROOT_CG 232 244 1.1 jmcneill #define IMX7D_UART2_ROOT_DIV 233 245 1.1 jmcneill #define IMX7D_UART3_ROOT_CLK 234 246 1.1 jmcneill #define IMX7D_UART3_ROOT_SRC 235 247 1.1 jmcneill #define IMX7D_UART3_ROOT_CG 236 248 1.1 jmcneill #define IMX7D_UART3_ROOT_DIV 237 249 1.1 jmcneill #define IMX7D_UART4_ROOT_CLK 238 250 1.1 jmcneill #define IMX7D_UART4_ROOT_SRC 239 251 1.1 jmcneill #define IMX7D_UART4_ROOT_CG 240 252 1.1 jmcneill #define IMX7D_UART4_ROOT_DIV 241 253 1.1 jmcneill #define IMX7D_UART5_ROOT_CLK 242 254 1.1 jmcneill #define IMX7D_UART5_ROOT_SRC 243 255 1.1 jmcneill #define IMX7D_UART5_ROOT_CG 244 256 1.1 jmcneill #define IMX7D_UART5_ROOT_DIV 245 257 1.1 jmcneill #define IMX7D_UART6_ROOT_CLK 246 258 1.1 jmcneill #define IMX7D_UART6_ROOT_SRC 247 259 1.1 jmcneill #define IMX7D_UART6_ROOT_CG 248 260 1.1 jmcneill #define IMX7D_UART6_ROOT_DIV 249 261 1.1 jmcneill #define IMX7D_UART7_ROOT_CLK 250 262 1.1 jmcneill #define IMX7D_UART7_ROOT_SRC 251 263 1.1 jmcneill #define IMX7D_UART7_ROOT_CG 252 264 1.1 jmcneill #define IMX7D_UART7_ROOT_DIV 253 265 1.1 jmcneill #define IMX7D_ECSPI1_ROOT_CLK 254 266 1.1 jmcneill #define IMX7D_ECSPI1_ROOT_SRC 255 267 1.1 jmcneill #define IMX7D_ECSPI1_ROOT_CG 256 268 1.1 jmcneill #define IMX7D_ECSPI1_ROOT_DIV 257 269 1.1 jmcneill #define IMX7D_ECSPI2_ROOT_CLK 258 270 1.1 jmcneill #define IMX7D_ECSPI2_ROOT_SRC 259 271 1.1 jmcneill #define IMX7D_ECSPI2_ROOT_CG 260 272 1.1 jmcneill #define IMX7D_ECSPI2_ROOT_DIV 261 273 1.1 jmcneill #define IMX7D_ECSPI3_ROOT_CLK 262 274 1.1 jmcneill #define IMX7D_ECSPI3_ROOT_SRC 263 275 1.1 jmcneill #define IMX7D_ECSPI3_ROOT_CG 264 276 1.1 jmcneill #define IMX7D_ECSPI3_ROOT_DIV 265 277 1.1 jmcneill #define IMX7D_ECSPI4_ROOT_CLK 266 278 1.1 jmcneill #define IMX7D_ECSPI4_ROOT_SRC 267 279 1.1 jmcneill #define IMX7D_ECSPI4_ROOT_CG 268 280 1.1 jmcneill #define IMX7D_ECSPI4_ROOT_DIV 269 281 1.1 jmcneill #define IMX7D_PWM1_ROOT_CLK 270 282 1.1 jmcneill #define IMX7D_PWM1_ROOT_SRC 271 283 1.1 jmcneill #define IMX7D_PWM1_ROOT_CG 272 284 1.1 jmcneill #define IMX7D_PWM1_ROOT_DIV 273 285 1.1 jmcneill #define IMX7D_PWM2_ROOT_CLK 274 286 1.1 jmcneill #define IMX7D_PWM2_ROOT_SRC 275 287 1.1 jmcneill #define IMX7D_PWM2_ROOT_CG 276 288 1.1 jmcneill #define IMX7D_PWM2_ROOT_DIV 277 289 1.1 jmcneill #define IMX7D_PWM3_ROOT_CLK 278 290 1.1 jmcneill #define IMX7D_PWM3_ROOT_SRC 279 291 1.1 jmcneill #define IMX7D_PWM3_ROOT_CG 280 292 1.1 jmcneill #define IMX7D_PWM3_ROOT_DIV 281 293 1.1 jmcneill #define IMX7D_PWM4_ROOT_CLK 282 294 1.1 jmcneill #define IMX7D_PWM4_ROOT_SRC 283 295 1.1 jmcneill #define IMX7D_PWM4_ROOT_CG 284 296 1.1 jmcneill #define IMX7D_PWM4_ROOT_DIV 285 297 1.1 jmcneill #define IMX7D_FLEXTIMER1_ROOT_CLK 286 298 1.1 jmcneill #define IMX7D_FLEXTIMER1_ROOT_SRC 287 299 1.1 jmcneill #define IMX7D_FLEXTIMER1_ROOT_CG 288 300 1.1 jmcneill #define IMX7D_FLEXTIMER1_ROOT_DIV 289 301 1.1 jmcneill #define IMX7D_FLEXTIMER2_ROOT_CLK 290 302 1.1 jmcneill #define IMX7D_FLEXTIMER2_ROOT_SRC 291 303 1.1 jmcneill #define IMX7D_FLEXTIMER2_ROOT_CG 292 304 1.1 jmcneill #define IMX7D_FLEXTIMER2_ROOT_DIV 293 305 1.1 jmcneill #define IMX7D_SIM1_ROOT_CLK 294 306 1.1 jmcneill #define IMX7D_SIM1_ROOT_SRC 295 307 1.1 jmcneill #define IMX7D_SIM1_ROOT_CG 296 308 1.1 jmcneill #define IMX7D_SIM1_ROOT_DIV 297 309 1.1 jmcneill #define IMX7D_SIM2_ROOT_CLK 298 310 1.1 jmcneill #define IMX7D_SIM2_ROOT_SRC 299 311 1.1 jmcneill #define IMX7D_SIM2_ROOT_CG 300 312 1.1 jmcneill #define IMX7D_SIM2_ROOT_DIV 301 313 1.1 jmcneill #define IMX7D_GPT1_ROOT_CLK 302 314 1.1 jmcneill #define IMX7D_GPT1_ROOT_SRC 303 315 1.1 jmcneill #define IMX7D_GPT1_ROOT_CG 304 316 1.1 jmcneill #define IMX7D_GPT1_ROOT_DIV 305 317 1.1 jmcneill #define IMX7D_GPT2_ROOT_CLK 306 318 1.1 jmcneill #define IMX7D_GPT2_ROOT_SRC 307 319 1.1 jmcneill #define IMX7D_GPT2_ROOT_CG 308 320 1.1 jmcneill #define IMX7D_GPT2_ROOT_DIV 309 321 1.1 jmcneill #define IMX7D_GPT3_ROOT_CLK 310 322 1.1 jmcneill #define IMX7D_GPT3_ROOT_SRC 311 323 1.1 jmcneill #define IMX7D_GPT3_ROOT_CG 312 324 1.1 jmcneill #define IMX7D_GPT3_ROOT_DIV 313 325 1.1 jmcneill #define IMX7D_GPT4_ROOT_CLK 314 326 1.1 jmcneill #define IMX7D_GPT4_ROOT_SRC 315 327 1.1 jmcneill #define IMX7D_GPT4_ROOT_CG 316 328 1.1 jmcneill #define IMX7D_GPT4_ROOT_DIV 317 329 1.1 jmcneill #define IMX7D_TRACE_ROOT_CLK 318 330 1.1 jmcneill #define IMX7D_TRACE_ROOT_SRC 319 331 1.1 jmcneill #define IMX7D_TRACE_ROOT_CG 320 332 1.1 jmcneill #define IMX7D_TRACE_ROOT_DIV 321 333 1.1 jmcneill #define IMX7D_WDOG1_ROOT_CLK 322 334 1.1 jmcneill #define IMX7D_WDOG_ROOT_SRC 323 335 1.1 jmcneill #define IMX7D_WDOG_ROOT_CG 324 336 1.1 jmcneill #define IMX7D_WDOG_ROOT_DIV 325 337 1.1 jmcneill #define IMX7D_CSI_MCLK_ROOT_CLK 326 338 1.1 jmcneill #define IMX7D_CSI_MCLK_ROOT_SRC 327 339 1.1 jmcneill #define IMX7D_CSI_MCLK_ROOT_CG 328 340 1.1 jmcneill #define IMX7D_CSI_MCLK_ROOT_DIV 329 341 1.1 jmcneill #define IMX7D_AUDIO_MCLK_ROOT_CLK 330 342 1.1 jmcneill #define IMX7D_AUDIO_MCLK_ROOT_SRC 331 343 1.1 jmcneill #define IMX7D_AUDIO_MCLK_ROOT_CG 332 344 1.1 jmcneill #define IMX7D_AUDIO_MCLK_ROOT_DIV 333 345 1.1 jmcneill #define IMX7D_WRCLK_ROOT_CLK 334 346 1.1 jmcneill #define IMX7D_WRCLK_ROOT_SRC 335 347 1.1 jmcneill #define IMX7D_WRCLK_ROOT_CG 336 348 1.1 jmcneill #define IMX7D_WRCLK_ROOT_DIV 337 349 1.1 jmcneill #define IMX7D_CLKO1_ROOT_SRC 338 350 1.1 jmcneill #define IMX7D_CLKO1_ROOT_CG 339 351 1.1 jmcneill #define IMX7D_CLKO1_ROOT_DIV 340 352 1.1 jmcneill #define IMX7D_CLKO2_ROOT_SRC 341 353 1.1 jmcneill #define IMX7D_CLKO2_ROOT_CG 342 354 1.1 jmcneill #define IMX7D_CLKO2_ROOT_DIV 343 355 1.1 jmcneill #define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 356 1.1 jmcneill #define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 357 1.1 jmcneill #define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 358 1.1 jmcneill #define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 359 1.1 jmcneill #define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 360 1.1 jmcneill #define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 361 1.1 jmcneill #define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 362 1.1 jmcneill #define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 363 1.1 jmcneill #define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 364 1.1 jmcneill #define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 365 1.1 jmcneill #define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 366 1.1 jmcneill #define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 367 1.1 jmcneill #define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 368 1.1 jmcneill #define IMX7D_SAI1_ROOT_PRE_DIV 357 369 1.1 jmcneill #define IMX7D_SAI2_ROOT_PRE_DIV 358 370 1.1 jmcneill #define IMX7D_SAI3_ROOT_PRE_DIV 359 371 1.1 jmcneill #define IMX7D_SPDIF_ROOT_PRE_DIV 360 372 1.1 jmcneill #define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 373 1.1 jmcneill #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 374 1.1 jmcneill #define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 375 1.1 jmcneill #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 376 1.1 jmcneill #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 377 1.1 jmcneill #define IMX7D_EIM_ROOT_PRE_DIV 366 378 1.1 jmcneill #define IMX7D_NAND_ROOT_PRE_DIV 367 379 1.1 jmcneill #define IMX7D_QSPI_ROOT_PRE_DIV 368 380 1.1 jmcneill #define IMX7D_USDHC1_ROOT_PRE_DIV 369 381 1.1 jmcneill #define IMX7D_USDHC2_ROOT_PRE_DIV 370 382 1.1 jmcneill #define IMX7D_USDHC3_ROOT_PRE_DIV 371 383 1.1 jmcneill #define IMX7D_CAN1_ROOT_PRE_DIV 372 384 1.1 jmcneill #define IMX7D_CAN2_ROOT_PRE_DIV 373 385 1.1 jmcneill #define IMX7D_I2C1_ROOT_PRE_DIV 374 386 1.1 jmcneill #define IMX7D_I2C2_ROOT_PRE_DIV 375 387 1.1 jmcneill #define IMX7D_I2C3_ROOT_PRE_DIV 376 388 1.1 jmcneill #define IMX7D_I2C4_ROOT_PRE_DIV 377 389 1.1 jmcneill #define IMX7D_UART1_ROOT_PRE_DIV 378 390 1.1 jmcneill #define IMX7D_UART2_ROOT_PRE_DIV 379 391 1.1 jmcneill #define IMX7D_UART3_ROOT_PRE_DIV 380 392 1.1 jmcneill #define IMX7D_UART4_ROOT_PRE_DIV 381 393 1.1 jmcneill #define IMX7D_UART5_ROOT_PRE_DIV 382 394 1.1 jmcneill #define IMX7D_UART6_ROOT_PRE_DIV 383 395 1.1 jmcneill #define IMX7D_UART7_ROOT_PRE_DIV 384 396 1.1 jmcneill #define IMX7D_ECSPI1_ROOT_PRE_DIV 385 397 1.1 jmcneill #define IMX7D_ECSPI2_ROOT_PRE_DIV 386 398 1.1 jmcneill #define IMX7D_ECSPI3_ROOT_PRE_DIV 387 399 1.1 jmcneill #define IMX7D_ECSPI4_ROOT_PRE_DIV 388 400 1.1 jmcneill #define IMX7D_PWM1_ROOT_PRE_DIV 389 401 1.1 jmcneill #define IMX7D_PWM2_ROOT_PRE_DIV 390 402 1.1 jmcneill #define IMX7D_PWM3_ROOT_PRE_DIV 391 403 1.1 jmcneill #define IMX7D_PWM4_ROOT_PRE_DIV 392 404 1.1 jmcneill #define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 405 1.1 jmcneill #define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 406 1.1 jmcneill #define IMX7D_SIM1_ROOT_PRE_DIV 395 407 1.1 jmcneill #define IMX7D_SIM2_ROOT_PRE_DIV 396 408 1.1 jmcneill #define IMX7D_GPT1_ROOT_PRE_DIV 397 409 1.1 jmcneill #define IMX7D_GPT2_ROOT_PRE_DIV 398 410 1.1 jmcneill #define IMX7D_GPT3_ROOT_PRE_DIV 399 411 1.1 jmcneill #define IMX7D_GPT4_ROOT_PRE_DIV 400 412 1.1 jmcneill #define IMX7D_TRACE_ROOT_PRE_DIV 401 413 1.1 jmcneill #define IMX7D_WDOG_ROOT_PRE_DIV 402 414 1.1 jmcneill #define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 415 1.1 jmcneill #define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 416 1.1 jmcneill #define IMX7D_WRCLK_ROOT_PRE_DIV 405 417 1.1 jmcneill #define IMX7D_CLKO1_ROOT_PRE_DIV 406 418 1.1 jmcneill #define IMX7D_CLKO2_ROOT_PRE_DIV 407 419 1.1 jmcneill #define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 420 1.1 jmcneill #define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 421 1.1 jmcneill #define IMX7D_LVDS1_IN_CLK 410 422 1.1 jmcneill #define IMX7D_LVDS1_OUT_SEL 411 423 1.1 jmcneill #define IMX7D_LVDS1_OUT_CLK 412 424 1.1 jmcneill #define IMX7D_CLK_DUMMY 413 425 1.1 jmcneill #define IMX7D_GPT_3M_CLK 414 426 1.1 jmcneill #define IMX7D_OCRAM_CLK 415 427 1.1 jmcneill #define IMX7D_OCRAM_S_CLK 416 428 1.1 jmcneill #define IMX7D_WDOG2_ROOT_CLK 417 429 1.1 jmcneill #define IMX7D_WDOG3_ROOT_CLK 418 430 1.1 jmcneill #define IMX7D_WDOG4_ROOT_CLK 419 431 1.1 jmcneill #define IMX7D_SDMA_CORE_CLK 420 432 1.1 jmcneill #define IMX7D_USB1_MAIN_480M_CLK 421 433 1.1 jmcneill #define IMX7D_USB_CTRL_CLK 422 434 1.1 jmcneill #define IMX7D_USB_PHY1_CLK 423 435 1.1 jmcneill #define IMX7D_USB_PHY2_CLK 424 436 1.1 jmcneill #define IMX7D_IPG_ROOT_CLK 425 437 1.1 jmcneill #define IMX7D_SAI1_IPG_CLK 426 438 1.1 jmcneill #define IMX7D_SAI2_IPG_CLK 427 439 1.1 jmcneill #define IMX7D_SAI3_IPG_CLK 428 440 1.1 jmcneill #define IMX7D_PLL_AUDIO_TEST_DIV 429 441 1.1 jmcneill #define IMX7D_PLL_AUDIO_POST_DIV 430 442 1.1 jmcneill #define IMX7D_PLL_VIDEO_TEST_DIV 431 443 1.1 jmcneill #define IMX7D_PLL_VIDEO_POST_DIV 432 444 1.1 jmcneill #define IMX7D_MU_ROOT_CLK 433 445 1.1 jmcneill #define IMX7D_SEMA4_HS_ROOT_CLK 434 446 1.1 jmcneill #define IMX7D_PLL_DRAM_TEST_DIV 435 447 1.1 jmcneill #define IMX7D_ADC_ROOT_CLK 436 448 1.1 jmcneill #define IMX7D_CLK_ARM 437 449 1.1 jmcneill #define IMX7D_CKIL 438 450 1.1 jmcneill #define IMX7D_OCOTP_CLK 439 451 1.1.1.2 jmcneill #define IMX7D_NAND_RAWNAND_CLK 440 452 1.1.1.2 jmcneill #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 453 1.1.1.4 jmcneill #define IMX7D_SNVS_CLK 442 454 1.1.1.4 jmcneill #define IMX7D_CAAM_CLK 443 455 1.1.1.4 jmcneill #define IMX7D_KPP_ROOT_CLK 444 456 1.1.1.7 jmcneill #define IMX7D_PXP_CLK 445 457 1.1.1.7 jmcneill #define IMX7D_CLK_END 446 458 1.1 jmcneill #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 459