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      1      1.1  jmcneill /*	$NetBSD: imx8-clock.h,v 1.1.1.3 2021/11/07 16:49:59 jmcneill Exp $	*/
      2      1.1  jmcneill 
      3      1.1  jmcneill /* SPDX-License-Identifier: GPL-2.0+ */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * Copyright 2018 NXP
      6      1.1  jmcneill  *   Dong Aisheng <aisheng.dong (at) nxp.com>
      7      1.1  jmcneill  */
      8      1.1  jmcneill 
      9      1.1  jmcneill #ifndef __DT_BINDINGS_CLOCK_IMX_H
     10      1.1  jmcneill #define __DT_BINDINGS_CLOCK_IMX_H
     11      1.1  jmcneill 
     12      1.1  jmcneill /* LPCG clocks */
     13      1.1  jmcneill 
     14      1.1  jmcneill /* LSIO SS LPCG */
     15      1.1  jmcneill #define IMX_LSIO_LPCG_PWM0_IPG_CLK			0
     16      1.1  jmcneill #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK			1
     17      1.1  jmcneill #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK			2
     18      1.1  jmcneill #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK			3
     19      1.1  jmcneill #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK			4
     20      1.1  jmcneill #define IMX_LSIO_LPCG_PWM1_IPG_CLK			5
     21      1.1  jmcneill #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK			6
     22      1.1  jmcneill #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK			7
     23      1.1  jmcneill #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK			8
     24      1.1  jmcneill #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK			9
     25      1.1  jmcneill #define IMX_LSIO_LPCG_PWM2_IPG_CLK			10
     26      1.1  jmcneill #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK			11
     27      1.1  jmcneill #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK			12
     28      1.1  jmcneill #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK			13
     29      1.1  jmcneill #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK			14
     30      1.1  jmcneill #define IMX_LSIO_LPCG_PWM3_IPG_CLK			15
     31      1.1  jmcneill #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK			16
     32      1.1  jmcneill #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK			17
     33      1.1  jmcneill #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK			18
     34      1.1  jmcneill #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK			19
     35      1.1  jmcneill #define IMX_LSIO_LPCG_PWM4_IPG_CLK			20
     36      1.1  jmcneill #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK			21
     37      1.1  jmcneill #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK			22
     38      1.1  jmcneill #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK			23
     39      1.1  jmcneill #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK			24
     40      1.1  jmcneill #define IMX_LSIO_LPCG_PWM5_IPG_CLK			25
     41      1.1  jmcneill #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK			26
     42      1.1  jmcneill #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK			27
     43      1.1  jmcneill #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK			28
     44      1.1  jmcneill #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK			29
     45      1.1  jmcneill #define IMX_LSIO_LPCG_PWM6_IPG_CLK			30
     46      1.1  jmcneill #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK			31
     47      1.1  jmcneill #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK			32
     48      1.1  jmcneill #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK			33
     49      1.1  jmcneill #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK			34
     50      1.1  jmcneill #define IMX_LSIO_LPCG_PWM7_IPG_CLK			35
     51      1.1  jmcneill #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK			36
     52      1.1  jmcneill #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK			37
     53      1.1  jmcneill #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK			38
     54      1.1  jmcneill #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK			39
     55      1.1  jmcneill #define IMX_LSIO_LPCG_GPT0_IPG_CLK			40
     56      1.1  jmcneill #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK			41
     57      1.1  jmcneill #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK			42
     58      1.1  jmcneill #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK			43
     59      1.1  jmcneill #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK			44
     60      1.1  jmcneill #define IMX_LSIO_LPCG_GPT1_IPG_CLK			45
     61      1.1  jmcneill #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK			46
     62      1.1  jmcneill #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK			47
     63      1.1  jmcneill #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK			48
     64      1.1  jmcneill #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK			49
     65      1.1  jmcneill #define IMX_LSIO_LPCG_GPT2_IPG_CLK			50
     66      1.1  jmcneill #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK			51
     67      1.1  jmcneill #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK			52
     68      1.1  jmcneill #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK			53
     69      1.1  jmcneill #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK			54
     70      1.1  jmcneill #define IMX_LSIO_LPCG_GPT3_IPG_CLK			55
     71      1.1  jmcneill #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK			56
     72      1.1  jmcneill #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK			57
     73      1.1  jmcneill #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK			58
     74      1.1  jmcneill #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK			59
     75      1.1  jmcneill #define IMX_LSIO_LPCG_GPT4_IPG_CLK			60
     76      1.1  jmcneill #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK			61
     77      1.1  jmcneill #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK			62
     78      1.1  jmcneill #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK			63
     79      1.1  jmcneill #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK			64
     80      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI0_HCLK			65
     81      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI0_IPG_CLK			66
     82      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK			67
     83      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK			68
     84      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI1_HCLK			69
     85      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI1_IPG_CLK			70
     86      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK			71
     87      1.1  jmcneill #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK			72
     88      1.1  jmcneill 
     89      1.1  jmcneill #define IMX_LSIO_LPCG_CLK_END				73
     90      1.1  jmcneill 
     91      1.1  jmcneill /* Connectivity SS LPCG */
     92      1.1  jmcneill #define IMX_CONN_LPCG_SDHC0_IPG_CLK			0
     93      1.1  jmcneill #define IMX_CONN_LPCG_SDHC0_PER_CLK			1
     94      1.1  jmcneill #define IMX_CONN_LPCG_SDHC0_HCLK			2
     95      1.1  jmcneill #define IMX_CONN_LPCG_SDHC1_IPG_CLK			3
     96      1.1  jmcneill #define IMX_CONN_LPCG_SDHC1_PER_CLK			4
     97      1.1  jmcneill #define IMX_CONN_LPCG_SDHC1_HCLK			5
     98      1.1  jmcneill #define IMX_CONN_LPCG_SDHC2_IPG_CLK			6
     99      1.1  jmcneill #define IMX_CONN_LPCG_SDHC2_PER_CLK			7
    100      1.1  jmcneill #define IMX_CONN_LPCG_SDHC2_HCLK			8
    101      1.1  jmcneill #define IMX_CONN_LPCG_GPMI_APB_CLK			9
    102      1.1  jmcneill #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK			10
    103      1.1  jmcneill #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK			11
    104      1.1  jmcneill #define IMX_CONN_LPCG_GPMI_BCH_CLK			12
    105      1.1  jmcneill #define IMX_CONN_LPCG_APBHDMA_CLK			13
    106      1.1  jmcneill #define IMX_CONN_LPCG_ENET0_ROOT_CLK			14
    107      1.1  jmcneill #define IMX_CONN_LPCG_ENET0_TX_CLK			15
    108      1.1  jmcneill #define IMX_CONN_LPCG_ENET0_AHB_CLK			16
    109      1.1  jmcneill #define IMX_CONN_LPCG_ENET0_IPG_S_CLK			17
    110      1.1  jmcneill #define IMX_CONN_LPCG_ENET0_IPG_CLK			18
    111      1.1  jmcneill 
    112      1.1  jmcneill #define IMX_CONN_LPCG_ENET1_ROOT_CLK			19
    113      1.1  jmcneill #define IMX_CONN_LPCG_ENET1_TX_CLK			20
    114      1.1  jmcneill #define IMX_CONN_LPCG_ENET1_AHB_CLK			21
    115      1.1  jmcneill #define IMX_CONN_LPCG_ENET1_IPG_S_CLK			22
    116      1.1  jmcneill #define IMX_CONN_LPCG_ENET1_IPG_CLK			23
    117      1.1  jmcneill 
    118      1.1  jmcneill #define IMX_CONN_LPCG_CLK_END				24
    119      1.1  jmcneill 
    120      1.1  jmcneill /* ADMA SS LPCG */
    121      1.1  jmcneill #define IMX_ADMA_LPCG_UART0_IPG_CLK			0
    122      1.1  jmcneill #define IMX_ADMA_LPCG_UART0_BAUD_CLK			1
    123      1.1  jmcneill #define IMX_ADMA_LPCG_UART1_IPG_CLK			2
    124      1.1  jmcneill #define IMX_ADMA_LPCG_UART1_BAUD_CLK			3
    125      1.1  jmcneill #define IMX_ADMA_LPCG_UART2_IPG_CLK			4
    126      1.1  jmcneill #define IMX_ADMA_LPCG_UART2_BAUD_CLK			5
    127      1.1  jmcneill #define IMX_ADMA_LPCG_UART3_IPG_CLK			6
    128      1.1  jmcneill #define IMX_ADMA_LPCG_UART3_BAUD_CLK			7
    129      1.1  jmcneill #define IMX_ADMA_LPCG_SPI0_IPG_CLK			8
    130      1.1  jmcneill #define IMX_ADMA_LPCG_SPI1_IPG_CLK			9
    131      1.1  jmcneill #define IMX_ADMA_LPCG_SPI2_IPG_CLK			10
    132      1.1  jmcneill #define IMX_ADMA_LPCG_SPI3_IPG_CLK			11
    133      1.1  jmcneill #define IMX_ADMA_LPCG_SPI0_CLK				12
    134      1.1  jmcneill #define IMX_ADMA_LPCG_SPI1_CLK				13
    135      1.1  jmcneill #define IMX_ADMA_LPCG_SPI2_CLK				14
    136      1.1  jmcneill #define IMX_ADMA_LPCG_SPI3_CLK				15
    137      1.1  jmcneill #define IMX_ADMA_LPCG_CAN0_IPG_CLK			16
    138      1.1  jmcneill #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK			17
    139      1.1  jmcneill #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK			18
    140      1.1  jmcneill #define IMX_ADMA_LPCG_CAN1_IPG_CLK			19
    141      1.1  jmcneill #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK			20
    142      1.1  jmcneill #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK			21
    143      1.1  jmcneill #define IMX_ADMA_LPCG_CAN2_IPG_CLK			22
    144      1.1  jmcneill #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK			23
    145      1.1  jmcneill #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK			24
    146      1.1  jmcneill #define IMX_ADMA_LPCG_I2C0_CLK				25
    147      1.1  jmcneill #define IMX_ADMA_LPCG_I2C1_CLK				26
    148      1.1  jmcneill #define IMX_ADMA_LPCG_I2C2_CLK				27
    149      1.1  jmcneill #define IMX_ADMA_LPCG_I2C3_CLK				28
    150      1.1  jmcneill #define IMX_ADMA_LPCG_I2C0_IPG_CLK			29
    151      1.1  jmcneill #define IMX_ADMA_LPCG_I2C1_IPG_CLK			30
    152      1.1  jmcneill #define IMX_ADMA_LPCG_I2C2_IPG_CLK			31
    153      1.1  jmcneill #define IMX_ADMA_LPCG_I2C3_IPG_CLK			32
    154      1.1  jmcneill #define IMX_ADMA_LPCG_FTM0_CLK				33
    155      1.1  jmcneill #define IMX_ADMA_LPCG_FTM1_CLK				34
    156      1.1  jmcneill #define IMX_ADMA_LPCG_FTM0_IPG_CLK			35
    157      1.1  jmcneill #define IMX_ADMA_LPCG_FTM1_IPG_CLK			36
    158      1.1  jmcneill #define IMX_ADMA_LPCG_PWM_HI_CLK			37
    159      1.1  jmcneill #define IMX_ADMA_LPCG_PWM_IPG_CLK			38
    160      1.1  jmcneill #define IMX_ADMA_LPCG_LCD_PIX_CLK			39
    161      1.1  jmcneill #define IMX_ADMA_LPCG_LCD_APB_CLK			40
    162  1.1.1.2     skrll #define IMX_ADMA_LPCG_DSP_ADB_CLK			41
    163  1.1.1.2     skrll #define IMX_ADMA_LPCG_DSP_IPG_CLK			42
    164  1.1.1.2     skrll #define IMX_ADMA_LPCG_DSP_CORE_CLK			43
    165  1.1.1.2     skrll #define IMX_ADMA_LPCG_OCRAM_IPG_CLK			44
    166      1.1  jmcneill 
    167  1.1.1.2     skrll #define IMX_ADMA_LPCG_CLK_END				45
    168      1.1  jmcneill 
    169      1.1  jmcneill #endif /* __DT_BINDINGS_CLOCK_IMX_H */
    170