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      1      1.1  jmcneill /*	$NetBSD: imx8mq-clock.h,v 1.1.1.3 2021/11/07 16:49:59 jmcneill Exp $	*/
      2      1.1  jmcneill 
      3      1.1  jmcneill /* SPDX-License-Identifier: GPL-2.0 */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * Copyright 2016 Freescale Semiconductor, Inc.
      6      1.1  jmcneill  * Copyright 2017 NXP
      7      1.1  jmcneill  */
      8      1.1  jmcneill 
      9      1.1  jmcneill #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
     10      1.1  jmcneill #define __DT_BINDINGS_CLOCK_IMX8MQ_H
     11      1.1  jmcneill 
     12      1.1  jmcneill #define IMX8MQ_CLK_DUMMY		0
     13      1.1  jmcneill #define IMX8MQ_CLK_32K			1
     14      1.1  jmcneill #define IMX8MQ_CLK_25M			2
     15      1.1  jmcneill #define IMX8MQ_CLK_27M			3
     16      1.1  jmcneill #define IMX8MQ_CLK_EXT1			4
     17      1.1  jmcneill #define IMX8MQ_CLK_EXT2			5
     18      1.1  jmcneill #define IMX8MQ_CLK_EXT3			6
     19      1.1  jmcneill #define IMX8MQ_CLK_EXT4			7
     20      1.1  jmcneill 
     21      1.1  jmcneill /* ANAMIX PLL clocks */
     22      1.1  jmcneill /* FRAC PLLs */
     23      1.1  jmcneill /* ARM PLL */
     24      1.1  jmcneill #define IMX8MQ_ARM_PLL_REF_SEL		8
     25      1.1  jmcneill #define IMX8MQ_ARM_PLL_REF_DIV		9
     26      1.1  jmcneill #define IMX8MQ_ARM_PLL			10
     27      1.1  jmcneill #define IMX8MQ_ARM_PLL_BYPASS		11
     28      1.1  jmcneill #define IMX8MQ_ARM_PLL_OUT		12
     29      1.1  jmcneill 
     30      1.1  jmcneill /* GPU PLL */
     31      1.1  jmcneill #define IMX8MQ_GPU_PLL_REF_SEL		13
     32      1.1  jmcneill #define IMX8MQ_GPU_PLL_REF_DIV		14
     33      1.1  jmcneill #define IMX8MQ_GPU_PLL			15
     34      1.1  jmcneill #define IMX8MQ_GPU_PLL_BYPASS		16
     35      1.1  jmcneill #define IMX8MQ_GPU_PLL_OUT		17
     36      1.1  jmcneill 
     37      1.1  jmcneill /* VPU PLL */
     38      1.1  jmcneill #define IMX8MQ_VPU_PLL_REF_SEL		18
     39      1.1  jmcneill #define IMX8MQ_VPU_PLL_REF_DIV		19
     40      1.1  jmcneill #define IMX8MQ_VPU_PLL			20
     41      1.1  jmcneill #define IMX8MQ_VPU_PLL_BYPASS		21
     42      1.1  jmcneill #define IMX8MQ_VPU_PLL_OUT		22
     43      1.1  jmcneill 
     44      1.1  jmcneill /* AUDIO PLL1 */
     45      1.1  jmcneill #define IMX8MQ_AUDIO_PLL1_REF_SEL	23
     46      1.1  jmcneill #define IMX8MQ_AUDIO_PLL1_REF_DIV	24
     47      1.1  jmcneill #define IMX8MQ_AUDIO_PLL1		25
     48      1.1  jmcneill #define IMX8MQ_AUDIO_PLL1_BYPASS	26
     49      1.1  jmcneill #define IMX8MQ_AUDIO_PLL1_OUT		27
     50      1.1  jmcneill 
     51      1.1  jmcneill /* AUDIO PLL2 */
     52      1.1  jmcneill #define IMX8MQ_AUDIO_PLL2_REF_SEL	28
     53      1.1  jmcneill #define IMX8MQ_AUDIO_PLL2_REF_DIV	29
     54      1.1  jmcneill #define IMX8MQ_AUDIO_PLL2		30
     55      1.1  jmcneill #define IMX8MQ_AUDIO_PLL2_BYPASS	31
     56      1.1  jmcneill #define IMX8MQ_AUDIO_PLL2_OUT		32
     57      1.1  jmcneill 
     58      1.1  jmcneill /* VIDEO PLL1 */
     59      1.1  jmcneill #define IMX8MQ_VIDEO_PLL1_REF_SEL	33
     60      1.1  jmcneill #define IMX8MQ_VIDEO_PLL1_REF_DIV	34
     61      1.1  jmcneill #define IMX8MQ_VIDEO_PLL1		35
     62      1.1  jmcneill #define IMX8MQ_VIDEO_PLL1_BYPASS	36
     63      1.1  jmcneill #define IMX8MQ_VIDEO_PLL1_OUT		37
     64      1.1  jmcneill 
     65      1.1  jmcneill /* SYS1 PLL */
     66      1.1  jmcneill #define IMX8MQ_SYS1_PLL1_REF_SEL	38
     67      1.1  jmcneill #define IMX8MQ_SYS1_PLL1_REF_DIV	39
     68      1.1  jmcneill #define IMX8MQ_SYS1_PLL1		40
     69      1.1  jmcneill #define IMX8MQ_SYS1_PLL1_OUT		41
     70      1.1  jmcneill #define IMX8MQ_SYS1_PLL1_OUT_DIV	42
     71      1.1  jmcneill #define IMX8MQ_SYS1_PLL2		43
     72      1.1  jmcneill #define IMX8MQ_SYS1_PLL2_DIV		44
     73      1.1  jmcneill #define IMX8MQ_SYS1_PLL2_OUT		45
     74      1.1  jmcneill 
     75      1.1  jmcneill /* SYS2 PLL */
     76      1.1  jmcneill #define IMX8MQ_SYS2_PLL1_REF_SEL	46
     77      1.1  jmcneill #define IMX8MQ_SYS2_PLL1_REF_DIV	47
     78      1.1  jmcneill #define IMX8MQ_SYS2_PLL1		48
     79      1.1  jmcneill #define IMX8MQ_SYS2_PLL1_OUT		49
     80      1.1  jmcneill #define IMX8MQ_SYS2_PLL1_OUT_DIV	50
     81      1.1  jmcneill #define IMX8MQ_SYS2_PLL2		51
     82      1.1  jmcneill #define IMX8MQ_SYS2_PLL2_DIV		52
     83      1.1  jmcneill #define IMX8MQ_SYS2_PLL2_OUT		53
     84      1.1  jmcneill 
     85      1.1  jmcneill /* SYS3 PLL */
     86      1.1  jmcneill #define IMX8MQ_SYS3_PLL1_REF_SEL	54
     87      1.1  jmcneill #define IMX8MQ_SYS3_PLL1_REF_DIV	55
     88      1.1  jmcneill #define IMX8MQ_SYS3_PLL1		56
     89      1.1  jmcneill #define IMX8MQ_SYS3_PLL1_OUT		57
     90      1.1  jmcneill #define IMX8MQ_SYS3_PLL1_OUT_DIV	58
     91      1.1  jmcneill #define IMX8MQ_SYS3_PLL2		59
     92      1.1  jmcneill #define IMX8MQ_SYS3_PLL2_DIV		60
     93      1.1  jmcneill #define IMX8MQ_SYS3_PLL2_OUT		61
     94      1.1  jmcneill 
     95      1.1  jmcneill /* DRAM PLL */
     96      1.1  jmcneill #define IMX8MQ_DRAM_PLL1_REF_SEL	62
     97      1.1  jmcneill #define IMX8MQ_DRAM_PLL1_REF_DIV	63
     98      1.1  jmcneill #define IMX8MQ_DRAM_PLL1		64
     99      1.1  jmcneill #define IMX8MQ_DRAM_PLL1_OUT		65
    100      1.1  jmcneill #define IMX8MQ_DRAM_PLL1_OUT_DIV	66
    101      1.1  jmcneill #define IMX8MQ_DRAM_PLL2		67
    102      1.1  jmcneill #define IMX8MQ_DRAM_PLL2_DIV		68
    103      1.1  jmcneill #define IMX8MQ_DRAM_PLL2_OUT		69
    104      1.1  jmcneill 
    105      1.1  jmcneill /* SYS PLL DIV */
    106      1.1  jmcneill #define IMX8MQ_SYS1_PLL_40M		70
    107      1.1  jmcneill #define IMX8MQ_SYS1_PLL_80M		71
    108      1.1  jmcneill #define IMX8MQ_SYS1_PLL_100M		72
    109      1.1  jmcneill #define IMX8MQ_SYS1_PLL_133M		73
    110      1.1  jmcneill #define IMX8MQ_SYS1_PLL_160M		74
    111      1.1  jmcneill #define IMX8MQ_SYS1_PLL_200M		75
    112      1.1  jmcneill #define IMX8MQ_SYS1_PLL_266M		76
    113      1.1  jmcneill #define IMX8MQ_SYS1_PLL_400M		77
    114      1.1  jmcneill #define IMX8MQ_SYS1_PLL_800M		78
    115      1.1  jmcneill 
    116      1.1  jmcneill #define IMX8MQ_SYS2_PLL_50M		79
    117      1.1  jmcneill #define IMX8MQ_SYS2_PLL_100M		80
    118      1.1  jmcneill #define IMX8MQ_SYS2_PLL_125M		81
    119      1.1  jmcneill #define IMX8MQ_SYS2_PLL_166M		82
    120      1.1  jmcneill #define IMX8MQ_SYS2_PLL_200M		83
    121      1.1  jmcneill #define IMX8MQ_SYS2_PLL_250M		84
    122      1.1  jmcneill #define IMX8MQ_SYS2_PLL_333M		85
    123      1.1  jmcneill #define IMX8MQ_SYS2_PLL_500M		86
    124      1.1  jmcneill #define IMX8MQ_SYS2_PLL_1000M		87
    125      1.1  jmcneill 
    126      1.1  jmcneill /* CCM ROOT clocks */
    127      1.1  jmcneill /* A53 */
    128      1.1  jmcneill #define IMX8MQ_CLK_A53_SRC		88
    129      1.1  jmcneill #define IMX8MQ_CLK_A53_CG		89
    130      1.1  jmcneill #define IMX8MQ_CLK_A53_DIV		90
    131      1.1  jmcneill /* M4 */
    132      1.1  jmcneill #define IMX8MQ_CLK_M4_SRC		91
    133      1.1  jmcneill #define IMX8MQ_CLK_M4_CG		92
    134      1.1  jmcneill #define IMX8MQ_CLK_M4_DIV		93
    135      1.1  jmcneill /* VPU */
    136      1.1  jmcneill #define IMX8MQ_CLK_VPU_SRC		94
    137      1.1  jmcneill #define IMX8MQ_CLK_VPU_CG		95
    138      1.1  jmcneill #define IMX8MQ_CLK_VPU_DIV		96
    139      1.1  jmcneill /* GPU CORE */
    140      1.1  jmcneill #define IMX8MQ_CLK_GPU_CORE_SRC		97
    141      1.1  jmcneill #define IMX8MQ_CLK_GPU_CORE_CG		98
    142      1.1  jmcneill #define IMX8MQ_CLK_GPU_CORE_DIV		99
    143      1.1  jmcneill /* GPU SHADER */
    144      1.1  jmcneill #define IMX8MQ_CLK_GPU_SHADER_SRC	100
    145      1.1  jmcneill #define IMX8MQ_CLK_GPU_SHADER_CG	101
    146      1.1  jmcneill #define IMX8MQ_CLK_GPU_SHADER_DIV	102
    147      1.1  jmcneill 
    148      1.1  jmcneill /* BUS TYPE */
    149      1.1  jmcneill /* MAIN AXI */
    150      1.1  jmcneill #define IMX8MQ_CLK_MAIN_AXI		103
    151      1.1  jmcneill /* ENET AXI */
    152      1.1  jmcneill #define IMX8MQ_CLK_ENET_AXI		104
    153      1.1  jmcneill /* NAND_USDHC_BUS */
    154      1.1  jmcneill #define IMX8MQ_CLK_NAND_USDHC_BUS	105
    155      1.1  jmcneill /* VPU BUS */
    156      1.1  jmcneill #define IMX8MQ_CLK_VPU_BUS		106
    157      1.1  jmcneill /* DISP_AXI */
    158      1.1  jmcneill #define IMX8MQ_CLK_DISP_AXI		107
    159      1.1  jmcneill /* DISP APB */
    160      1.1  jmcneill #define IMX8MQ_CLK_DISP_APB		108
    161      1.1  jmcneill /* DISP RTRM */
    162      1.1  jmcneill #define IMX8MQ_CLK_DISP_RTRM		109
    163      1.1  jmcneill /* USB_BUS */
    164      1.1  jmcneill #define IMX8MQ_CLK_USB_BUS		110
    165      1.1  jmcneill /* GPU_AXI */
    166      1.1  jmcneill #define IMX8MQ_CLK_GPU_AXI		111
    167      1.1  jmcneill /* GPU_AHB */
    168      1.1  jmcneill #define IMX8MQ_CLK_GPU_AHB		112
    169      1.1  jmcneill /* NOC */
    170      1.1  jmcneill #define IMX8MQ_CLK_NOC			113
    171      1.1  jmcneill /* NOC_APB */
    172      1.1  jmcneill #define IMX8MQ_CLK_NOC_APB		115
    173      1.1  jmcneill 
    174      1.1  jmcneill /* AHB */
    175      1.1  jmcneill #define IMX8MQ_CLK_AHB			116
    176      1.1  jmcneill /* AUDIO AHB */
    177      1.1  jmcneill #define IMX8MQ_CLK_AUDIO_AHB		117
    178      1.1  jmcneill 
    179      1.1  jmcneill /* DRAM_ALT */
    180      1.1  jmcneill #define IMX8MQ_CLK_DRAM_ALT		118
    181      1.1  jmcneill /* DRAM APB */
    182      1.1  jmcneill #define IMX8MQ_CLK_DRAM_APB		119
    183      1.1  jmcneill /* VPU_G1 */
    184      1.1  jmcneill #define IMX8MQ_CLK_VPU_G1		120
    185      1.1  jmcneill /* VPU_G2 */
    186      1.1  jmcneill #define IMX8MQ_CLK_VPU_G2		121
    187      1.1  jmcneill /* DISP_DTRC */
    188      1.1  jmcneill #define IMX8MQ_CLK_DISP_DTRC		122
    189      1.1  jmcneill /* DISP_DC8000 */
    190      1.1  jmcneill #define IMX8MQ_CLK_DISP_DC8000		123
    191      1.1  jmcneill /* PCIE_CTRL */
    192      1.1  jmcneill #define IMX8MQ_CLK_PCIE1_CTRL		124
    193      1.1  jmcneill /* PCIE_PHY */
    194      1.1  jmcneill #define IMX8MQ_CLK_PCIE1_PHY		125
    195      1.1  jmcneill /* PCIE_AUX */
    196      1.1  jmcneill #define IMX8MQ_CLK_PCIE1_AUX		126
    197      1.1  jmcneill /* DC_PIXEL */
    198      1.1  jmcneill #define IMX8MQ_CLK_DC_PIXEL		127
    199      1.1  jmcneill /* LCDIF_PIXEL */
    200      1.1  jmcneill #define IMX8MQ_CLK_LCDIF_PIXEL		128
    201      1.1  jmcneill /* SAI1~6 */
    202      1.1  jmcneill #define IMX8MQ_CLK_SAI1			129
    203      1.1  jmcneill 
    204      1.1  jmcneill #define IMX8MQ_CLK_SAI2			130
    205      1.1  jmcneill 
    206      1.1  jmcneill #define IMX8MQ_CLK_SAI3			131
    207      1.1  jmcneill 
    208      1.1  jmcneill #define IMX8MQ_CLK_SAI4			132
    209      1.1  jmcneill 
    210      1.1  jmcneill #define IMX8MQ_CLK_SAI5			133
    211      1.1  jmcneill 
    212      1.1  jmcneill #define IMX8MQ_CLK_SAI6			134
    213      1.1  jmcneill /* SPDIF1 */
    214      1.1  jmcneill #define IMX8MQ_CLK_SPDIF1		135
    215      1.1  jmcneill /* SPDIF2 */
    216      1.1  jmcneill #define IMX8MQ_CLK_SPDIF2		136
    217      1.1  jmcneill /* ENET_REF */
    218      1.1  jmcneill #define IMX8MQ_CLK_ENET_REF		137
    219      1.1  jmcneill /* ENET_TIMER */
    220      1.1  jmcneill #define IMX8MQ_CLK_ENET_TIMER		138
    221      1.1  jmcneill /* ENET_PHY */
    222      1.1  jmcneill #define IMX8MQ_CLK_ENET_PHY_REF		139
    223      1.1  jmcneill /* NAND */
    224      1.1  jmcneill #define IMX8MQ_CLK_NAND			140
    225      1.1  jmcneill /* QSPI */
    226      1.1  jmcneill #define IMX8MQ_CLK_QSPI			141
    227      1.1  jmcneill /* USDHC1 */
    228      1.1  jmcneill #define IMX8MQ_CLK_USDHC1		142
    229      1.1  jmcneill /* USDHC2 */
    230      1.1  jmcneill #define IMX8MQ_CLK_USDHC2		143
    231      1.1  jmcneill /* I2C1 */
    232      1.1  jmcneill #define IMX8MQ_CLK_I2C1			144
    233      1.1  jmcneill /* I2C2 */
    234      1.1  jmcneill #define IMX8MQ_CLK_I2C2			145
    235      1.1  jmcneill /* I2C3 */
    236      1.1  jmcneill #define IMX8MQ_CLK_I2C3			146
    237      1.1  jmcneill /* I2C4 */
    238      1.1  jmcneill #define IMX8MQ_CLK_I2C4			147
    239      1.1  jmcneill /* UART1 */
    240      1.1  jmcneill #define IMX8MQ_CLK_UART1		148
    241      1.1  jmcneill /* UART2 */
    242      1.1  jmcneill #define IMX8MQ_CLK_UART2		149
    243      1.1  jmcneill /* UART3 */
    244      1.1  jmcneill #define IMX8MQ_CLK_UART3		150
    245      1.1  jmcneill /* UART4 */
    246      1.1  jmcneill #define IMX8MQ_CLK_UART4		151
    247      1.1  jmcneill /* USB_CORE_REF */
    248      1.1  jmcneill #define IMX8MQ_CLK_USB_CORE_REF		152
    249      1.1  jmcneill /* USB_PHY_REF */
    250      1.1  jmcneill #define IMX8MQ_CLK_USB_PHY_REF		153
    251      1.1  jmcneill /* ECSPI1 */
    252      1.1  jmcneill #define IMX8MQ_CLK_ECSPI1		154
    253      1.1  jmcneill /* ECSPI2 */
    254      1.1  jmcneill #define IMX8MQ_CLK_ECSPI2		155
    255      1.1  jmcneill /* PWM1 */
    256      1.1  jmcneill #define IMX8MQ_CLK_PWM1			156
    257      1.1  jmcneill /* PWM2 */
    258      1.1  jmcneill #define IMX8MQ_CLK_PWM2			157
    259      1.1  jmcneill /* PWM3 */
    260      1.1  jmcneill #define IMX8MQ_CLK_PWM3			158
    261      1.1  jmcneill /* PWM4 */
    262      1.1  jmcneill #define IMX8MQ_CLK_PWM4			159
    263      1.1  jmcneill /* GPT1 */
    264      1.1  jmcneill #define IMX8MQ_CLK_GPT1			160
    265      1.1  jmcneill /* WDOG */
    266      1.1  jmcneill #define IMX8MQ_CLK_WDOG			161
    267      1.1  jmcneill /* WRCLK */
    268      1.1  jmcneill #define IMX8MQ_CLK_WRCLK		162
    269      1.1  jmcneill /* DSI_CORE */
    270      1.1  jmcneill #define IMX8MQ_CLK_DSI_CORE		163
    271      1.1  jmcneill /* DSI_PHY */
    272      1.1  jmcneill #define IMX8MQ_CLK_DSI_PHY_REF		164
    273      1.1  jmcneill /* DSI_DBI */
    274      1.1  jmcneill #define IMX8MQ_CLK_DSI_DBI		165
    275      1.1  jmcneill /*DSI_ESC */
    276      1.1  jmcneill #define IMX8MQ_CLK_DSI_ESC		166
    277      1.1  jmcneill /* CSI1_CORE */
    278      1.1  jmcneill #define IMX8MQ_CLK_CSI1_CORE		167
    279      1.1  jmcneill /* CSI1_PHY */
    280      1.1  jmcneill #define IMX8MQ_CLK_CSI1_PHY_REF		168
    281      1.1  jmcneill /* CSI_ESC */
    282      1.1  jmcneill #define IMX8MQ_CLK_CSI1_ESC		169
    283      1.1  jmcneill /* CSI2_CORE */
    284      1.1  jmcneill #define IMX8MQ_CLK_CSI2_CORE		170
    285      1.1  jmcneill /* CSI2_PHY */
    286      1.1  jmcneill #define IMX8MQ_CLK_CSI2_PHY_REF		171
    287      1.1  jmcneill /* CSI2_ESC */
    288      1.1  jmcneill #define IMX8MQ_CLK_CSI2_ESC		172
    289      1.1  jmcneill /* PCIE2_CTRL */
    290      1.1  jmcneill #define IMX8MQ_CLK_PCIE2_CTRL		173
    291      1.1  jmcneill /* PCIE2_PHY */
    292      1.1  jmcneill #define IMX8MQ_CLK_PCIE2_PHY		174
    293      1.1  jmcneill /* PCIE2_AUX */
    294      1.1  jmcneill #define IMX8MQ_CLK_PCIE2_AUX		175
    295      1.1  jmcneill /* ECSPI3 */
    296      1.1  jmcneill #define IMX8MQ_CLK_ECSPI3		176
    297      1.1  jmcneill 
    298      1.1  jmcneill /* CCGR clocks */
    299      1.1  jmcneill #define IMX8MQ_CLK_A53_ROOT			177
    300      1.1  jmcneill #define IMX8MQ_CLK_DRAM_ROOT			178
    301      1.1  jmcneill #define IMX8MQ_CLK_ECSPI1_ROOT			179
    302      1.1  jmcneill #define IMX8MQ_CLK_ECSPI2_ROOT			180
    303      1.1  jmcneill #define IMX8MQ_CLK_ECSPI3_ROOT			181
    304      1.1  jmcneill #define IMX8MQ_CLK_ENET1_ROOT			182
    305      1.1  jmcneill #define IMX8MQ_CLK_GPT1_ROOT			183
    306      1.1  jmcneill #define IMX8MQ_CLK_I2C1_ROOT			184
    307      1.1  jmcneill #define IMX8MQ_CLK_I2C2_ROOT			185
    308      1.1  jmcneill #define IMX8MQ_CLK_I2C3_ROOT			186
    309      1.1  jmcneill #define IMX8MQ_CLK_I2C4_ROOT			187
    310      1.1  jmcneill #define IMX8MQ_CLK_M4_ROOT			188
    311      1.1  jmcneill #define IMX8MQ_CLK_PCIE1_ROOT			189
    312      1.1  jmcneill #define IMX8MQ_CLK_PCIE2_ROOT			190
    313      1.1  jmcneill #define IMX8MQ_CLK_PWM1_ROOT			191
    314      1.1  jmcneill #define IMX8MQ_CLK_PWM2_ROOT			192
    315      1.1  jmcneill #define IMX8MQ_CLK_PWM3_ROOT			193
    316      1.1  jmcneill #define IMX8MQ_CLK_PWM4_ROOT			194
    317      1.1  jmcneill #define IMX8MQ_CLK_QSPI_ROOT			195
    318      1.1  jmcneill #define IMX8MQ_CLK_SAI1_ROOT			196
    319      1.1  jmcneill #define IMX8MQ_CLK_SAI2_ROOT			197
    320      1.1  jmcneill #define IMX8MQ_CLK_SAI3_ROOT			198
    321      1.1  jmcneill #define IMX8MQ_CLK_SAI4_ROOT			199
    322      1.1  jmcneill #define IMX8MQ_CLK_SAI5_ROOT			200
    323      1.1  jmcneill #define IMX8MQ_CLK_SAI6_ROOT			201
    324      1.1  jmcneill #define IMX8MQ_CLK_UART1_ROOT			202
    325      1.1  jmcneill #define IMX8MQ_CLK_UART2_ROOT			203
    326      1.1  jmcneill #define IMX8MQ_CLK_UART3_ROOT			204
    327      1.1  jmcneill #define IMX8MQ_CLK_UART4_ROOT			205
    328      1.1  jmcneill #define IMX8MQ_CLK_USB1_CTRL_ROOT		206
    329      1.1  jmcneill #define IMX8MQ_CLK_USB2_CTRL_ROOT		207
    330      1.1  jmcneill #define IMX8MQ_CLK_USB1_PHY_ROOT		208
    331      1.1  jmcneill #define IMX8MQ_CLK_USB2_PHY_ROOT		209
    332      1.1  jmcneill #define IMX8MQ_CLK_USDHC1_ROOT			210
    333      1.1  jmcneill #define IMX8MQ_CLK_USDHC2_ROOT			211
    334      1.1  jmcneill #define IMX8MQ_CLK_WDOG1_ROOT			212
    335      1.1  jmcneill #define IMX8MQ_CLK_WDOG2_ROOT			213
    336      1.1  jmcneill #define IMX8MQ_CLK_WDOG3_ROOT			214
    337      1.1  jmcneill #define IMX8MQ_CLK_GPU_ROOT			215
    338      1.1  jmcneill #define IMX8MQ_CLK_HEVC_ROOT			216
    339      1.1  jmcneill #define IMX8MQ_CLK_AVC_ROOT			217
    340      1.1  jmcneill #define IMX8MQ_CLK_VP9_ROOT			218
    341      1.1  jmcneill #define IMX8MQ_CLK_HEVC_INTER_ROOT		219
    342      1.1  jmcneill #define IMX8MQ_CLK_DISP_ROOT			220
    343      1.1  jmcneill #define IMX8MQ_CLK_HDMI_ROOT			221
    344      1.1  jmcneill #define IMX8MQ_CLK_HDMI_PHY_ROOT		222
    345      1.1  jmcneill #define IMX8MQ_CLK_VPU_DEC_ROOT			223
    346      1.1  jmcneill #define IMX8MQ_CLK_CSI1_ROOT			224
    347      1.1  jmcneill #define IMX8MQ_CLK_CSI2_ROOT			225
    348      1.1  jmcneill #define IMX8MQ_CLK_RAWNAND_ROOT			226
    349      1.1  jmcneill #define IMX8MQ_CLK_SDMA1_ROOT			227
    350      1.1  jmcneill #define IMX8MQ_CLK_SDMA2_ROOT			228
    351      1.1  jmcneill #define IMX8MQ_CLK_VPU_G1_ROOT			229
    352      1.1  jmcneill #define IMX8MQ_CLK_VPU_G2_ROOT			230
    353      1.1  jmcneill 
    354      1.1  jmcneill /* SCCG PLL GATE */
    355      1.1  jmcneill #define IMX8MQ_SYS1_PLL_OUT			231
    356      1.1  jmcneill #define IMX8MQ_SYS2_PLL_OUT			232
    357      1.1  jmcneill #define IMX8MQ_SYS3_PLL_OUT			233
    358      1.1  jmcneill #define IMX8MQ_DRAM_PLL_OUT			234
    359      1.1  jmcneill 
    360      1.1  jmcneill #define IMX8MQ_GPT_3M_CLK			235
    361      1.1  jmcneill 
    362      1.1  jmcneill #define IMX8MQ_CLK_IPG_ROOT			236
    363      1.1  jmcneill #define IMX8MQ_CLK_IPG_AUDIO_ROOT		237
    364      1.1  jmcneill #define IMX8MQ_CLK_SAI1_IPG			238
    365      1.1  jmcneill #define IMX8MQ_CLK_SAI2_IPG			239
    366      1.1  jmcneill #define IMX8MQ_CLK_SAI3_IPG			240
    367      1.1  jmcneill #define IMX8MQ_CLK_SAI4_IPG			241
    368      1.1  jmcneill #define IMX8MQ_CLK_SAI5_IPG			242
    369      1.1  jmcneill #define IMX8MQ_CLK_SAI6_IPG			243
    370      1.1  jmcneill 
    371      1.1  jmcneill /* DSI AHB/IPG clocks */
    372      1.1  jmcneill /* rxesc clock */
    373      1.1  jmcneill #define IMX8MQ_CLK_DSI_AHB			244
    374      1.1  jmcneill /* txesc clock */
    375      1.1  jmcneill #define IMX8MQ_CLK_DSI_IPG_DIV                  245
    376      1.1  jmcneill 
    377      1.1  jmcneill #define IMX8MQ_CLK_TMU_ROOT			246
    378      1.1  jmcneill 
    379      1.1  jmcneill /* Display root clocks */
    380      1.1  jmcneill #define IMX8MQ_CLK_DISP_AXI_ROOT		247
    381      1.1  jmcneill #define IMX8MQ_CLK_DISP_APB_ROOT		248
    382      1.1  jmcneill #define IMX8MQ_CLK_DISP_RTRM_ROOT		249
    383      1.1  jmcneill 
    384      1.1  jmcneill #define IMX8MQ_CLK_OCOTP_ROOT			250
    385      1.1  jmcneill 
    386      1.1  jmcneill #define IMX8MQ_CLK_DRAM_ALT_ROOT		251
    387      1.1  jmcneill #define IMX8MQ_CLK_DRAM_CORE			252
    388      1.1  jmcneill 
    389      1.1  jmcneill #define IMX8MQ_CLK_MU_ROOT			253
    390      1.1  jmcneill #define IMX8MQ_VIDEO2_PLL_OUT			254
    391      1.1  jmcneill 
    392      1.1  jmcneill #define IMX8MQ_CLK_CLKO2			255
    393      1.1  jmcneill 
    394      1.1  jmcneill #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	256
    395      1.1  jmcneill 
    396      1.1  jmcneill #define IMX8MQ_CLK_CLKO1			257
    397      1.1  jmcneill #define IMX8MQ_CLK_ARM				258
    398      1.1  jmcneill 
    399      1.1  jmcneill #define IMX8MQ_CLK_GPIO1_ROOT			259
    400      1.1  jmcneill #define IMX8MQ_CLK_GPIO2_ROOT			260
    401      1.1  jmcneill #define IMX8MQ_CLK_GPIO3_ROOT			261
    402      1.1  jmcneill #define IMX8MQ_CLK_GPIO4_ROOT			262
    403      1.1  jmcneill #define IMX8MQ_CLK_GPIO5_ROOT			263
    404      1.1  jmcneill 
    405  1.1.1.2     skrll #define IMX8MQ_CLK_SNVS_ROOT			264
    406  1.1.1.2     skrll #define IMX8MQ_CLK_GIC				265
    407  1.1.1.2     skrll 
    408  1.1.1.2     skrll #define IMX8MQ_VIDEO2_PLL1_REF_SEL		266
    409  1.1.1.2     skrll 
    410  1.1.1.3  jmcneill #define IMX8MQ_CLK_GPU_CORE			285
    411  1.1.1.3  jmcneill #define IMX8MQ_CLK_GPU_SHADER			286
    412  1.1.1.3  jmcneill #define IMX8MQ_CLK_M4_CORE			287
    413  1.1.1.3  jmcneill #define IMX8MQ_CLK_VPU_CORE			288
    414  1.1.1.2     skrll 
    415  1.1.1.3  jmcneill #define IMX8MQ_CLK_A53_CORE			289
    416  1.1.1.3  jmcneill 
    417  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
    418  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
    419  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
    420  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
    421  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
    422  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
    423  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
    424  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
    425  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
    426  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
    427  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
    428  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_SEL			301
    429  1.1.1.3  jmcneill #define IMX8MQ_CLK_MON_CLK2_OUT			302
    430  1.1.1.3  jmcneill 
    431  1.1.1.3  jmcneill #define IMX8MQ_CLK_END				303
    432  1.1.1.2     skrll 
    433      1.1  jmcneill #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
    434