ingenic,jz4760-cgu.h revision 1.1.1.1 
1/*	$NetBSD: ingenic,jz4760-cgu.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0 */
4/*
5 * This header provides clock numbers for the ingenic,jz4760-cgu DT binding.
6 */
7
8#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
9#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
10
11#define JZ4760_CLK_EXT		0
12#define JZ4760_CLK_OSC32K	1
13#define JZ4760_CLK_PLL0		2
14#define JZ4760_CLK_PLL0_HALF	3
15#define JZ4760_CLK_PLL1		4
16#define JZ4760_CLK_CCLK		5
17#define JZ4760_CLK_HCLK		6
18#define JZ4760_CLK_SCLK		7
19#define JZ4760_CLK_H2CLK	8
20#define JZ4760_CLK_MCLK		9
21#define JZ4760_CLK_PCLK		10
22#define JZ4760_CLK_MMC_MUX	11
23#define JZ4760_CLK_MMC0		12
24#define JZ4760_CLK_MMC1		13
25#define JZ4760_CLK_MMC2		14
26#define JZ4760_CLK_CIM		15
27#define JZ4760_CLK_UHC		16
28#define JZ4760_CLK_GPU		17
29#define JZ4760_CLK_GPS		18
30#define JZ4760_CLK_SSI_MUX	19
31#define JZ4760_CLK_PCM		20
32#define JZ4760_CLK_I2S		21
33#define JZ4760_CLK_OTG		22
34#define JZ4760_CLK_SSI0		23
35#define JZ4760_CLK_SSI1		24
36#define JZ4760_CLK_SSI2		25
37#define JZ4760_CLK_DMA		26
38#define JZ4760_CLK_I2C0		27
39#define JZ4760_CLK_I2C1		28
40#define JZ4760_CLK_UART0	29
41#define JZ4760_CLK_UART1	30
42#define JZ4760_CLK_UART2	31
43#define JZ4760_CLK_UART3	32
44#define JZ4760_CLK_IPU		33
45#define JZ4760_CLK_ADC		34
46#define JZ4760_CLK_AIC		35
47#define JZ4760_CLK_VPU		36
48#define JZ4760_CLK_UHC_PHY	37
49#define JZ4760_CLK_OTG_PHY	38
50#define JZ4760_CLK_EXT512	39
51#define JZ4760_CLK_RTC		40
52#define JZ4760_CLK_LPCLK_DIV	41
53#define JZ4760_CLK_TVE		42
54#define JZ4760_CLK_LPCLK	43
55#define JZ4760_CLK_MDMA		44
56#define JZ4760_CLK_BDMA		45
57
58#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */
59