11.1Sskrll/* $NetBSD: ingenic,jz4740-cgu.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sskrll/* 51.1Sskrll * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. 61.1Sskrll * 71.1Sskrll * They are roughly ordered as: 81.1Sskrll * - external clocks 91.1Sskrll * - PLLs 101.1Sskrll * - muxes/dividers in the order they appear in the jz4740 programmers manual 111.1Sskrll * - gates in order of their bit in the CLKGR* registers 121.1Sskrll */ 131.1Sskrll 141.1Sskrll#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 151.1Sskrll#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 161.1Sskrll 171.1Sskrll#define JZ4740_CLK_EXT 0 181.1Sskrll#define JZ4740_CLK_RTC 1 191.1Sskrll#define JZ4740_CLK_PLL 2 201.1Sskrll#define JZ4740_CLK_PLL_HALF 3 211.1Sskrll#define JZ4740_CLK_CCLK 4 221.1Sskrll#define JZ4740_CLK_HCLK 5 231.1Sskrll#define JZ4740_CLK_PCLK 6 241.1Sskrll#define JZ4740_CLK_MCLK 7 251.1Sskrll#define JZ4740_CLK_LCD 8 261.1Sskrll#define JZ4740_CLK_LCD_PCLK 9 271.1Sskrll#define JZ4740_CLK_I2S 10 281.1Sskrll#define JZ4740_CLK_SPI 11 291.1Sskrll#define JZ4740_CLK_MMC 12 301.1Sskrll#define JZ4740_CLK_UHC 13 311.1Sskrll#define JZ4740_CLK_UDC 14 321.1Sskrll#define JZ4740_CLK_UART0 15 331.1Sskrll#define JZ4740_CLK_UART1 16 341.1Sskrll#define JZ4740_CLK_DMA 17 351.1Sskrll#define JZ4740_CLK_IPU 18 361.1Sskrll#define JZ4740_CLK_ADC 19 371.1Sskrll#define JZ4740_CLK_I2C 20 381.1Sskrll#define JZ4740_CLK_AIC 21 391.1Sskrll#define JZ4740_CLK_TCU 22 401.1Sskrll 411.1Sskrll#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ 42