11.1Sskrll/* $NetBSD: ingenic,jz4755-cgu.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 41.1Sskrll/* 51.1Sskrll * This header provides clock numbers for the ingenic,jz4755-cgu DT binding. 61.1Sskrll */ 71.1Sskrll 81.1Sskrll#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ 91.1Sskrll#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ 101.1Sskrll 111.1Sskrll#define JZ4755_CLK_EXT 0 121.1Sskrll#define JZ4755_CLK_OSC32K 1 131.1Sskrll#define JZ4755_CLK_PLL 2 141.1Sskrll#define JZ4755_CLK_PLL_HALF 3 151.1Sskrll#define JZ4755_CLK_EXT_HALF 4 161.1Sskrll#define JZ4755_CLK_CCLK 5 171.1Sskrll#define JZ4755_CLK_H0CLK 6 181.1Sskrll#define JZ4755_CLK_PCLK 7 191.1Sskrll#define JZ4755_CLK_MCLK 8 201.1Sskrll#define JZ4755_CLK_H1CLK 9 211.1Sskrll#define JZ4755_CLK_UDC 10 221.1Sskrll#define JZ4755_CLK_LCD 11 231.1Sskrll#define JZ4755_CLK_UART0 12 241.1Sskrll#define JZ4755_CLK_UART1 13 251.1Sskrll#define JZ4755_CLK_UART2 14 261.1Sskrll#define JZ4755_CLK_DMA 15 271.1Sskrll#define JZ4755_CLK_MMC 16 281.1Sskrll#define JZ4755_CLK_MMC0 17 291.1Sskrll#define JZ4755_CLK_MMC1 18 301.1Sskrll#define JZ4755_CLK_EXT512 19 311.1Sskrll#define JZ4755_CLK_RTC 20 321.1Sskrll#define JZ4755_CLK_UDC_PHY 21 331.1Sskrll#define JZ4755_CLK_I2S 22 341.1Sskrll#define JZ4755_CLK_SPI 23 351.1Sskrll#define JZ4755_CLK_AIC 24 361.1Sskrll#define JZ4755_CLK_ADC 25 371.1Sskrll#define JZ4755_CLK_TCU 26 381.1Sskrll#define JZ4755_CLK_BCH 27 391.1Sskrll#define JZ4755_CLK_I2C 28 401.1Sskrll#define JZ4755_CLK_TVE 29 411.1Sskrll#define JZ4755_CLK_CIM 30 421.1Sskrll#define JZ4755_CLK_AUX_CPU 31 431.1Sskrll#define JZ4755_CLK_AHB1 32 441.1Sskrll#define JZ4755_CLK_IDCT 33 451.1Sskrll#define JZ4755_CLK_DB 34 461.1Sskrll#define JZ4755_CLK_ME 35 471.1Sskrll#define JZ4755_CLK_MC 36 481.1Sskrll#define JZ4755_CLK_TSSI 37 491.1Sskrll#define JZ4755_CLK_IPU 38 501.1Sskrll 511.1Sskrll#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */ 52