intel,lgm-clk.h revision 1.1.1.1 
1/*	$NetBSD: intel,lgm-clk.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4/*
5 * Copyright (C) 2020 Intel Corporation.
6 * Lei Chuanhua <Chuanhua.lei@intel.com>
7 * Zhu Yixin <Yixin.zhu@intel.com>
8 */
9#ifndef __INTEL_LGM_CLK_H
10#define __INTEL_LGM_CLK_H
11
12/* PLL clocks */
13#define LGM_CLK_OSC		1
14#define LGM_CLK_PLLPP		2
15#define LGM_CLK_PLL2		3
16#define LGM_CLK_PLL0CZ		4
17#define LGM_CLK_PLL0B		5
18#define LGM_CLK_PLL1		6
19#define LGM_CLK_LJPLL3		7
20#define LGM_CLK_LJPLL4		8
21#define LGM_CLK_PLL0CM0		9
22#define LGM_CLK_PLL0CM1		10
23
24/* clocks from PLLs */
25
26/* ROPLL clocks */
27#define LGM_CLK_PP_HW		15
28#define LGM_CLK_PP_UC		16
29#define LGM_CLK_PP_FXD		17
30#define LGM_CLK_PP_TBM		18
31
32/* PLL2 clocks */
33#define LGM_CLK_DDR		20
34
35/* PLL0CZ */
36#define LGM_CLK_CM		25
37#define LGM_CLK_IC		26
38#define LGM_CLK_SDXC3		27
39
40/* PLL0B */
41#define LGM_CLK_NGI		30
42#define LGM_CLK_NOC4		31
43#define LGM_CLK_SW		32
44#define LGM_CLK_QSPI		33
45#define LGM_CLK_CQEM		LGM_CLK_SW
46#define LGM_CLK_EMMC5		LGM_CLK_NOC4
47
48/* PLL1 */
49#define LGM_CLK_CT		35
50#define LGM_CLK_DSP		36
51#define LGM_CLK_VIF		37
52
53/* LJPLL3 */
54#define LGM_CLK_CML		40
55#define LGM_CLK_SERDES		41
56#define LGM_CLK_POOL		42
57#define LGM_CLK_PTP		43
58
59/* LJPLL4 */
60#define LGM_CLK_PCIE		45
61#define LGM_CLK_SATA		LGM_CLK_PCIE
62
63/* PLL0CM0 */
64#define LGM_CLK_CPU0		50
65
66/* PLL0CM1 */
67#define LGM_CLK_CPU1		55
68
69/* Miscellaneous clocks */
70#define LGM_CLK_EMMC4		60
71#define LGM_CLK_SDXC2		61
72#define LGM_CLK_EMMC		62
73#define LGM_CLK_SDXC		63
74#define LGM_CLK_SLIC		64
75#define LGM_CLK_DCL		65
76#define LGM_CLK_DOCSIS		66
77#define LGM_CLK_PCM		67
78#define LGM_CLK_DDR_PHY		68
79#define LGM_CLK_PONDEF		69
80#define LGM_CLK_PL25M		70
81#define LGM_CLK_PL10M		71
82#define LGM_CLK_PL1544K		72
83#define LGM_CLK_PL2048K		73
84#define LGM_CLK_PL8K		74
85#define LGM_CLK_PON_NTR		75
86#define LGM_CLK_SYNC0		76
87#define LGM_CLK_SYNC1		77
88#define LGM_CLK_PROGDIV		78
89#define LGM_CLK_OD0		79
90#define LGM_CLK_OD1		80
91#define LGM_CLK_CBPHY0		81
92#define LGM_CLK_CBPHY1		82
93#define LGM_CLK_CBPHY2		83
94#define LGM_CLK_CBPHY3		84
95
96/* Gate clocks */
97/* Gate CLK0 */
98#define LGM_GCLK_C55		100
99#define LGM_GCLK_QSPI		101
100#define LGM_GCLK_EIP197		102
101#define LGM_GCLK_VAULT		103
102#define LGM_GCLK_TOE		104
103#define LGM_GCLK_SDXC		105
104#define LGM_GCLK_EMMC		106
105#define LGM_GCLK_SPI_DBG	107
106#define LGM_GCLK_DMA3		108
107
108/* Gate CLK1 */
109#define LGM_GCLK_DMA0		120
110#define LGM_GCLK_LEDC0		121
111#define LGM_GCLK_LEDC1		122
112#define LGM_GCLK_I2S0		123
113#define LGM_GCLK_I2S1		124
114#define LGM_GCLK_EBU		125
115#define LGM_GCLK_PWM		126
116#define LGM_GCLK_I2C0		127
117#define LGM_GCLK_I2C1		128
118#define LGM_GCLK_I2C2		129
119#define LGM_GCLK_I2C3		130
120#define LGM_GCLK_SSC0		131
121#define LGM_GCLK_SSC1		132
122#define LGM_GCLK_SSC2		133
123#define LGM_GCLK_SSC3		134
124#define LGM_GCLK_GPTC0		135
125#define LGM_GCLK_GPTC1		136
126#define LGM_GCLK_GPTC2		137
127#define LGM_GCLK_GPTC3		138
128#define LGM_GCLK_ASC0		139
129#define LGM_GCLK_ASC1		140
130#define LGM_GCLK_ASC2		141
131#define LGM_GCLK_ASC3		142
132#define LGM_GCLK_PCM0		143
133#define LGM_GCLK_PCM1		144
134#define LGM_GCLK_PCM2		145
135
136/* Gate CLK2 */
137#define LGM_GCLK_PCIE10		150
138#define LGM_GCLK_PCIE11		151
139#define LGM_GCLK_PCIE30		152
140#define LGM_GCLK_PCIE31		153
141#define LGM_GCLK_PCIE20		154
142#define LGM_GCLK_PCIE21		155
143#define LGM_GCLK_PCIE40		156
144#define LGM_GCLK_PCIE41		157
145#define LGM_GCLK_XPCS0		158
146#define LGM_GCLK_XPCS1		159
147#define LGM_GCLK_XPCS2		160
148#define LGM_GCLK_XPCS3		161
149#define LGM_GCLK_SATA0		162
150#define LGM_GCLK_SATA1		163
151#define LGM_GCLK_SATA2		164
152#define LGM_GCLK_SATA3		165
153
154/* Gate CLK3 */
155#define LGM_GCLK_ARCEM4		170
156#define LGM_GCLK_IDMAR1		171
157#define LGM_GCLK_IDMAT0		172
158#define LGM_GCLK_IDMAT1		173
159#define LGM_GCLK_IDMAT2		174
160#define LGM_GCLK_PPV4		175
161#define LGM_GCLK_GSWIPO		176
162#define LGM_GCLK_CQEM		177
163#define LGM_GCLK_XPCS5		178
164#define LGM_GCLK_USB1		179
165#define LGM_GCLK_USB2		180
166
167#endif /* __INTEL_LGM_CLK_H */
168