1 1.1 jmcneill /* $NetBSD: lpc18xx-ccu.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* 4 1.1 jmcneill * Copyright (c) 2015 Joachim Eastwood <manabian (at) gmail.com> 5 1.1 jmcneill * 6 1.1 jmcneill * This code is released using a dual license strategy: BSD/GPL 7 1.1 jmcneill * You can choose the licence that better fits your requirements. 8 1.1 jmcneill * 9 1.1 jmcneill * Released under the terms of 3-clause BSD License 10 1.1 jmcneill * Released under the terms of GNU General Public License Version 2.0 11 1.1 jmcneill * 12 1.1 jmcneill */ 13 1.1 jmcneill 14 1.1 jmcneill /* Clock Control Unit 1 (CCU1) clock offsets */ 15 1.1 jmcneill #define CLK_APB3_BUS 0x100 16 1.1 jmcneill #define CLK_APB3_I2C1 0x108 17 1.1 jmcneill #define CLK_APB3_DAC 0x110 18 1.1 jmcneill #define CLK_APB3_ADC0 0x118 19 1.1 jmcneill #define CLK_APB3_ADC1 0x120 20 1.1 jmcneill #define CLK_APB3_CAN0 0x128 21 1.1 jmcneill #define CLK_APB1_BUS 0x200 22 1.1 jmcneill #define CLK_APB1_MOTOCON_PWM 0x208 23 1.1 jmcneill #define CLK_APB1_I2C0 0x210 24 1.1 jmcneill #define CLK_APB1_I2S 0x218 25 1.1 jmcneill #define CLK_APB1_CAN1 0x220 26 1.1 jmcneill #define CLK_SPIFI 0x300 27 1.1 jmcneill #define CLK_CPU_BUS 0x400 28 1.1 jmcneill #define CLK_CPU_SPIFI 0x408 29 1.1 jmcneill #define CLK_CPU_GPIO 0x410 30 1.1 jmcneill #define CLK_CPU_LCD 0x418 31 1.1 jmcneill #define CLK_CPU_ETHERNET 0x420 32 1.1 jmcneill #define CLK_CPU_USB0 0x428 33 1.1 jmcneill #define CLK_CPU_EMC 0x430 34 1.1 jmcneill #define CLK_CPU_SDIO 0x438 35 1.1 jmcneill #define CLK_CPU_DMA 0x440 36 1.1 jmcneill #define CLK_CPU_CORE 0x448 37 1.1 jmcneill #define CLK_CPU_SCT 0x468 38 1.1 jmcneill #define CLK_CPU_USB1 0x470 39 1.1 jmcneill #define CLK_CPU_EMCDIV 0x478 40 1.1 jmcneill #define CLK_CPU_FLASHA 0x480 41 1.1 jmcneill #define CLK_CPU_FLASHB 0x488 42 1.1 jmcneill #define CLK_CPU_M0APP 0x490 43 1.1 jmcneill #define CLK_CPU_ADCHS 0x498 44 1.1 jmcneill #define CLK_CPU_EEPROM 0x4a0 45 1.1 jmcneill #define CLK_CPU_WWDT 0x500 46 1.1 jmcneill #define CLK_CPU_UART0 0x508 47 1.1 jmcneill #define CLK_CPU_UART1 0x510 48 1.1 jmcneill #define CLK_CPU_SSP0 0x518 49 1.1 jmcneill #define CLK_CPU_TIMER0 0x520 50 1.1 jmcneill #define CLK_CPU_TIMER1 0x528 51 1.1 jmcneill #define CLK_CPU_SCU 0x530 52 1.1 jmcneill #define CLK_CPU_CREG 0x538 53 1.1 jmcneill #define CLK_CPU_RITIMER 0x600 54 1.1 jmcneill #define CLK_CPU_UART2 0x608 55 1.1 jmcneill #define CLK_CPU_UART3 0x610 56 1.1 jmcneill #define CLK_CPU_TIMER2 0x618 57 1.1 jmcneill #define CLK_CPU_TIMER3 0x620 58 1.1 jmcneill #define CLK_CPU_SSP1 0x628 59 1.1 jmcneill #define CLK_CPU_QEI 0x630 60 1.1 jmcneill #define CLK_PERIPH_BUS 0x700 61 1.1 jmcneill #define CLK_PERIPH_CORE 0x710 62 1.1 jmcneill #define CLK_PERIPH_SGPIO 0x718 63 1.1 jmcneill #define CLK_USB0 0x800 64 1.1 jmcneill #define CLK_USB1 0x900 65 1.1 jmcneill #define CLK_SPI 0xA00 66 1.1 jmcneill #define CLK_ADCHS 0xB00 67 1.1 jmcneill 68 1.1 jmcneill /* Clock Control Unit 2 (CCU2) clock offsets */ 69 1.1 jmcneill #define CLK_AUDIO 0x100 70 1.1 jmcneill #define CLK_APB2_UART3 0x200 71 1.1 jmcneill #define CLK_APB2_UART2 0x300 72 1.1 jmcneill #define CLK_APB0_UART1 0x400 73 1.1 jmcneill #define CLK_APB0_UART0 0x500 74 1.1 jmcneill #define CLK_APB2_SSP1 0x600 75 1.1 jmcneill #define CLK_APB0_SSP0 0x700 76 1.1 jmcneill #define CLK_SDIO 0x800 77
Indexes created Mon Sep 29 21:09:56 GMT 2025