marvell,pxa1928.h revision 1.1.1.1.6.2
1 /* $NetBSD: marvell,pxa1928.h,v 1.1.1.1.6.2 2017/08/28 17:53:00 skrll Exp $ */ 2 3 #ifndef __DTS_MARVELL_PXA1928_CLOCK_H 4 #define __DTS_MARVELL_PXA1928_CLOCK_H 5 6 /* 7 * Clock ID values here correspond to the control register offset/4. 8 */ 9 10 /* apb peripherals */ 11 #define PXA1928_CLK_RTC 0x00 12 #define PXA1928_CLK_TWSI0 0x01 13 #define PXA1928_CLK_TWSI1 0x02 14 #define PXA1928_CLK_TWSI2 0x03 15 #define PXA1928_CLK_TWSI3 0x04 16 #define PXA1928_CLK_OWIRE 0x05 17 #define PXA1928_CLK_KPC 0x06 18 #define PXA1928_CLK_TB_ROTARY 0x07 19 #define PXA1928_CLK_SW_JTAG 0x08 20 #define PXA1928_CLK_TIMER1 0x09 21 #define PXA1928_CLK_UART0 0x0b 22 #define PXA1928_CLK_UART1 0x0c 23 #define PXA1928_CLK_UART2 0x0d 24 #define PXA1928_CLK_GPIO 0x0e 25 #define PXA1928_CLK_PWM0 0x0f 26 #define PXA1928_CLK_PWM1 0x10 27 #define PXA1928_CLK_PWM2 0x11 28 #define PXA1928_CLK_PWM3 0x12 29 #define PXA1928_CLK_SSP0 0x13 30 #define PXA1928_CLK_SSP1 0x14 31 #define PXA1928_CLK_SSP2 0x15 32 33 #define PXA1928_CLK_TWSI4 0x1f 34 #define PXA1928_CLK_TWSI5 0x20 35 #define PXA1928_CLK_UART3 0x22 36 #define PXA1928_CLK_THSENS_GLOB 0x24 37 #define PXA1928_CLK_THSENS_CPU 0x26 38 #define PXA1928_CLK_THSENS_VPU 0x27 39 #define PXA1928_CLK_THSENS_GC 0x28 40 #define PXA1928_APBC_NR_CLKS 0x30 41 42 43 /* axi peripherals */ 44 #define PXA1928_CLK_SDH0 0x15 45 #define PXA1928_CLK_SDH1 0x16 46 #define PXA1928_CLK_USB 0x17 47 #define PXA1928_CLK_NAND 0x18 48 #define PXA1928_CLK_DMA 0x19 49 50 #define PXA1928_CLK_SDH2 0x3a 51 #define PXA1928_CLK_SDH3 0x3b 52 #define PXA1928_CLK_HSIC 0x3e 53 #define PXA1928_CLK_SDH4 0x57 54 #define PXA1928_CLK_GC3D 0x5d 55 #define PXA1928_CLK_GC2D 0x5f 56 57 #define PXA1928_APMU_NR_CLKS 0x60 58 59 #endif 60
Indexes created Wed Oct 22 13:09:56 GMT 2025