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      1      1.1  jmcneill /*	$NetBSD: microchip,pic32-clock.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $	*/
      2      1.1  jmcneill 
      3  1.1.1.2     skrll /* SPDX-License-Identifier: GPL-2.0-only */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * Purna Chandra Mandal,<purna.mandal (at) microchip.com>
      6      1.1  jmcneill  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
      7      1.1  jmcneill  */
      8      1.1  jmcneill 
      9      1.1  jmcneill #ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
     10      1.1  jmcneill #define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
     11      1.1  jmcneill 
     12      1.1  jmcneill /* clock output indices */
     13      1.1  jmcneill #define POSCCLK		0
     14      1.1  jmcneill #define FRCCLK		1
     15      1.1  jmcneill #define BFRCCLK		2
     16      1.1  jmcneill #define LPRCCLK		3
     17      1.1  jmcneill #define SOSCCLK		4
     18      1.1  jmcneill #define FRCDIVCLK	5
     19      1.1  jmcneill #define PLLCLK		6
     20      1.1  jmcneill #define SCLK		7
     21      1.1  jmcneill #define PB1CLK		8
     22      1.1  jmcneill #define PB2CLK		9
     23      1.1  jmcneill #define PB3CLK		10
     24      1.1  jmcneill #define PB4CLK		11
     25      1.1  jmcneill #define PB5CLK		12
     26      1.1  jmcneill #define PB6CLK		13
     27      1.1  jmcneill #define PB7CLK		14
     28      1.1  jmcneill #define REF1CLK		15
     29      1.1  jmcneill #define REF2CLK		16
     30      1.1  jmcneill #define REF3CLK		17
     31      1.1  jmcneill #define REF4CLK		18
     32      1.1  jmcneill #define REF5CLK		19
     33      1.1  jmcneill #define UPLLCLK		20
     34      1.1  jmcneill #define MAXCLKS		21
     35      1.1  jmcneill 
     36      1.1  jmcneill #endif	/* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
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