mt8186-clk.h revision 1.1.1.1
1/* $NetBSD: mt8186-clk.h,v 1.1.1.1 2026/01/18 05:21:33 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 4/* 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_MT8186_H 10#define _DT_BINDINGS_CLK_MT8186_H 11 12/* MCUSYS */ 13 14#define CLK_MCU_ARMPLL_LL_SEL 0 15#define CLK_MCU_ARMPLL_BL_SEL 1 16#define CLK_MCU_ARMPLL_BUS_SEL 2 17#define CLK_MCU_NR_CLK 3 18 19/* TOPCKGEN */ 20 21#define CLK_TOP_AXI 0 22#define CLK_TOP_SCP 1 23#define CLK_TOP_MFG 2 24#define CLK_TOP_CAMTG 3 25#define CLK_TOP_CAMTG1 4 26#define CLK_TOP_CAMTG2 5 27#define CLK_TOP_CAMTG3 6 28#define CLK_TOP_CAMTG4 7 29#define CLK_TOP_CAMTG5 8 30#define CLK_TOP_CAMTG6 9 31#define CLK_TOP_UART 10 32#define CLK_TOP_SPI 11 33#define CLK_TOP_MSDC50_0_HCLK 12 34#define CLK_TOP_MSDC50_0 13 35#define CLK_TOP_MSDC30_1 14 36#define CLK_TOP_AUDIO 15 37#define CLK_TOP_AUD_INTBUS 16 38#define CLK_TOP_AUD_1 17 39#define CLK_TOP_AUD_2 18 40#define CLK_TOP_AUD_ENGEN1 19 41#define CLK_TOP_AUD_ENGEN2 20 42#define CLK_TOP_DISP_PWM 21 43#define CLK_TOP_SSPM 22 44#define CLK_TOP_DXCC 23 45#define CLK_TOP_USB_TOP 24 46#define CLK_TOP_SRCK 25 47#define CLK_TOP_SPM 26 48#define CLK_TOP_I2C 27 49#define CLK_TOP_PWM 28 50#define CLK_TOP_SENINF 29 51#define CLK_TOP_SENINF1 30 52#define CLK_TOP_SENINF2 31 53#define CLK_TOP_SENINF3 32 54#define CLK_TOP_AES_MSDCFDE 33 55#define CLK_TOP_PWRAP_ULPOSC 34 56#define CLK_TOP_CAMTM 35 57#define CLK_TOP_VENC 36 58#define CLK_TOP_CAM 37 59#define CLK_TOP_IMG1 38 60#define CLK_TOP_IPE 39 61#define CLK_TOP_DPMAIF 40 62#define CLK_TOP_VDEC 41 63#define CLK_TOP_DISP 42 64#define CLK_TOP_MDP 43 65#define CLK_TOP_AUDIO_H 44 66#define CLK_TOP_UFS 45 67#define CLK_TOP_AES_FDE 46 68#define CLK_TOP_AUDIODSP 47 69#define CLK_TOP_DVFSRC 48 70#define CLK_TOP_DSI_OCC 49 71#define CLK_TOP_SPMI_MST 50 72#define CLK_TOP_SPINOR 51 73#define CLK_TOP_NNA 52 74#define CLK_TOP_NNA1 53 75#define CLK_TOP_NNA2 54 76#define CLK_TOP_SSUSB_XHCI 55 77#define CLK_TOP_SSUSB_TOP_1P 56 78#define CLK_TOP_SSUSB_XHCI_1P 57 79#define CLK_TOP_WPE 58 80#define CLK_TOP_DPI 59 81#define CLK_TOP_U3_OCC_250M 60 82#define CLK_TOP_U3_OCC_500M 61 83#define CLK_TOP_ADSP_BUS 62 84#define CLK_TOP_APLL_I2S0_MCK_SEL 63 85#define CLK_TOP_APLL_I2S1_MCK_SEL 64 86#define CLK_TOP_APLL_I2S2_MCK_SEL 65 87#define CLK_TOP_APLL_I2S4_MCK_SEL 66 88#define CLK_TOP_APLL_TDMOUT_MCK_SEL 67 89#define CLK_TOP_MAINPLL_D2 68 90#define CLK_TOP_MAINPLL_D2_D2 69 91#define CLK_TOP_MAINPLL_D2_D4 70 92#define CLK_TOP_MAINPLL_D2_D16 71 93#define CLK_TOP_MAINPLL_D3 72 94#define CLK_TOP_MAINPLL_D3_D2 73 95#define CLK_TOP_MAINPLL_D3_D4 74 96#define CLK_TOP_MAINPLL_D5 75 97#define CLK_TOP_MAINPLL_D5_D2 76 98#define CLK_TOP_MAINPLL_D5_D4 77 99#define CLK_TOP_MAINPLL_D7 78 100#define CLK_TOP_MAINPLL_D7_D2 79 101#define CLK_TOP_MAINPLL_D7_D4 80 102#define CLK_TOP_UNIVPLL 81 103#define CLK_TOP_UNIVPLL_D2 82 104#define CLK_TOP_UNIVPLL_D2_D2 83 105#define CLK_TOP_UNIVPLL_D2_D4 84 106#define CLK_TOP_UNIVPLL_D3 85 107#define CLK_TOP_UNIVPLL_D3_D2 86 108#define CLK_TOP_UNIVPLL_D3_D4 87 109#define CLK_TOP_UNIVPLL_D3_D8 88 110#define CLK_TOP_UNIVPLL_D3_D32 89 111#define CLK_TOP_UNIVPLL_D5 90 112#define CLK_TOP_UNIVPLL_D5_D2 91 113#define CLK_TOP_UNIVPLL_D5_D4 92 114#define CLK_TOP_UNIVPLL_D7 93 115#define CLK_TOP_UNIVPLL_192M 94 116#define CLK_TOP_UNIVPLL_192M_D4 95 117#define CLK_TOP_UNIVPLL_192M_D8 96 118#define CLK_TOP_UNIVPLL_192M_D16 97 119#define CLK_TOP_UNIVPLL_192M_D32 98 120#define CLK_TOP_APLL1_D2 99 121#define CLK_TOP_APLL1_D4 100 122#define CLK_TOP_APLL1_D8 101 123#define CLK_TOP_APLL2_D2 102 124#define CLK_TOP_APLL2_D4 103 125#define CLK_TOP_APLL2_D8 104 126#define CLK_TOP_MMPLL_D2 105 127#define CLK_TOP_TVDPLL_D2 106 128#define CLK_TOP_TVDPLL_D4 107 129#define CLK_TOP_TVDPLL_D8 108 130#define CLK_TOP_TVDPLL_D16 109 131#define CLK_TOP_TVDPLL_D32 110 132#define CLK_TOP_MSDCPLL_D2 111 133#define CLK_TOP_ULPOSC1 112 134#define CLK_TOP_ULPOSC1_D2 113 135#define CLK_TOP_ULPOSC1_D4 114 136#define CLK_TOP_ULPOSC1_D8 115 137#define CLK_TOP_ULPOSC1_D10 116 138#define CLK_TOP_ULPOSC1_D16 117 139#define CLK_TOP_ULPOSC1_D32 118 140#define CLK_TOP_ADSPPLL_D2 119 141#define CLK_TOP_ADSPPLL_D4 120 142#define CLK_TOP_ADSPPLL_D8 121 143#define CLK_TOP_NNAPLL_D2 122 144#define CLK_TOP_NNAPLL_D4 123 145#define CLK_TOP_NNAPLL_D8 124 146#define CLK_TOP_NNA2PLL_D2 125 147#define CLK_TOP_NNA2PLL_D4 126 148#define CLK_TOP_NNA2PLL_D8 127 149#define CLK_TOP_F_BIST2FPC 128 150#define CLK_TOP_466M_FMEM 129 151#define CLK_TOP_MPLL 130 152#define CLK_TOP_APLL12_CK_DIV0 131 153#define CLK_TOP_APLL12_CK_DIV1 132 154#define CLK_TOP_APLL12_CK_DIV2 133 155#define CLK_TOP_APLL12_CK_DIV4 134 156#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135 157#define CLK_TOP_NR_CLK 136 158 159/* INFRACFG_AO */ 160 161#define CLK_INFRA_AO_PMIC_TMR 0 162#define CLK_INFRA_AO_PMIC_AP 1 163#define CLK_INFRA_AO_PMIC_MD 2 164#define CLK_INFRA_AO_PMIC_CONN 3 165#define CLK_INFRA_AO_SCP_CORE 4 166#define CLK_INFRA_AO_SEJ 5 167#define CLK_INFRA_AO_APXGPT 6 168#define CLK_INFRA_AO_ICUSB 7 169#define CLK_INFRA_AO_GCE 8 170#define CLK_INFRA_AO_THERM 9 171#define CLK_INFRA_AO_I2C_AP 10 172#define CLK_INFRA_AO_I2C_CCU 11 173#define CLK_INFRA_AO_I2C_SSPM 12 174#define CLK_INFRA_AO_I2C_RSV 13 175#define CLK_INFRA_AO_PWM_HCLK 14 176#define CLK_INFRA_AO_PWM1 15 177#define CLK_INFRA_AO_PWM2 16 178#define CLK_INFRA_AO_PWM3 17 179#define CLK_INFRA_AO_PWM4 18 180#define CLK_INFRA_AO_PWM5 19 181#define CLK_INFRA_AO_PWM 20 182#define CLK_INFRA_AO_UART0 21 183#define CLK_INFRA_AO_UART1 22 184#define CLK_INFRA_AO_UART2 23 185#define CLK_INFRA_AO_GCE_26M 24 186#define CLK_INFRA_AO_CQ_DMA_FPC 25 187#define CLK_INFRA_AO_BTIF 26 188#define CLK_INFRA_AO_SPI0 27 189#define CLK_INFRA_AO_MSDC0 28 190#define CLK_INFRA_AO_MSDCFDE 29 191#define CLK_INFRA_AO_MSDC1 30 192#define CLK_INFRA_AO_DVFSRC 31 193#define CLK_INFRA_AO_GCPU 32 194#define CLK_INFRA_AO_TRNG 33 195#define CLK_INFRA_AO_AUXADC 34 196#define CLK_INFRA_AO_CPUM 35 197#define CLK_INFRA_AO_CCIF1_AP 36 198#define CLK_INFRA_AO_CCIF1_MD 37 199#define CLK_INFRA_AO_AUXADC_MD 38 200#define CLK_INFRA_AO_AP_DMA 39 201#define CLK_INFRA_AO_XIU 40 202#define CLK_INFRA_AO_DEVICE_APC 41 203#define CLK_INFRA_AO_CCIF_AP 42 204#define CLK_INFRA_AO_DEBUGTOP 43 205#define CLK_INFRA_AO_AUDIO 44 206#define CLK_INFRA_AO_CCIF_MD 45 207#define CLK_INFRA_AO_DXCC_SEC_CORE 46 208#define CLK_INFRA_AO_DXCC_AO 47 209#define CLK_INFRA_AO_IMP_IIC 48 210#define CLK_INFRA_AO_DRAMC_F26M 49 211#define CLK_INFRA_AO_RG_PWM_FBCLK6 50 212#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51 213#define CLK_INFRA_AO_DISP_PWM 52 214#define CLK_INFRA_AO_CLDMA_BCLK 53 215#define CLK_INFRA_AO_AUDIO_26M_BCLK 54 216#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55 217#define CLK_INFRA_AO_SPI1 56 218#define CLK_INFRA_AO_I2C4 57 219#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58 220#define CLK_INFRA_AO_SPI2 59 221#define CLK_INFRA_AO_SPI3 60 222#define CLK_INFRA_AO_SSUSB_TOP_REF 61 223#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62 224#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63 225#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64 226#define CLK_INFRA_AO_SSPM 65 227#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66 228#define CLK_INFRA_AO_I2C5 67 229#define CLK_INFRA_AO_I2C5_ARBITER 68 230#define CLK_INFRA_AO_I2C5_IMM 69 231#define CLK_INFRA_AO_I2C1_ARBITER 70 232#define CLK_INFRA_AO_I2C1_IMM 71 233#define CLK_INFRA_AO_I2C2_ARBITER 72 234#define CLK_INFRA_AO_I2C2_IMM 73 235#define CLK_INFRA_AO_SPI4 74 236#define CLK_INFRA_AO_SPI5 75 237#define CLK_INFRA_AO_CQ_DMA 76 238#define CLK_INFRA_AO_BIST2FPC 77 239#define CLK_INFRA_AO_MSDC0_SELF 78 240#define CLK_INFRA_AO_SPINOR 79 241#define CLK_INFRA_AO_SSPM_26M_SELF 80 242#define CLK_INFRA_AO_SSPM_32K_SELF 81 243#define CLK_INFRA_AO_I2C6 82 244#define CLK_INFRA_AO_AP_MSDC0 83 245#define CLK_INFRA_AO_MD_MSDC0 84 246#define CLK_INFRA_AO_MSDC0_SRC 85 247#define CLK_INFRA_AO_MSDC1_SRC 86 248#define CLK_INFRA_AO_SEJ_F13M 87 249#define CLK_INFRA_AO_AES_TOP0_BCLK 88 250#define CLK_INFRA_AO_MCU_PM_BCLK 89 251#define CLK_INFRA_AO_CCIF2_AP 90 252#define CLK_INFRA_AO_CCIF2_MD 91 253#define CLK_INFRA_AO_CCIF3_AP 92 254#define CLK_INFRA_AO_CCIF3_MD 93 255#define CLK_INFRA_AO_FADSP_26M 94 256#define CLK_INFRA_AO_FADSP_32K 95 257#define CLK_INFRA_AO_CCIF4_AP 96 258#define CLK_INFRA_AO_CCIF4_MD 97 259#define CLK_INFRA_AO_FADSP 98 260#define CLK_INFRA_AO_FLASHIF_133M 99 261#define CLK_INFRA_AO_FLASHIF_66M 100 262#define CLK_INFRA_AO_NR_CLK 101 263 264/* APMIXEDSYS */ 265 266#define CLK_APMIXED_ARMPLL_LL 0 267#define CLK_APMIXED_ARMPLL_BL 1 268#define CLK_APMIXED_CCIPLL 2 269#define CLK_APMIXED_MAINPLL 3 270#define CLK_APMIXED_UNIV2PLL 4 271#define CLK_APMIXED_MSDCPLL 5 272#define CLK_APMIXED_MMPLL 6 273#define CLK_APMIXED_NNAPLL 7 274#define CLK_APMIXED_NNA2PLL 8 275#define CLK_APMIXED_ADSPPLL 9 276#define CLK_APMIXED_MFGPLL 10 277#define CLK_APMIXED_TVDPLL 11 278#define CLK_APMIXED_APLL1 12 279#define CLK_APMIXED_APLL2 13 280#define CLK_APMIXED_NR_CLK 14 281 282/* IMP_IIC_WRAP */ 283 284#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0 285#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1 286#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2 287#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3 288#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4 289#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5 290#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6 291#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7 292#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8 293#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9 294#define CLK_IMP_IIC_WRAP_NR_CLK 10 295 296/* MFGCFG */ 297 298#define CLK_MFG_BG3D 0 299#define CLK_MFG_NR_CLK 1 300 301/* MMSYS */ 302 303#define CLK_MM_DISP_MUTEX0 0 304#define CLK_MM_APB_MM_BUS 1 305#define CLK_MM_DISP_OVL0 2 306#define CLK_MM_DISP_RDMA0 3 307#define CLK_MM_DISP_OVL0_2L 4 308#define CLK_MM_DISP_WDMA0 5 309#define CLK_MM_DISP_RSZ0 6 310#define CLK_MM_DISP_AAL0 7 311#define CLK_MM_DISP_CCORR0 8 312#define CLK_MM_DISP_COLOR0 9 313#define CLK_MM_SMI_INFRA 10 314#define CLK_MM_DISP_DSC_WRAP0 11 315#define CLK_MM_DISP_GAMMA0 12 316#define CLK_MM_DISP_POSTMASK0 13 317#define CLK_MM_DISP_DITHER0 14 318#define CLK_MM_SMI_COMMON 15 319#define CLK_MM_DSI0 16 320#define CLK_MM_DISP_FAKE_ENG0 17 321#define CLK_MM_DISP_FAKE_ENG1 18 322#define CLK_MM_SMI_GALS 19 323#define CLK_MM_SMI_IOMMU 20 324#define CLK_MM_DISP_RDMA1 21 325#define CLK_MM_DISP_DPI 22 326#define CLK_MM_DSI0_DSI_CK_DOMAIN 23 327#define CLK_MM_DISP_26M 24 328#define CLK_MM_NR_CLK 25 329 330/* WPESYS */ 331 332#define CLK_WPE_CK_EN 0 333#define CLK_WPE_SMI_LARB8_CK_EN 1 334#define CLK_WPE_SYS_EVENT_TX_CK_EN 2 335#define CLK_WPE_SMI_LARB8_PCLK_EN 3 336#define CLK_WPE_NR_CLK 4 337 338/* IMGSYS1 */ 339 340#define CLK_IMG1_LARB9_IMG1 0 341#define CLK_IMG1_LARB10_IMG1 1 342#define CLK_IMG1_DIP 2 343#define CLK_IMG1_GALS_IMG1 3 344#define CLK_IMG1_NR_CLK 4 345 346/* IMGSYS2 */ 347 348#define CLK_IMG2_LARB9_IMG2 0 349#define CLK_IMG2_LARB10_IMG2 1 350#define CLK_IMG2_MFB 2 351#define CLK_IMG2_WPE 3 352#define CLK_IMG2_MSS 4 353#define CLK_IMG2_GALS_IMG2 5 354#define CLK_IMG2_NR_CLK 6 355 356/* VDECSYS */ 357 358#define CLK_VDEC_LARB1_CKEN 0 359#define CLK_VDEC_LAT_CKEN 1 360#define CLK_VDEC_LAT_ACTIVE 2 361#define CLK_VDEC_LAT_CKEN_ENG 3 362#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4 363#define CLK_VDEC_CKEN 5 364#define CLK_VDEC_ACTIVE 6 365#define CLK_VDEC_CKEN_ENG 7 366#define CLK_VDEC_NR_CLK 8 367 368/* VENCSYS */ 369 370#define CLK_VENC_CKE0_LARB 0 371#define CLK_VENC_CKE1_VENC 1 372#define CLK_VENC_CKE2_JPGENC 2 373#define CLK_VENC_CKE5_GALS 3 374#define CLK_VENC_NR_CLK 4 375 376/* CAMSYS */ 377 378#define CLK_CAM_LARB13 0 379#define CLK_CAM_DFP_VAD 1 380#define CLK_CAM_LARB14 2 381#define CLK_CAM 3 382#define CLK_CAMTG 4 383#define CLK_CAM_SENINF 5 384#define CLK_CAMSV1 6 385#define CLK_CAMSV2 7 386#define CLK_CAMSV3 8 387#define CLK_CAM_CCU0 9 388#define CLK_CAM_CCU1 10 389#define CLK_CAM_MRAW0 11 390#define CLK_CAM_FAKE_ENG 12 391#define CLK_CAM_CCU_GALS 13 392#define CLK_CAM2MM_GALS 14 393#define CLK_CAM_NR_CLK 15 394 395/* CAMSYS_RAWA */ 396 397#define CLK_CAM_RAWA_LARBX_RAWA 0 398#define CLK_CAM_RAWA 1 399#define CLK_CAM_RAWA_CAMTG_RAWA 2 400#define CLK_CAM_RAWA_NR_CLK 3 401 402/* CAMSYS_RAWB */ 403 404#define CLK_CAM_RAWB_LARBX_RAWB 0 405#define CLK_CAM_RAWB 1 406#define CLK_CAM_RAWB_CAMTG_RAWB 2 407#define CLK_CAM_RAWB_NR_CLK 3 408 409/* MDPSYS */ 410 411#define CLK_MDP_RDMA0 0 412#define CLK_MDP_TDSHP0 1 413#define CLK_MDP_IMG_DL_ASYNC0 2 414#define CLK_MDP_IMG_DL_ASYNC1 3 415#define CLK_MDP_DISP_RDMA 4 416#define CLK_MDP_HMS 5 417#define CLK_MDP_SMI0 6 418#define CLK_MDP_APB_BUS 7 419#define CLK_MDP_WROT0 8 420#define CLK_MDP_RSZ0 9 421#define CLK_MDP_HDR0 10 422#define CLK_MDP_MUTEX0 11 423#define CLK_MDP_WROT1 12 424#define CLK_MDP_RSZ1 13 425#define CLK_MDP_FAKE_ENG0 14 426#define CLK_MDP_AAL0 15 427#define CLK_MDP_DISP_WDMA 16 428#define CLK_MDP_COLOR 17 429#define CLK_MDP_IMG_DL_ASYNC2 18 430#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19 431#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20 432#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21 433#define CLK_MDP_NR_CLK 22 434 435/* IPESYS */ 436 437#define CLK_IPE_LARB19 0 438#define CLK_IPE_LARB20 1 439#define CLK_IPE_SMI_SUBCOM 2 440#define CLK_IPE_FD 3 441#define CLK_IPE_FE 4 442#define CLK_IPE_RSC 5 443#define CLK_IPE_DPE 6 444#define CLK_IPE_GALS_IPE 7 445#define CLK_IPE_NR_CLK 8 446 447#endif /* _DT_BINDINGS_CLK_MT8186_H */ 448