mt8195-clk.h revision 1.1.1.1
1/* $NetBSD: mt8195-clk.h,v 1.1.1.1 2026/01/18 05:21:33 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 4/* 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_MT8195_H 10#define _DT_BINDINGS_CLK_MT8195_H 11 12/* TOPCKGEN */ 13 14#define CLK_TOP_AXI 0 15#define CLK_TOP_SPM 1 16#define CLK_TOP_SCP 2 17#define CLK_TOP_BUS_AXIMEM 3 18#define CLK_TOP_VPP 4 19#define CLK_TOP_ETHDR 5 20#define CLK_TOP_IPE 6 21#define CLK_TOP_CAM 7 22#define CLK_TOP_CCU 8 23#define CLK_TOP_IMG 9 24#define CLK_TOP_CAMTM 10 25#define CLK_TOP_DSP 11 26#define CLK_TOP_DSP1 12 27#define CLK_TOP_DSP2 13 28#define CLK_TOP_DSP3 14 29#define CLK_TOP_DSP4 15 30#define CLK_TOP_DSP5 16 31#define CLK_TOP_DSP6 17 32#define CLK_TOP_DSP7 18 33#define CLK_TOP_IPU_IF 19 34#define CLK_TOP_MFG_CORE_TMP 20 35#define CLK_TOP_CAMTG 21 36#define CLK_TOP_CAMTG2 22 37#define CLK_TOP_CAMTG3 23 38#define CLK_TOP_CAMTG4 24 39#define CLK_TOP_CAMTG5 25 40#define CLK_TOP_UART 26 41#define CLK_TOP_SPI 27 42#define CLK_TOP_SPIS 28 43#define CLK_TOP_MSDC50_0_HCLK 29 44#define CLK_TOP_MSDC50_0 30 45#define CLK_TOP_MSDC30_1 31 46#define CLK_TOP_MSDC30_2 32 47#define CLK_TOP_INTDIR 33 48#define CLK_TOP_AUD_INTBUS 34 49#define CLK_TOP_AUDIO_H 35 50#define CLK_TOP_PWRAP_ULPOSC 36 51#define CLK_TOP_ATB 37 52#define CLK_TOP_PWRMCU 38 53#define CLK_TOP_DP 39 54#define CLK_TOP_EDP 40 55#define CLK_TOP_DPI 41 56#define CLK_TOP_DISP_PWM0 42 57#define CLK_TOP_DISP_PWM1 43 58#define CLK_TOP_USB_TOP 44 59#define CLK_TOP_SSUSB_XHCI 45 60#define CLK_TOP_USB_TOP_1P 46 61#define CLK_TOP_SSUSB_XHCI_1P 47 62#define CLK_TOP_USB_TOP_2P 48 63#define CLK_TOP_SSUSB_XHCI_2P 49 64#define CLK_TOP_USB_TOP_3P 50 65#define CLK_TOP_SSUSB_XHCI_3P 51 66#define CLK_TOP_I2C 52 67#define CLK_TOP_SENINF 53 68#define CLK_TOP_SENINF1 54 69#define CLK_TOP_SENINF2 55 70#define CLK_TOP_SENINF3 56 71#define CLK_TOP_GCPU 57 72#define CLK_TOP_DXCC 58 73#define CLK_TOP_DPMAIF_MAIN 59 74#define CLK_TOP_AES_UFSFDE 60 75#define CLK_TOP_UFS 61 76#define CLK_TOP_UFS_TICK1US 62 77#define CLK_TOP_UFS_MP_SAP_CFG 63 78#define CLK_TOP_VENC 64 79#define CLK_TOP_VDEC 65 80#define CLK_TOP_PWM 66 81#define CLK_TOP_MCUPM 67 82#define CLK_TOP_SPMI_P_MST 68 83#define CLK_TOP_SPMI_M_MST 69 84#define CLK_TOP_DVFSRC 70 85#define CLK_TOP_TL 71 86#define CLK_TOP_TL_P1 72 87#define CLK_TOP_AES_MSDCFDE 73 88#define CLK_TOP_DSI_OCC 74 89#define CLK_TOP_WPE_VPP 75 90#define CLK_TOP_HDCP 76 91#define CLK_TOP_HDCP_24M 77 92#define CLK_TOP_HD20_DACR_REF_CLK 78 93#define CLK_TOP_HD20_HDCP_CCLK 79 94#define CLK_TOP_HDMI_XTAL 80 95#define CLK_TOP_HDMI_APB 81 96#define CLK_TOP_SNPS_ETH_250M 82 97#define CLK_TOP_SNPS_ETH_62P4M_PTP 83 98#define CLK_TOP_SNPS_ETH_50M_RMII 84 99#define CLK_TOP_DGI_OUT 85 100#define CLK_TOP_NNA0 86 101#define CLK_TOP_NNA1 87 102#define CLK_TOP_ADSP 88 103#define CLK_TOP_ASM_H 89 104#define CLK_TOP_ASM_M 90 105#define CLK_TOP_ASM_L 91 106#define CLK_TOP_APLL1 92 107#define CLK_TOP_APLL2 93 108#define CLK_TOP_APLL3 94 109#define CLK_TOP_APLL4 95 110#define CLK_TOP_APLL5 96 111#define CLK_TOP_I2SO1_MCK 97 112#define CLK_TOP_I2SO2_MCK 98 113#define CLK_TOP_I2SI1_MCK 99 114#define CLK_TOP_I2SI2_MCK 100 115#define CLK_TOP_DPTX_MCK 101 116#define CLK_TOP_AUD_IEC_CLK 102 117#define CLK_TOP_A1SYS_HP 103 118#define CLK_TOP_A2SYS_HF 104 119#define CLK_TOP_A3SYS_HF 105 120#define CLK_TOP_A4SYS_HF 106 121#define CLK_TOP_SPINFI_BCLK 107 122#define CLK_TOP_NFI1X 108 123#define CLK_TOP_ECC 109 124#define CLK_TOP_AUDIO_LOCAL_BUS 110 125#define CLK_TOP_SPINOR 111 126#define CLK_TOP_DVIO_DGI_REF 112 127#define CLK_TOP_ULPOSC 113 128#define CLK_TOP_ULPOSC_CORE 114 129#define CLK_TOP_SRCK 115 130#define CLK_TOP_MFG_CK_FAST_REF 116 131#define CLK_TOP_CLK26M_D2 117 132#define CLK_TOP_CLK26M_D52 118 133#define CLK_TOP_IN_DGI 119 134#define CLK_TOP_IN_DGI_D2 120 135#define CLK_TOP_IN_DGI_D4 121 136#define CLK_TOP_IN_DGI_D6 122 137#define CLK_TOP_IN_DGI_D8 123 138#define CLK_TOP_MAINPLL_D3 124 139#define CLK_TOP_MAINPLL_D4 125 140#define CLK_TOP_MAINPLL_D4_D2 126 141#define CLK_TOP_MAINPLL_D4_D4 127 142#define CLK_TOP_MAINPLL_D4_D8 128 143#define CLK_TOP_MAINPLL_D5 129 144#define CLK_TOP_MAINPLL_D5_D2 130 145#define CLK_TOP_MAINPLL_D5_D4 131 146#define CLK_TOP_MAINPLL_D5_D8 132 147#define CLK_TOP_MAINPLL_D6 133 148#define CLK_TOP_MAINPLL_D6_D2 134 149#define CLK_TOP_MAINPLL_D6_D4 135 150#define CLK_TOP_MAINPLL_D6_D8 136 151#define CLK_TOP_MAINPLL_D7 137 152#define CLK_TOP_MAINPLL_D7_D2 138 153#define CLK_TOP_MAINPLL_D7_D4 139 154#define CLK_TOP_MAINPLL_D7_D8 140 155#define CLK_TOP_MAINPLL_D9 141 156#define CLK_TOP_UNIVPLL_D2 142 157#define CLK_TOP_UNIVPLL_D3 143 158#define CLK_TOP_UNIVPLL_D4 144 159#define CLK_TOP_UNIVPLL_D4_D2 145 160#define CLK_TOP_UNIVPLL_D4_D4 146 161#define CLK_TOP_UNIVPLL_D4_D8 147 162#define CLK_TOP_UNIVPLL_D5 148 163#define CLK_TOP_UNIVPLL_D5_D2 149 164#define CLK_TOP_UNIVPLL_D5_D4 150 165#define CLK_TOP_UNIVPLL_D5_D8 151 166#define CLK_TOP_UNIVPLL_D6 152 167#define CLK_TOP_UNIVPLL_D6_D2 153 168#define CLK_TOP_UNIVPLL_D6_D4 154 169#define CLK_TOP_UNIVPLL_D6_D8 155 170#define CLK_TOP_UNIVPLL_D6_D16 156 171#define CLK_TOP_UNIVPLL_D7 157 172#define CLK_TOP_UNIVPLL_192M 158 173#define CLK_TOP_UNIVPLL_192M_D4 159 174#define CLK_TOP_UNIVPLL_192M_D8 160 175#define CLK_TOP_UNIVPLL_192M_D16 161 176#define CLK_TOP_UNIVPLL_192M_D32 162 177#define CLK_TOP_APLL1_D3 163 178#define CLK_TOP_APLL1_D4 164 179#define CLK_TOP_APLL2_D3 165 180#define CLK_TOP_APLL2_D4 166 181#define CLK_TOP_APLL3_D4 167 182#define CLK_TOP_APLL4_D4 168 183#define CLK_TOP_APLL5_D4 169 184#define CLK_TOP_HDMIRX_APLL_D3 170 185#define CLK_TOP_HDMIRX_APLL_D4 171 186#define CLK_TOP_HDMIRX_APLL_D6 172 187#define CLK_TOP_MMPLL_D4 173 188#define CLK_TOP_MMPLL_D4_D2 174 189#define CLK_TOP_MMPLL_D4_D4 175 190#define CLK_TOP_MMPLL_D5 176 191#define CLK_TOP_MMPLL_D5_D2 177 192#define CLK_TOP_MMPLL_D5_D4 178 193#define CLK_TOP_MMPLL_D6 179 194#define CLK_TOP_MMPLL_D6_D2 180 195#define CLK_TOP_MMPLL_D7 181 196#define CLK_TOP_MMPLL_D9 182 197#define CLK_TOP_TVDPLL1_D2 183 198#define CLK_TOP_TVDPLL1_D4 184 199#define CLK_TOP_TVDPLL1_D8 185 200#define CLK_TOP_TVDPLL1_D16 186 201#define CLK_TOP_TVDPLL2_D2 187 202#define CLK_TOP_TVDPLL2_D4 188 203#define CLK_TOP_TVDPLL2_D8 189 204#define CLK_TOP_TVDPLL2_D16 190 205#define CLK_TOP_MSDCPLL_D2 191 206#define CLK_TOP_MSDCPLL_D4 192 207#define CLK_TOP_MSDCPLL_D16 193 208#define CLK_TOP_ETHPLL_D2 194 209#define CLK_TOP_ETHPLL_D8 195 210#define CLK_TOP_ETHPLL_D10 196 211#define CLK_TOP_DGIPLL_D2 197 212#define CLK_TOP_ULPOSC1 198 213#define CLK_TOP_ULPOSC1_D2 199 214#define CLK_TOP_ULPOSC1_D4 200 215#define CLK_TOP_ULPOSC1_D7 201 216#define CLK_TOP_ULPOSC1_D8 202 217#define CLK_TOP_ULPOSC1_D10 203 218#define CLK_TOP_ULPOSC1_D16 204 219#define CLK_TOP_ULPOSC2 205 220#define CLK_TOP_ADSPPLL_D2 206 221#define CLK_TOP_ADSPPLL_D4 207 222#define CLK_TOP_ADSPPLL_D8 208 223#define CLK_TOP_MEM_466M 209 224#define CLK_TOP_MPHONE_SLAVE_B 210 225#define CLK_TOP_PEXTP_PIPE 211 226#define CLK_TOP_UFS_RX_SYMBOL 212 227#define CLK_TOP_UFS_TX_SYMBOL 213 228#define CLK_TOP_SSUSB_U3PHY_P1_P_P0 214 229#define CLK_TOP_UFS_RX_SYMBOL1 215 230#define CLK_TOP_FPC 216 231#define CLK_TOP_HDMIRX_P 217 232#define CLK_TOP_APLL12_DIV0 218 233#define CLK_TOP_APLL12_DIV1 219 234#define CLK_TOP_APLL12_DIV2 220 235#define CLK_TOP_APLL12_DIV3 221 236#define CLK_TOP_APLL12_DIV4 222 237#define CLK_TOP_APLL12_DIV9 223 238#define CLK_TOP_CFG_VPP0 224 239#define CLK_TOP_CFG_VPP1 225 240#define CLK_TOP_CFG_VDO0 226 241#define CLK_TOP_CFG_VDO1 227 242#define CLK_TOP_CFG_UNIPLL_SES 228 243#define CLK_TOP_CFG_26M_VPP0 229 244#define CLK_TOP_CFG_26M_VPP1 230 245#define CLK_TOP_CFG_26M_AUD 231 246#define CLK_TOP_CFG_AXI_EAST 232 247#define CLK_TOP_CFG_AXI_EAST_NORTH 233 248#define CLK_TOP_CFG_AXI_NORTH 234 249#define CLK_TOP_CFG_AXI_SOUTH 235 250#define CLK_TOP_CFG_EXT_TEST 236 251#define CLK_TOP_SSUSB_REF 237 252#define CLK_TOP_SSUSB_PHY_REF 238 253#define CLK_TOP_SSUSB_P1_REF 239 254#define CLK_TOP_SSUSB_PHY_P1_REF 240 255#define CLK_TOP_SSUSB_P2_REF 241 256#define CLK_TOP_SSUSB_PHY_P2_REF 242 257#define CLK_TOP_SSUSB_P3_REF 243 258#define CLK_TOP_SSUSB_PHY_P3_REF 244 259#define CLK_TOP_NR_CLK 245 260 261/* INFRACFG_AO */ 262 263#define CLK_INFRA_AO_PMIC_TMR 0 264#define CLK_INFRA_AO_PMIC_AP 1 265#define CLK_INFRA_AO_PMIC_MD 2 266#define CLK_INFRA_AO_PMIC_CONN 3 267#define CLK_INFRA_AO_SEJ 4 268#define CLK_INFRA_AO_APXGPT 5 269#define CLK_INFRA_AO_GCE 6 270#define CLK_INFRA_AO_GCE2 7 271#define CLK_INFRA_AO_THERM 8 272#define CLK_INFRA_AO_PWM_H 9 273#define CLK_INFRA_AO_PWM1 10 274#define CLK_INFRA_AO_PWM2 11 275#define CLK_INFRA_AO_PWM3 12 276#define CLK_INFRA_AO_PWM4 13 277#define CLK_INFRA_AO_PWM 14 278#define CLK_INFRA_AO_UART0 15 279#define CLK_INFRA_AO_UART1 16 280#define CLK_INFRA_AO_UART2 17 281#define CLK_INFRA_AO_UART3 18 282#define CLK_INFRA_AO_UART4 19 283#define CLK_INFRA_AO_GCE_26M 20 284#define CLK_INFRA_AO_CQ_DMA_FPC 21 285#define CLK_INFRA_AO_UART5 22 286#define CLK_INFRA_AO_HDMI_26M 23 287#define CLK_INFRA_AO_SPI0 24 288#define CLK_INFRA_AO_MSDC0 25 289#define CLK_INFRA_AO_MSDC1 26 290#define CLK_INFRA_AO_CG1_MSDC2 27 291#define CLK_INFRA_AO_MSDC0_SRC 28 292#define CLK_INFRA_AO_TRNG 29 293#define CLK_INFRA_AO_AUXADC 30 294#define CLK_INFRA_AO_CPUM 31 295#define CLK_INFRA_AO_HDMI_32K 32 296#define CLK_INFRA_AO_CEC_66M_H 33 297#define CLK_INFRA_AO_IRRX 34 298#define CLK_INFRA_AO_PCIE_TL_26M 35 299#define CLK_INFRA_AO_MSDC1_SRC 36 300#define CLK_INFRA_AO_CEC_66M_B 37 301#define CLK_INFRA_AO_PCIE_TL_96M 38 302#define CLK_INFRA_AO_DEVICE_APC 39 303#define CLK_INFRA_AO_ECC_66M_H 40 304#define CLK_INFRA_AO_DEBUGSYS 41 305#define CLK_INFRA_AO_AUDIO 42 306#define CLK_INFRA_AO_PCIE_TL_32K 43 307#define CLK_INFRA_AO_DBG_TRACE 44 308#define CLK_INFRA_AO_DRAMC_F26M 45 309#define CLK_INFRA_AO_IRTX 46 310#define CLK_INFRA_AO_SSUSB 47 311#define CLK_INFRA_AO_DISP_PWM 48 312#define CLK_INFRA_AO_CLDMA_B 49 313#define CLK_INFRA_AO_AUDIO_26M_B 50 314#define CLK_INFRA_AO_SPI1 51 315#define CLK_INFRA_AO_SPI2 52 316#define CLK_INFRA_AO_SPI3 53 317#define CLK_INFRA_AO_UNIPRO_SYS 54 318#define CLK_INFRA_AO_UNIPRO_TICK 55 319#define CLK_INFRA_AO_UFS_MP_SAP_B 56 320#define CLK_INFRA_AO_PWRMCU 57 321#define CLK_INFRA_AO_PWRMCU_BUS_H 58 322#define CLK_INFRA_AO_APDMA_B 59 323#define CLK_INFRA_AO_SPI4 60 324#define CLK_INFRA_AO_SPI5 61 325#define CLK_INFRA_AO_CQ_DMA 62 326#define CLK_INFRA_AO_AES_UFSFDE 63 327#define CLK_INFRA_AO_AES 64 328#define CLK_INFRA_AO_UFS_TICK 65 329#define CLK_INFRA_AO_SSUSB_XHCI 66 330#define CLK_INFRA_AO_MSDC0_SELF 67 331#define CLK_INFRA_AO_MSDC1_SELF 68 332#define CLK_INFRA_AO_MSDC2_SELF 69 333#define CLK_INFRA_AO_I2S_DMA 70 334#define CLK_INFRA_AO_AP_MSDC0 71 335#define CLK_INFRA_AO_MD_MSDC0 72 336#define CLK_INFRA_AO_CG3_MSDC2 73 337#define CLK_INFRA_AO_GCPU 74 338#define CLK_INFRA_AO_PCIE_PERI_26M 75 339#define CLK_INFRA_AO_GCPU_66M_B 76 340#define CLK_INFRA_AO_GCPU_133M_B 77 341#define CLK_INFRA_AO_DISP_PWM1 78 342#define CLK_INFRA_AO_FBIST2FPC 79 343#define CLK_INFRA_AO_DEVICE_APC_SYNC 80 344#define CLK_INFRA_AO_PCIE_P1_PERI_26M 81 345#define CLK_INFRA_AO_SPIS0 82 346#define CLK_INFRA_AO_SPIS1 83 347#define CLK_INFRA_AO_133M_M_PERI 84 348#define CLK_INFRA_AO_66M_M_PERI 85 349#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 86 350#define CLK_INFRA_AO_PCIE_PL_P_250M_P1 87 351#define CLK_INFRA_AO_PCIE_P1_TL_96M 88 352#define CLK_INFRA_AO_AES_MSDCFDE_0P 89 353#define CLK_INFRA_AO_UFS_TX_SYMBOL 90 354#define CLK_INFRA_AO_UFS_RX_SYMBOL 91 355#define CLK_INFRA_AO_UFS_RX_SYMBOL1 92 356#define CLK_INFRA_AO_PERI_UFS_MEM_SUB 93 357#define CLK_INFRA_AO_NR_CLK 94 358 359/* APMIXEDSYS */ 360 361#define CLK_APMIXED_NNAPLL 0 362#define CLK_APMIXED_RESPLL 1 363#define CLK_APMIXED_ETHPLL 2 364#define CLK_APMIXED_MSDCPLL 3 365#define CLK_APMIXED_TVDPLL1 4 366#define CLK_APMIXED_TVDPLL2 5 367#define CLK_APMIXED_MMPLL 6 368#define CLK_APMIXED_MAINPLL 7 369#define CLK_APMIXED_VDECPLL 8 370#define CLK_APMIXED_IMGPLL 9 371#define CLK_APMIXED_UNIVPLL 10 372#define CLK_APMIXED_HDMIPLL1 11 373#define CLK_APMIXED_HDMIPLL2 12 374#define CLK_APMIXED_HDMIRX_APLL 13 375#define CLK_APMIXED_USB1PLL 14 376#define CLK_APMIXED_ADSPPLL 15 377#define CLK_APMIXED_APLL1 16 378#define CLK_APMIXED_APLL2 17 379#define CLK_APMIXED_APLL3 18 380#define CLK_APMIXED_APLL4 19 381#define CLK_APMIXED_APLL5 20 382#define CLK_APMIXED_MFGPLL 21 383#define CLK_APMIXED_DGIPLL 22 384#define CLK_APMIXED_PLL_SSUSB26M 23 385#define CLK_APMIXED_NR_CLK 24 386 387/* SCP_ADSP */ 388 389#define CLK_SCP_ADSP_AUDIODSP 0 390#define CLK_SCP_ADSP_NR_CLK 1 391 392/* PERICFG_AO */ 393 394#define CLK_PERI_AO_ETHERNET 0 395#define CLK_PERI_AO_ETHERNET_BUS 1 396#define CLK_PERI_AO_FLASHIF_BUS 2 397#define CLK_PERI_AO_FLASHIF_FLASH 3 398#define CLK_PERI_AO_SSUSB_1P_BUS 4 399#define CLK_PERI_AO_SSUSB_1P_XHCI 5 400#define CLK_PERI_AO_SSUSB_2P_BUS 6 401#define CLK_PERI_AO_SSUSB_2P_XHCI 7 402#define CLK_PERI_AO_SSUSB_3P_BUS 8 403#define CLK_PERI_AO_SSUSB_3P_XHCI 9 404#define CLK_PERI_AO_SPINFI 10 405#define CLK_PERI_AO_ETHERNET_MAC 11 406#define CLK_PERI_AO_NFI_H 12 407#define CLK_PERI_AO_FNFI1X 13 408#define CLK_PERI_AO_PCIE_P0_MEM 14 409#define CLK_PERI_AO_PCIE_P1_MEM 15 410#define CLK_PERI_AO_NR_CLK 16 411 412/* IMP_IIC_WRAP_S */ 413 414#define CLK_IMP_IIC_WRAP_S_I2C5 0 415#define CLK_IMP_IIC_WRAP_S_I2C6 1 416#define CLK_IMP_IIC_WRAP_S_I2C7 2 417#define CLK_IMP_IIC_WRAP_S_NR_CLK 3 418 419/* IMP_IIC_WRAP_W */ 420 421#define CLK_IMP_IIC_WRAP_W_I2C0 0 422#define CLK_IMP_IIC_WRAP_W_I2C1 1 423#define CLK_IMP_IIC_WRAP_W_I2C2 2 424#define CLK_IMP_IIC_WRAP_W_I2C3 3 425#define CLK_IMP_IIC_WRAP_W_I2C4 4 426#define CLK_IMP_IIC_WRAP_W_NR_CLK 5 427 428/* MFGCFG */ 429 430#define CLK_MFG_BG3D 0 431#define CLK_MFG_NR_CLK 1 432 433/* VPPSYS0 */ 434 435#define CLK_VPP0_MDP_FG 0 436#define CLK_VPP0_STITCH 1 437#define CLK_VPP0_PADDING 2 438#define CLK_VPP0_MDP_TCC 3 439#define CLK_VPP0_WARP0_ASYNC_TX 4 440#define CLK_VPP0_WARP1_ASYNC_TX 5 441#define CLK_VPP0_MUTEX 6 442#define CLK_VPP0_VPP02VPP1_RELAY 7 443#define CLK_VPP0_VPP12VPP0_ASYNC 8 444#define CLK_VPP0_MMSYSRAM_TOP 9 445#define CLK_VPP0_MDP_AAL 10 446#define CLK_VPP0_MDP_RSZ 11 447#define CLK_VPP0_SMI_COMMON 12 448#define CLK_VPP0_GALS_VDO0_LARB0 13 449#define CLK_VPP0_GALS_VDO0_LARB1 14 450#define CLK_VPP0_GALS_VENCSYS 15 451#define CLK_VPP0_GALS_VENCSYS_CORE1 16 452#define CLK_VPP0_GALS_INFRA 17 453#define CLK_VPP0_GALS_CAMSYS 18 454#define CLK_VPP0_GALS_VPP1_LARB5 19 455#define CLK_VPP0_GALS_VPP1_LARB6 20 456#define CLK_VPP0_SMI_REORDER 21 457#define CLK_VPP0_SMI_IOMMU 22 458#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23 459#define CLK_VPP0_MDP_RDMA 24 460#define CLK_VPP0_MDP_WROT 25 461#define CLK_VPP0_GALS_EMI0_EMI1 26 462#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27 463#define CLK_VPP0_SMI_RSI 28 464#define CLK_VPP0_SMI_COMMON_LARB4 29 465#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30 466#define CLK_VPP0_GALS_VPP1_WPE 31 467#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 468#define CLK_VPP0_FAKE_ENG 33 469#define CLK_VPP0_MDP_HDR 34 470#define CLK_VPP0_MDP_TDSHP 35 471#define CLK_VPP0_MDP_COLOR 36 472#define CLK_VPP0_MDP_OVL 37 473#define CLK_VPP0_WARP0_RELAY 38 474#define CLK_VPP0_WARP0_MDP_DL_ASYNC 39 475#define CLK_VPP0_WARP1_RELAY 40 476#define CLK_VPP0_WARP1_MDP_DL_ASYNC 41 477#define CLK_VPP0_NR_CLK 42 478 479/* WPESYS */ 480 481#define CLK_WPE_VPP0 0 482#define CLK_WPE_VPP1 1 483#define CLK_WPE_SMI_LARB7 2 484#define CLK_WPE_SMI_LARB8 3 485#define CLK_WPE_EVENT_TX 4 486#define CLK_WPE_SMI_LARB7_P 5 487#define CLK_WPE_SMI_LARB8_P 6 488#define CLK_WPE_NR_CLK 7 489 490/* WPESYS_VPP0 */ 491 492#define CLK_WPE_VPP0_VECI 0 493#define CLK_WPE_VPP0_VEC2I 1 494#define CLK_WPE_VPP0_VEC3I 2 495#define CLK_WPE_VPP0_WPEO 3 496#define CLK_WPE_VPP0_MSKO 4 497#define CLK_WPE_VPP0_VGEN 5 498#define CLK_WPE_VPP0_EXT 6 499#define CLK_WPE_VPP0_VFC 7 500#define CLK_WPE_VPP0_CACH0_TOP 8 501#define CLK_WPE_VPP0_CACH0_DMA 9 502#define CLK_WPE_VPP0_CACH1_TOP 10 503#define CLK_WPE_VPP0_CACH1_DMA 11 504#define CLK_WPE_VPP0_CACH2_TOP 12 505#define CLK_WPE_VPP0_CACH2_DMA 13 506#define CLK_WPE_VPP0_CACH3_TOP 14 507#define CLK_WPE_VPP0_CACH3_DMA 15 508#define CLK_WPE_VPP0_PSP 16 509#define CLK_WPE_VPP0_PSP2 17 510#define CLK_WPE_VPP0_SYNC 18 511#define CLK_WPE_VPP0_C24 19 512#define CLK_WPE_VPP0_MDP_CROP 20 513#define CLK_WPE_VPP0_ISP_CROP 21 514#define CLK_WPE_VPP0_TOP 22 515#define CLK_WPE_VPP0_NR_CLK 23 516 517/* WPESYS_VPP1 */ 518 519#define CLK_WPE_VPP1_VECI 0 520#define CLK_WPE_VPP1_VEC2I 1 521#define CLK_WPE_VPP1_VEC3I 2 522#define CLK_WPE_VPP1_WPEO 3 523#define CLK_WPE_VPP1_MSKO 4 524#define CLK_WPE_VPP1_VGEN 5 525#define CLK_WPE_VPP1_EXT 6 526#define CLK_WPE_VPP1_VFC 7 527#define CLK_WPE_VPP1_CACH0_TOP 8 528#define CLK_WPE_VPP1_CACH0_DMA 9 529#define CLK_WPE_VPP1_CACH1_TOP 10 530#define CLK_WPE_VPP1_CACH1_DMA 11 531#define CLK_WPE_VPP1_CACH2_TOP 12 532#define CLK_WPE_VPP1_CACH2_DMA 13 533#define CLK_WPE_VPP1_CACH3_TOP 14 534#define CLK_WPE_VPP1_CACH3_DMA 15 535#define CLK_WPE_VPP1_PSP 16 536#define CLK_WPE_VPP1_PSP2 17 537#define CLK_WPE_VPP1_SYNC 18 538#define CLK_WPE_VPP1_C24 19 539#define CLK_WPE_VPP1_MDP_CROP 20 540#define CLK_WPE_VPP1_ISP_CROP 21 541#define CLK_WPE_VPP1_TOP 22 542#define CLK_WPE_VPP1_NR_CLK 23 543 544/* VPPSYS1 */ 545 546#define CLK_VPP1_SVPP1_MDP_OVL 0 547#define CLK_VPP1_SVPP1_MDP_TCC 1 548#define CLK_VPP1_SVPP1_MDP_WROT 2 549#define CLK_VPP1_SVPP1_VPP_PAD 3 550#define CLK_VPP1_SVPP2_MDP_WROT 4 551#define CLK_VPP1_SVPP2_VPP_PAD 5 552#define CLK_VPP1_SVPP3_MDP_WROT 6 553#define CLK_VPP1_SVPP3_VPP_PAD 7 554#define CLK_VPP1_SVPP1_MDP_RDMA 8 555#define CLK_VPP1_SVPP1_MDP_FG 9 556#define CLK_VPP1_SVPP2_MDP_RDMA 10 557#define CLK_VPP1_SVPP2_MDP_FG 11 558#define CLK_VPP1_SVPP3_MDP_RDMA 12 559#define CLK_VPP1_SVPP3_MDP_FG 13 560#define CLK_VPP1_VPP_SPLIT 14 561#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15 562#define CLK_VPP1_SVPP1_MDP_TDSHP 16 563#define CLK_VPP1_SVPP1_MDP_COLOR 17 564#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 18 565#define CLK_VPP1_SVPP2_VPP_MERGE 19 566#define CLK_VPP1_SVPP2_MDP_COLOR 20 567#define CLK_VPP1_VPPSYS1_GALS 21 568#define CLK_VPP1_SVPP3_VPP_MERGE 22 569#define CLK_VPP1_SVPP3_MDP_COLOR 23 570#define CLK_VPP1_VPPSYS1_LARB 24 571#define CLK_VPP1_SVPP1_MDP_RSZ 25 572#define CLK_VPP1_SVPP1_MDP_HDR 26 573#define CLK_VPP1_SVPP1_MDP_AAL 27 574#define CLK_VPP1_SVPP2_MDP_HDR 28 575#define CLK_VPP1_SVPP2_MDP_AAL 29 576#define CLK_VPP1_DL_ASYNC 30 577#define CLK_VPP1_LARB5_FAKE_ENG 31 578#define CLK_VPP1_SVPP3_MDP_HDR 32 579#define CLK_VPP1_SVPP3_MDP_AAL 33 580#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 34 581#define CLK_VPP1_LARB6_FAKE_ENG 35 582#define CLK_VPP1_SVPP2_MDP_RSZ 36 583#define CLK_VPP1_SVPP3_MDP_RSZ 37 584#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38 585#define CLK_VPP1_DISP_MUTEX 39 586#define CLK_VPP1_SVPP2_MDP_TDSHP 40 587#define CLK_VPP1_SVPP3_MDP_TDSHP 41 588#define CLK_VPP1_VPP0_DL1_RELAY 42 589#define CLK_VPP1_HDMI_META 43 590#define CLK_VPP1_VPP_SPLIT_HDMI 44 591#define CLK_VPP1_DGI_IN 45 592#define CLK_VPP1_DGI_OUT 46 593#define CLK_VPP1_VPP_SPLIT_DGI 47 594#define CLK_VPP1_VPP0_DL_ASYNC 48 595#define CLK_VPP1_VPP0_DL_RELAY 49 596#define CLK_VPP1_VPP_SPLIT_26M 50 597#define CLK_VPP1_NR_CLK 51 598 599/* IMGSYS */ 600 601#define CLK_IMG_LARB9 0 602#define CLK_IMG_TRAW0 1 603#define CLK_IMG_TRAW1 2 604#define CLK_IMG_TRAW2 3 605#define CLK_IMG_TRAW3 4 606#define CLK_IMG_DIP0 5 607#define CLK_IMG_WPE0 6 608#define CLK_IMG_IPE 7 609#define CLK_IMG_DIP1 8 610#define CLK_IMG_WPE1 9 611#define CLK_IMG_GALS 10 612#define CLK_IMG_NR_CLK 11 613 614/* IMGSYS1_DIP_TOP */ 615 616#define CLK_IMG1_DIP_TOP_LARB10 0 617#define CLK_IMG1_DIP_TOP_DIP_TOP 1 618#define CLK_IMG1_DIP_TOP_NR_CLK 2 619 620/* IMGSYS1_DIP_NR */ 621 622#define CLK_IMG1_DIP_NR_RESERVE 0 623#define CLK_IMG1_DIP_NR_DIP_NR 1 624#define CLK_IMG1_DIP_NR_NR_CLK 2 625 626/* IMGSYS1_WPE */ 627 628#define CLK_IMG1_WPE_LARB11 0 629#define CLK_IMG1_WPE_WPE 1 630#define CLK_IMG1_WPE_NR_CLK 2 631 632/* IPESYS */ 633 634#define CLK_IPE_DPE 0 635#define CLK_IPE_FDVT 1 636#define CLK_IPE_ME 2 637#define CLK_IPE_TOP 3 638#define CLK_IPE_SMI_LARB12 4 639#define CLK_IPE_NR_CLK 5 640 641/* CAMSYS */ 642 643#define CLK_CAM_LARB13 0 644#define CLK_CAM_LARB14 1 645#define CLK_CAM_MAIN_CAM 2 646#define CLK_CAM_MAIN_CAMTG 3 647#define CLK_CAM_SENINF 4 648#define CLK_CAM_GCAMSVA 5 649#define CLK_CAM_GCAMSVB 6 650#define CLK_CAM_GCAMSVC 7 651#define CLK_CAM_SCAMSA 8 652#define CLK_CAM_SCAMSB 9 653#define CLK_CAM_CAMSV_TOP 10 654#define CLK_CAM_CAMSV_CQ 11 655#define CLK_CAM_ADL 12 656#define CLK_CAM_ASG 13 657#define CLK_CAM_PDA 14 658#define CLK_CAM_FAKE_ENG 15 659#define CLK_CAM_MAIN_MRAW0 16 660#define CLK_CAM_MAIN_MRAW1 17 661#define CLK_CAM_MAIN_MRAW2 18 662#define CLK_CAM_MAIN_MRAW3 19 663#define CLK_CAM_CAM2MM0_GALS 20 664#define CLK_CAM_CAM2MM1_GALS 21 665#define CLK_CAM_CAM2SYS_GALS 22 666#define CLK_CAM_NR_CLK 23 667 668/* CAMSYS_RAWA */ 669 670#define CLK_CAM_RAWA_LARBX 0 671#define CLK_CAM_RAWA_CAM 1 672#define CLK_CAM_RAWA_CAMTG 2 673#define CLK_CAM_RAWA_NR_CLK 3 674 675/* CAMSYS_YUVA */ 676 677#define CLK_CAM_YUVA_LARBX 0 678#define CLK_CAM_YUVA_CAM 1 679#define CLK_CAM_YUVA_CAMTG 2 680#define CLK_CAM_YUVA_NR_CLK 3 681 682/* CAMSYS_RAWB */ 683 684#define CLK_CAM_RAWB_LARBX 0 685#define CLK_CAM_RAWB_CAM 1 686#define CLK_CAM_RAWB_CAMTG 2 687#define CLK_CAM_RAWB_NR_CLK 3 688 689/* CAMSYS_YUVB */ 690 691#define CLK_CAM_YUVB_LARBX 0 692#define CLK_CAM_YUVB_CAM 1 693#define CLK_CAM_YUVB_CAMTG 2 694#define CLK_CAM_YUVB_NR_CLK 3 695 696/* CAMSYS_MRAW */ 697 698#define CLK_CAM_MRAW_LARBX 0 699#define CLK_CAM_MRAW_CAMTG 1 700#define CLK_CAM_MRAW_MRAW0 2 701#define CLK_CAM_MRAW_MRAW1 3 702#define CLK_CAM_MRAW_MRAW2 4 703#define CLK_CAM_MRAW_MRAW3 5 704#define CLK_CAM_MRAW_NR_CLK 6 705 706/* CCUSYS */ 707 708#define CLK_CCU_LARB18 0 709#define CLK_CCU_AHB 1 710#define CLK_CCU_CCU0 2 711#define CLK_CCU_CCU1 3 712#define CLK_CCU_NR_CLK 4 713 714/* VDECSYS_SOC */ 715 716#define CLK_VDEC_SOC_LARB1 0 717#define CLK_VDEC_SOC_LAT 1 718#define CLK_VDEC_SOC_VDEC 2 719#define CLK_VDEC_SOC_NR_CLK 3 720 721/* VDECSYS */ 722 723#define CLK_VDEC_LARB1 0 724#define CLK_VDEC_LAT 1 725#define CLK_VDEC_VDEC 2 726#define CLK_VDEC_NR_CLK 3 727 728/* VDECSYS_CORE1 */ 729 730#define CLK_VDEC_CORE1_LARB1 0 731#define CLK_VDEC_CORE1_LAT 1 732#define CLK_VDEC_CORE1_VDEC 2 733#define CLK_VDEC_CORE1_NR_CLK 3 734 735/* APUSYS_PLL */ 736 737#define CLK_APUSYS_PLL_APUPLL 0 738#define CLK_APUSYS_PLL_NPUPLL 1 739#define CLK_APUSYS_PLL_APUPLL1 2 740#define CLK_APUSYS_PLL_APUPLL2 3 741#define CLK_APUSYS_PLL_NR_CLK 4 742 743/* VENCSYS */ 744 745#define CLK_VENC_LARB 0 746#define CLK_VENC_VENC 1 747#define CLK_VENC_JPGENC 2 748#define CLK_VENC_JPGDEC 3 749#define CLK_VENC_JPGDEC_C1 4 750#define CLK_VENC_GALS 5 751#define CLK_VENC_NR_CLK 6 752 753/* VENCSYS_CORE1 */ 754 755#define CLK_VENC_CORE1_LARB 0 756#define CLK_VENC_CORE1_VENC 1 757#define CLK_VENC_CORE1_JPGENC 2 758#define CLK_VENC_CORE1_JPGDEC 3 759#define CLK_VENC_CORE1_JPGDEC_C1 4 760#define CLK_VENC_CORE1_GALS 5 761#define CLK_VENC_CORE1_NR_CLK 6 762 763/* VDOSYS0 */ 764 765#define CLK_VDO0_DISP_OVL0 0 766#define CLK_VDO0_DISP_COLOR0 1 767#define CLK_VDO0_DISP_COLOR1 2 768#define CLK_VDO0_DISP_CCORR0 3 769#define CLK_VDO0_DISP_CCORR1 4 770#define CLK_VDO0_DISP_AAL0 5 771#define CLK_VDO0_DISP_AAL1 6 772#define CLK_VDO0_DISP_GAMMA0 7 773#define CLK_VDO0_DISP_GAMMA1 8 774#define CLK_VDO0_DISP_DITHER0 9 775#define CLK_VDO0_DISP_DITHER1 10 776#define CLK_VDO0_DISP_OVL1 11 777#define CLK_VDO0_DISP_WDMA0 12 778#define CLK_VDO0_DISP_WDMA1 13 779#define CLK_VDO0_DISP_RDMA0 14 780#define CLK_VDO0_DISP_RDMA1 15 781#define CLK_VDO0_DSI0 16 782#define CLK_VDO0_DSI1 17 783#define CLK_VDO0_DSC_WRAP0 18 784#define CLK_VDO0_VPP_MERGE0 19 785#define CLK_VDO0_DP_INTF0 20 786#define CLK_VDO0_DISP_MUTEX0 21 787#define CLK_VDO0_DISP_IL_ROT0 22 788#define CLK_VDO0_APB_BUS 23 789#define CLK_VDO0_FAKE_ENG0 24 790#define CLK_VDO0_FAKE_ENG1 25 791#define CLK_VDO0_DL_ASYNC0 26 792#define CLK_VDO0_DL_ASYNC1 27 793#define CLK_VDO0_DL_ASYNC2 28 794#define CLK_VDO0_DL_ASYNC3 29 795#define CLK_VDO0_DL_ASYNC4 30 796#define CLK_VDO0_DISP_MONITOR0 31 797#define CLK_VDO0_DISP_MONITOR1 32 798#define CLK_VDO0_DISP_MONITOR2 33 799#define CLK_VDO0_DISP_MONITOR3 34 800#define CLK_VDO0_DISP_MONITOR4 35 801#define CLK_VDO0_SMI_GALS 36 802#define CLK_VDO0_SMI_COMMON 37 803#define CLK_VDO0_SMI_EMI 38 804#define CLK_VDO0_SMI_IOMMU 39 805#define CLK_VDO0_SMI_LARB 40 806#define CLK_VDO0_SMI_RSI 41 807#define CLK_VDO0_DSI0_DSI 42 808#define CLK_VDO0_DSI1_DSI 43 809#define CLK_VDO0_DP_INTF0_DP_INTF 44 810#define CLK_VDO0_NR_CLK 45 811 812/* VDOSYS1 */ 813 814#define CLK_VDO1_SMI_LARB2 0 815#define CLK_VDO1_SMI_LARB3 1 816#define CLK_VDO1_GALS 2 817#define CLK_VDO1_FAKE_ENG0 3 818#define CLK_VDO1_FAKE_ENG 4 819#define CLK_VDO1_MDP_RDMA0 5 820#define CLK_VDO1_MDP_RDMA1 6 821#define CLK_VDO1_MDP_RDMA2 7 822#define CLK_VDO1_MDP_RDMA3 8 823#define CLK_VDO1_VPP_MERGE0 9 824#define CLK_VDO1_VPP_MERGE1 10 825#define CLK_VDO1_VPP_MERGE2 11 826#define CLK_VDO1_VPP_MERGE3 12 827#define CLK_VDO1_VPP_MERGE4 13 828#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 829#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15 830#define CLK_VDO1_DISP_MUTEX 16 831#define CLK_VDO1_MDP_RDMA4 17 832#define CLK_VDO1_MDP_RDMA5 18 833#define CLK_VDO1_MDP_RDMA6 19 834#define CLK_VDO1_MDP_RDMA7 20 835#define CLK_VDO1_DP_INTF0_MM 21 836#define CLK_VDO1_DPI0_MM 22 837#define CLK_VDO1_DPI1_MM 23 838#define CLK_VDO1_DISP_MONITOR 24 839#define CLK_VDO1_MERGE0_DL_ASYNC 25 840#define CLK_VDO1_MERGE1_DL_ASYNC 26 841#define CLK_VDO1_MERGE2_DL_ASYNC 27 842#define CLK_VDO1_MERGE3_DL_ASYNC 28 843#define CLK_VDO1_MERGE4_DL_ASYNC 29 844#define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC 30 845#define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC 31 846#define CLK_VDO1_HDR_VDO_FE0 32 847#define CLK_VDO1_HDR_GFX_FE0 33 848#define CLK_VDO1_HDR_VDO_BE 34 849#define CLK_VDO1_HDR_VDO_FE1 35 850#define CLK_VDO1_HDR_GFX_FE1 36 851#define CLK_VDO1_DISP_MIXER 37 852#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38 853#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 39 854#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 40 855#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41 856#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 42 857#define CLK_VDO1_DPI0 43 858#define CLK_VDO1_DISP_MONITOR_DPI0 44 859#define CLK_VDO1_DPI1 45 860#define CLK_VDO1_DISP_MONITOR_DPI1 46 861#define CLK_VDO1_DPINTF 47 862#define CLK_VDO1_DISP_MONITOR_DPINTF 48 863#define CLK_VDO1_26M_SLOW 49 864#define CLK_VDO1_DPI1_HDMI 50 865#define CLK_VDO1_NR_CLK 51 866 867 868#endif /* _DT_BINDINGS_CLK_MT8195_H */ 869