11.1Sskrll/* $NetBSD: nxp,imx95-clock.h,v 1.1.1.1 2026/01/18 05:21:33 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 41.1Sskrll/* 51.1Sskrll * Copyright 2024 NXP 61.1Sskrll */ 71.1Sskrll 81.1Sskrll#ifndef __DT_BINDINGS_CLOCK_IMX95_H 91.1Sskrll#define __DT_BINDINGS_CLOCK_IMX95_H 101.1Sskrll 111.1Sskrll#define IMX95_CLK_VPUBLK_WAVE 0 121.1Sskrll#define IMX95_CLK_VPUBLK_JPEG_ENC 1 131.1Sskrll#define IMX95_CLK_VPUBLK_JPEG_DEC 2 141.1Sskrll 151.1Sskrll#define IMX95_CLK_CAMBLK_CSI2_FOR0 0 161.1Sskrll#define IMX95_CLK_CAMBLK_CSI2_FOR1 1 171.1Sskrll#define IMX95_CLK_CAMBLK_ISP_AXI 2 181.1Sskrll#define IMX95_CLK_CAMBLK_ISP_PIXEL 3 191.1Sskrll#define IMX95_CLK_CAMBLK_ISP 4 201.1Sskrll 211.1Sskrll#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 221.1Sskrll#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 231.1Sskrll#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 241.1Sskrll#define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 251.1Sskrll#define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 261.1Sskrll 271.1Sskrll#define IMX95_CLK_DISPMIX_ENG0_SEL 0 281.1Sskrll#define IMX95_CLK_DISPMIX_ENG1_SEL 1 291.1Sskrll 301.1Sskrll#define IMX95_CLK_NETCMIX_ENETC0_RMII 0 311.1Sskrll#define IMX95_CLK_NETCMIX_ENETC1_RMII 1 321.1Sskrll 331.1Sskrll#endif /* __DT_BINDINGS_CLOCK_IMX95_H */ 34