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omap5.h revision 1.1.1.1.2.2 
      1 /*	$NetBSD: omap5.h,v 1.1.1.1.2.2 2018/05/02 07:20:21 pgoyette Exp $	*/
      2 
      3 /*
      4  * Copyright 2017 Texas Instruments, Inc.
      5  *
      6  * This software is licensed under the terms of the GNU General Public
      7  * License version 2, as published by the Free Software Foundation, and
      8  * may be copied, distributed, and modified under those terms.
      9  *
     10  * This program is distributed in the hope that it will be useful,
     11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     13  * GNU General Public License for more details.
     14  */
     15 #ifndef __DT_BINDINGS_CLK_OMAP5_H
     16 #define __DT_BINDINGS_CLK_OMAP5_H
     17 
     18 #define OMAP5_CLKCTRL_OFFSET	0x20
     19 #define OMAP5_CLKCTRL_INDEX(offset)	((offset) - OMAP5_CLKCTRL_OFFSET)
     20 
     21 /* mpu clocks */
     22 #define OMAP5_MPU_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     23 
     24 /* dsp clocks */
     25 #define OMAP5_MMU_DSP_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     26 
     27 /* abe clocks */
     28 #define OMAP5_L4_ABE_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     29 #define OMAP5_MCPDM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
     30 #define OMAP5_DMIC_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
     31 #define OMAP5_MCBSP1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x48)
     32 #define OMAP5_MCBSP2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
     33 #define OMAP5_MCBSP3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x58)
     34 #define OMAP5_TIMER5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
     35 #define OMAP5_TIMER6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x70)
     36 #define OMAP5_TIMER7_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
     37 #define OMAP5_TIMER8_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x80)
     38 
     39 /* l3main1 clocks */
     40 #define OMAP5_L3_MAIN_1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     41 
     42 /* l3main2 clocks */
     43 #define OMAP5_L3_MAIN_2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     44 
     45 /* ipu clocks */
     46 #define OMAP5_MMU_IPU_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     47 
     48 /* dma clocks */
     49 #define OMAP5_DMA_SYSTEM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     50 
     51 /* emif clocks */
     52 #define OMAP5_DMM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     53 #define OMAP5_EMIF1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
     54 #define OMAP5_EMIF2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
     55 
     56 /* l4cfg clocks */
     57 #define OMAP5_L4_CFG_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     58 #define OMAP5_SPINLOCK_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
     59 #define OMAP5_MAILBOX_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
     60 
     61 /* l3instr clocks */
     62 #define OMAP5_L3_MAIN_3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
     63 #define OMAP5_L3_INSTR_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
     64 
     65 /* l4per clocks */
     66 #define OMAP5_TIMER10_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
     67 #define OMAP5_TIMER11_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
     68 #define OMAP5_TIMER2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
     69 #define OMAP5_TIMER3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x40)
     70 #define OMAP5_TIMER4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x48)
     71 #define OMAP5_TIMER9_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
     72 #define OMAP5_GPIO2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x60)
     73 #define OMAP5_GPIO3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
     74 #define OMAP5_GPIO4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x70)
     75 #define OMAP5_GPIO5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
     76 #define OMAP5_GPIO6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x80)
     77 #define OMAP5_I2C1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xa0)
     78 #define OMAP5_I2C2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xa8)
     79 #define OMAP5_I2C3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xb0)
     80 #define OMAP5_I2C4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xb8)
     81 #define OMAP5_L4_PER_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xc0)
     82 #define OMAP5_MCSPI1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf0)
     83 #define OMAP5_MCSPI2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf8)
     84 #define OMAP5_MCSPI3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x100)
     85 #define OMAP5_MCSPI4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x108)
     86 #define OMAP5_GPIO7_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x110)
     87 #define OMAP5_GPIO8_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x118)
     88 #define OMAP5_MMC3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x120)
     89 #define OMAP5_MMC4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x128)
     90 #define OMAP5_UART1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x140)
     91 #define OMAP5_UART2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x148)
     92 #define OMAP5_UART3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x150)
     93 #define OMAP5_UART4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x158)
     94 #define OMAP5_MMC5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x160)
     95 #define OMAP5_I2C5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x168)
     96 #define OMAP5_UART5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x170)
     97 #define OMAP5_UART6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x178)
     98 
     99 /* dss clocks */
    100 #define OMAP5_DSS_CORE_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
    101 
    102 /* l3init clocks */
    103 #define OMAP5_MMC1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
    104 #define OMAP5_MMC2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
    105 #define OMAP5_USB_HOST_HS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x58)
    106 #define OMAP5_USB_TLL_HS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
    107 #define OMAP5_SATA_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x88)
    108 #define OMAP5_OCP2SCP1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xe0)
    109 #define OMAP5_OCP2SCP3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xe8)
    110 #define OMAP5_USB_OTG_SS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf0)
    111 
    112 /* wkupaon clocks */
    113 #define OMAP5_L4_WKUP_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
    114 #define OMAP5_WD_TIMER2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
    115 #define OMAP5_GPIO1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
    116 #define OMAP5_TIMER1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x40)
    117 #define OMAP5_COUNTER_32K_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
    118 #define OMAP5_KBD_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
    119 
    120 #endif
    121