11.1Sjmcneill/* $NetBSD: qcom,dispcc-sdm845.h,v 1.1.1.2 2021/11/07 16:49:59 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sjmcneill/* 51.1.1.2Sjmcneill * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 91.1Sjmcneill#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 101.1Sjmcneill 111.1Sjmcneill/* DISP_CC clock registers */ 121.1Sjmcneill#define DISP_CC_MDSS_AHB_CLK 0 131.1Sjmcneill#define DISP_CC_MDSS_AXI_CLK 1 141.1Sjmcneill#define DISP_CC_MDSS_BYTE0_CLK 2 151.1Sjmcneill#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 161.1Sjmcneill#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 171.1Sjmcneill#define DISP_CC_MDSS_BYTE1_CLK 5 181.1Sjmcneill#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 191.1Sjmcneill#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 201.1Sjmcneill#define DISP_CC_MDSS_ESC0_CLK 8 211.1Sjmcneill#define DISP_CC_MDSS_ESC0_CLK_SRC 9 221.1Sjmcneill#define DISP_CC_MDSS_ESC1_CLK 10 231.1Sjmcneill#define DISP_CC_MDSS_ESC1_CLK_SRC 11 241.1Sjmcneill#define DISP_CC_MDSS_MDP_CLK 12 251.1Sjmcneill#define DISP_CC_MDSS_MDP_CLK_SRC 13 261.1Sjmcneill#define DISP_CC_MDSS_MDP_LUT_CLK 14 271.1Sjmcneill#define DISP_CC_MDSS_PCLK0_CLK 15 281.1Sjmcneill#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 291.1Sjmcneill#define DISP_CC_MDSS_PCLK1_CLK 17 301.1Sjmcneill#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 311.1Sjmcneill#define DISP_CC_MDSS_ROT_CLK 19 321.1Sjmcneill#define DISP_CC_MDSS_ROT_CLK_SRC 20 331.1Sjmcneill#define DISP_CC_MDSS_RSCC_AHB_CLK 21 341.1Sjmcneill#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 351.1Sjmcneill#define DISP_CC_MDSS_VSYNC_CLK 23 361.1Sjmcneill#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 371.1Sjmcneill#define DISP_CC_PLL0 25 381.1Sjmcneill#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 391.1Sjmcneill#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 401.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_AUX_CLK 28 411.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 421.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 431.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 441.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_LINK_CLK 32 451.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 461.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 471.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 481.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 491.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_PIXEL_CLK 37 501.1.1.2Sjmcneill#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 511.1Sjmcneill 521.1Sjmcneill/* DISP_CC Reset */ 531.1Sjmcneill#define DISP_CC_MDSS_RSCC_BCR 0 541.1Sjmcneill 551.1Sjmcneill/* DISP_CC GDSCR */ 561.1Sjmcneill#define MDSS_GDSC 0 571.1Sjmcneill 581.1Sjmcneill#endif 59