11.1Sjmcneill/*	$NetBSD: qcom,gcc-ipq6018.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
21.1Sjmcneill
31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */
41.1Sjmcneill/*
51.1Sjmcneill * Copyright (c) 2018, The Linux Foundation. All rights reserved.
61.1Sjmcneill */
71.1Sjmcneill
81.1Sjmcneill#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
91.1Sjmcneill#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
101.1Sjmcneill
111.1Sjmcneill#define GPLL0					0
121.1Sjmcneill#define UBI32_PLL				1
131.1Sjmcneill#define GPLL6					2
141.1Sjmcneill#define GPLL4					3
151.1Sjmcneill#define PCNOC_BFDCD_CLK_SRC			4
161.1Sjmcneill#define GPLL2					5
171.1Sjmcneill#define NSS_CRYPTO_PLL				6
181.1Sjmcneill#define NSS_PPE_CLK_SRC				7
191.1Sjmcneill#define GCC_XO_CLK_SRC				8
201.1Sjmcneill#define NSS_CE_CLK_SRC				9
211.1Sjmcneill#define GCC_SLEEP_CLK_SRC			10
221.1Sjmcneill#define APSS_AHB_CLK_SRC			11
231.1Sjmcneill#define NSS_PORT5_RX_CLK_SRC			12
241.1Sjmcneill#define NSS_PORT5_TX_CLK_SRC			13
251.1Sjmcneill#define PCIE0_AXI_CLK_SRC			14
261.1Sjmcneill#define USB0_MASTER_CLK_SRC			15
271.1Sjmcneill#define APSS_AHB_POSTDIV_CLK_SRC		16
281.1Sjmcneill#define NSS_PORT1_RX_CLK_SRC			17
291.1Sjmcneill#define NSS_PORT1_TX_CLK_SRC			18
301.1Sjmcneill#define NSS_PORT2_RX_CLK_SRC			19
311.1Sjmcneill#define NSS_PORT2_TX_CLK_SRC			20
321.1Sjmcneill#define NSS_PORT3_RX_CLK_SRC			21
331.1Sjmcneill#define NSS_PORT3_TX_CLK_SRC			22
341.1Sjmcneill#define NSS_PORT4_RX_CLK_SRC			23
351.1Sjmcneill#define NSS_PORT4_TX_CLK_SRC			24
361.1Sjmcneill#define NSS_PORT5_RX_DIV_CLK_SRC		25
371.1Sjmcneill#define NSS_PORT5_TX_DIV_CLK_SRC		26
381.1Sjmcneill#define APSS_AXI_CLK_SRC			27
391.1Sjmcneill#define NSS_CRYPTO_CLK_SRC			28
401.1Sjmcneill#define NSS_PORT1_RX_DIV_CLK_SRC		29
411.1Sjmcneill#define NSS_PORT1_TX_DIV_CLK_SRC		30
421.1Sjmcneill#define NSS_PORT2_RX_DIV_CLK_SRC		31
431.1Sjmcneill#define NSS_PORT2_TX_DIV_CLK_SRC		32
441.1Sjmcneill#define NSS_PORT3_RX_DIV_CLK_SRC		33
451.1Sjmcneill#define NSS_PORT3_TX_DIV_CLK_SRC		34
461.1Sjmcneill#define NSS_PORT4_RX_DIV_CLK_SRC		35
471.1Sjmcneill#define NSS_PORT4_TX_DIV_CLK_SRC		36
481.1Sjmcneill#define NSS_UBI0_CLK_SRC			37
491.1Sjmcneill#define BLSP1_QUP1_I2C_APPS_CLK_SRC		38
501.1Sjmcneill#define BLSP1_QUP1_SPI_APPS_CLK_SRC		39
511.1Sjmcneill#define BLSP1_QUP2_I2C_APPS_CLK_SRC		40
521.1Sjmcneill#define BLSP1_QUP2_SPI_APPS_CLK_SRC		41
531.1Sjmcneill#define BLSP1_QUP3_I2C_APPS_CLK_SRC		42
541.1Sjmcneill#define BLSP1_QUP3_SPI_APPS_CLK_SRC		43
551.1Sjmcneill#define BLSP1_QUP4_I2C_APPS_CLK_SRC		44
561.1Sjmcneill#define BLSP1_QUP4_SPI_APPS_CLK_SRC		45
571.1Sjmcneill#define BLSP1_QUP5_I2C_APPS_CLK_SRC		46
581.1Sjmcneill#define BLSP1_QUP5_SPI_APPS_CLK_SRC		47
591.1Sjmcneill#define BLSP1_QUP6_I2C_APPS_CLK_SRC		48
601.1Sjmcneill#define BLSP1_QUP6_SPI_APPS_CLK_SRC		49
611.1Sjmcneill#define BLSP1_UART1_APPS_CLK_SRC		50
621.1Sjmcneill#define BLSP1_UART2_APPS_CLK_SRC		51
631.1Sjmcneill#define BLSP1_UART3_APPS_CLK_SRC		52
641.1Sjmcneill#define BLSP1_UART4_APPS_CLK_SRC		53
651.1Sjmcneill#define BLSP1_UART5_APPS_CLK_SRC		54
661.1Sjmcneill#define BLSP1_UART6_APPS_CLK_SRC		55
671.1Sjmcneill#define CRYPTO_CLK_SRC				56
681.1Sjmcneill#define NSS_UBI0_DIV_CLK_SRC			57
691.1Sjmcneill#define PCIE0_AUX_CLK_SRC			58
701.1Sjmcneill#define PCIE0_PIPE_CLK_SRC			59
711.1Sjmcneill#define SDCC1_APPS_CLK_SRC			60
721.1Sjmcneill#define USB0_AUX_CLK_SRC			61
731.1Sjmcneill#define USB0_MOCK_UTMI_CLK_SRC			62
741.1Sjmcneill#define USB0_PIPE_CLK_SRC			63
751.1Sjmcneill#define USB1_MOCK_UTMI_CLK_SRC			64
761.1Sjmcneill#define GCC_APSS_AHB_CLK			65
771.1Sjmcneill#define GCC_APSS_AXI_CLK			66
781.1Sjmcneill#define GCC_BLSP1_AHB_CLK			67
791.1Sjmcneill#define GCC_BLSP1_QUP1_I2C_APPS_CLK		68
801.1Sjmcneill#define GCC_BLSP1_QUP1_SPI_APPS_CLK		69
811.1Sjmcneill#define GCC_BLSP1_QUP2_I2C_APPS_CLK		70
821.1Sjmcneill#define GCC_BLSP1_QUP2_SPI_APPS_CLK		71
831.1Sjmcneill#define GCC_BLSP1_QUP3_I2C_APPS_CLK		72
841.1Sjmcneill#define GCC_BLSP1_QUP3_SPI_APPS_CLK		73
851.1Sjmcneill#define GCC_BLSP1_QUP4_I2C_APPS_CLK		74
861.1Sjmcneill#define GCC_BLSP1_QUP4_SPI_APPS_CLK		75
871.1Sjmcneill#define GCC_BLSP1_QUP5_I2C_APPS_CLK		76
881.1Sjmcneill#define GCC_BLSP1_QUP5_SPI_APPS_CLK		77
891.1Sjmcneill#define GCC_BLSP1_QUP6_I2C_APPS_CLK		78
901.1Sjmcneill#define GCC_BLSP1_QUP6_SPI_APPS_CLK		79
911.1Sjmcneill#define GCC_BLSP1_UART1_APPS_CLK		80
921.1Sjmcneill#define GCC_BLSP1_UART2_APPS_CLK		81
931.1Sjmcneill#define GCC_BLSP1_UART3_APPS_CLK		82
941.1Sjmcneill#define GCC_BLSP1_UART4_APPS_CLK		83
951.1Sjmcneill#define GCC_BLSP1_UART5_APPS_CLK		84
961.1Sjmcneill#define GCC_BLSP1_UART6_APPS_CLK		85
971.1Sjmcneill#define GCC_CRYPTO_AHB_CLK			86
981.1Sjmcneill#define GCC_CRYPTO_AXI_CLK			87
991.1Sjmcneill#define GCC_CRYPTO_CLK				88
1001.1Sjmcneill#define GCC_XO_CLK				89
1011.1Sjmcneill#define GCC_XO_DIV4_CLK				90
1021.1Sjmcneill#define GCC_MDIO_AHB_CLK			91
1031.1Sjmcneill#define GCC_CRYPTO_PPE_CLK			92
1041.1Sjmcneill#define GCC_NSS_CE_APB_CLK			93
1051.1Sjmcneill#define GCC_NSS_CE_AXI_CLK			94
1061.1Sjmcneill#define GCC_NSS_CFG_CLK				95
1071.1Sjmcneill#define GCC_NSS_CRYPTO_CLK			96
1081.1Sjmcneill#define GCC_NSS_CSR_CLK				97
1091.1Sjmcneill#define GCC_NSS_EDMA_CFG_CLK			98
1101.1Sjmcneill#define GCC_NSS_EDMA_CLK			99
1111.1Sjmcneill#define GCC_NSS_NOC_CLK				100
1121.1Sjmcneill#define GCC_NSS_PORT1_RX_CLK			101
1131.1Sjmcneill#define GCC_NSS_PORT1_TX_CLK			102
1141.1Sjmcneill#define GCC_NSS_PORT2_RX_CLK			103
1151.1Sjmcneill#define GCC_NSS_PORT2_TX_CLK			104
1161.1Sjmcneill#define GCC_NSS_PORT3_RX_CLK			105
1171.1Sjmcneill#define GCC_NSS_PORT3_TX_CLK			106
1181.1Sjmcneill#define GCC_NSS_PORT4_RX_CLK			107
1191.1Sjmcneill#define GCC_NSS_PORT4_TX_CLK			108
1201.1Sjmcneill#define GCC_NSS_PORT5_RX_CLK			109
1211.1Sjmcneill#define GCC_NSS_PORT5_TX_CLK			110
1221.1Sjmcneill#define GCC_NSS_PPE_CFG_CLK			111
1231.1Sjmcneill#define GCC_NSS_PPE_CLK				112
1241.1Sjmcneill#define GCC_NSS_PPE_IPE_CLK			113
1251.1Sjmcneill#define GCC_NSS_PTP_REF_CLK			114
1261.1Sjmcneill#define GCC_NSSNOC_CE_APB_CLK			115
1271.1Sjmcneill#define GCC_NSSNOC_CE_AXI_CLK			116
1281.1Sjmcneill#define GCC_NSSNOC_CRYPTO_CLK			117
1291.1Sjmcneill#define GCC_NSSNOC_PPE_CFG_CLK			118
1301.1Sjmcneill#define GCC_NSSNOC_PPE_CLK			119
1311.1Sjmcneill#define GCC_NSSNOC_QOSGEN_REF_CLK		120
1321.1Sjmcneill#define GCC_NSSNOC_TIMEOUT_REF_CLK		121
1331.1Sjmcneill#define GCC_NSSNOC_UBI0_AHB_CLK			122
1341.1Sjmcneill#define GCC_PORT1_MAC_CLK			123
1351.1Sjmcneill#define GCC_PORT2_MAC_CLK			124
1361.1Sjmcneill#define GCC_PORT3_MAC_CLK			125
1371.1Sjmcneill#define GCC_PORT4_MAC_CLK			126
1381.1Sjmcneill#define GCC_PORT5_MAC_CLK			127
1391.1Sjmcneill#define GCC_UBI0_AHB_CLK			128
1401.1Sjmcneill#define GCC_UBI0_AXI_CLK			129
1411.1Sjmcneill#define GCC_UBI0_CORE_CLK			130
1421.1Sjmcneill#define GCC_PCIE0_AHB_CLK			131
1431.1Sjmcneill#define GCC_PCIE0_AUX_CLK			132
1441.1Sjmcneill#define GCC_PCIE0_AXI_M_CLK			133
1451.1Sjmcneill#define GCC_PCIE0_AXI_S_CLK			134
1461.1Sjmcneill#define GCC_PCIE0_PIPE_CLK			135
1471.1Sjmcneill#define GCC_PRNG_AHB_CLK			136
1481.1Sjmcneill#define GCC_QPIC_AHB_CLK			137
1491.1Sjmcneill#define GCC_QPIC_CLK				138
1501.1Sjmcneill#define GCC_SDCC1_AHB_CLK			139
1511.1Sjmcneill#define GCC_SDCC1_APPS_CLK			140
1521.1Sjmcneill#define GCC_UNIPHY0_AHB_CLK			141
1531.1Sjmcneill#define GCC_UNIPHY0_PORT1_RX_CLK		142
1541.1Sjmcneill#define GCC_UNIPHY0_PORT1_TX_CLK		143
1551.1Sjmcneill#define GCC_UNIPHY0_PORT2_RX_CLK		144
1561.1Sjmcneill#define GCC_UNIPHY0_PORT2_TX_CLK		145
1571.1Sjmcneill#define GCC_UNIPHY0_PORT3_RX_CLK		146
1581.1Sjmcneill#define GCC_UNIPHY0_PORT3_TX_CLK		147
1591.1Sjmcneill#define GCC_UNIPHY0_PORT4_RX_CLK		148
1601.1Sjmcneill#define GCC_UNIPHY0_PORT4_TX_CLK		149
1611.1Sjmcneill#define GCC_UNIPHY0_PORT5_RX_CLK		150
1621.1Sjmcneill#define GCC_UNIPHY0_PORT5_TX_CLK		151
1631.1Sjmcneill#define GCC_UNIPHY0_SYS_CLK			152
1641.1Sjmcneill#define GCC_UNIPHY1_AHB_CLK			153
1651.1Sjmcneill#define GCC_UNIPHY1_PORT5_RX_CLK		154
1661.1Sjmcneill#define GCC_UNIPHY1_PORT5_TX_CLK		155
1671.1Sjmcneill#define GCC_UNIPHY1_SYS_CLK			156
1681.1Sjmcneill#define GCC_USB0_AUX_CLK			157
1691.1Sjmcneill#define GCC_USB0_MASTER_CLK			158
1701.1Sjmcneill#define GCC_USB0_MOCK_UTMI_CLK			159
1711.1Sjmcneill#define GCC_USB0_PHY_CFG_AHB_CLK		160
1721.1Sjmcneill#define GCC_USB0_PIPE_CLK			161
1731.1Sjmcneill#define GCC_USB0_SLEEP_CLK			162
1741.1Sjmcneill#define GCC_USB1_MASTER_CLK			163
1751.1Sjmcneill#define GCC_USB1_MOCK_UTMI_CLK			164
1761.1Sjmcneill#define GCC_USB1_PHY_CFG_AHB_CLK		165
1771.1Sjmcneill#define GCC_USB1_SLEEP_CLK			166
1781.1Sjmcneill#define GP1_CLK_SRC				167
1791.1Sjmcneill#define GP2_CLK_SRC				168
1801.1Sjmcneill#define GP3_CLK_SRC				169
1811.1Sjmcneill#define GCC_GP1_CLK				170
1821.1Sjmcneill#define GCC_GP2_CLK				171
1831.1Sjmcneill#define GCC_GP3_CLK				172
1841.1Sjmcneill#define SYSTEM_NOC_BFDCD_CLK_SRC		173
1851.1Sjmcneill#define GCC_NSSNOC_SNOC_CLK			174
1861.1Sjmcneill#define GCC_UBI0_NC_AXI_CLK			175
1871.1Sjmcneill#define GCC_UBI1_NC_AXI_CLK			176
1881.1Sjmcneill#define GPLL0_MAIN				177
1891.1Sjmcneill#define UBI32_PLL_MAIN				178
1901.1Sjmcneill#define GPLL6_MAIN				179
1911.1Sjmcneill#define GPLL4_MAIN				180
1921.1Sjmcneill#define GPLL2_MAIN				181
1931.1Sjmcneill#define NSS_CRYPTO_PLL_MAIN			182
1941.1Sjmcneill#define GCC_CMN_12GPLL_AHB_CLK			183
1951.1Sjmcneill#define GCC_CMN_12GPLL_SYS_CLK			184
1961.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK		185
1971.1Sjmcneill#define GCC_SYS_NOC_USB0_AXI_CLK		186
1981.1Sjmcneill#define GCC_SYS_NOC_PCIE0_AXI_CLK		187
1991.1Sjmcneill#define QDSS_TSCTR_CLK_SRC			188
2001.1Sjmcneill#define QDSS_AT_CLK_SRC				189
2011.1Sjmcneill#define GCC_QDSS_AT_CLK				190
2021.1Sjmcneill#define GCC_QDSS_DAP_CLK			191
2031.1Sjmcneill#define ADSS_PWM_CLK_SRC			192
2041.1Sjmcneill#define GCC_ADSS_PWM_CLK			193
2051.1Sjmcneill#define SDCC1_ICE_CORE_CLK_SRC			194
2061.1Sjmcneill#define GCC_SDCC1_ICE_CORE_CLK			195
2071.1Sjmcneill#define GCC_DCC_CLK				196
2081.1Sjmcneill#define PCIE0_RCHNG_CLK_SRC			197
2091.1Sjmcneill#define GCC_PCIE0_AXI_S_BRIDGE_CLK		198
2101.1Sjmcneill#define PCIE0_RCHNG_CLK				199
2111.1Sjmcneill#define UBI32_MEM_NOC_BFDCD_CLK_SRC		200
2121.1Sjmcneill#define WCSS_AHB_CLK_SRC			201
2131.1Sjmcneill#define Q6_AXI_CLK_SRC				202
2141.1Sjmcneill#define GCC_Q6SS_PCLKDBG_CLK			203
2151.1Sjmcneill#define GCC_Q6_TSCTR_1TO2_CLK			204
2161.1Sjmcneill#define GCC_WCSS_CORE_TBU_CLK			205
2171.1Sjmcneill#define GCC_WCSS_AXI_M_CLK			206
2181.1Sjmcneill#define GCC_SYS_NOC_WCSS_AHB_CLK		207
2191.1Sjmcneill#define GCC_Q6_AXIM_CLK				208
2201.1Sjmcneill#define GCC_Q6SS_ATBM_CLK			209
2211.1Sjmcneill#define GCC_WCSS_Q6_TBU_CLK			210
2221.1Sjmcneill#define GCC_Q6_AXIM2_CLK			211
2231.1Sjmcneill#define GCC_Q6_AHB_CLK				212
2241.1Sjmcneill#define GCC_Q6_AHB_S_CLK			213
2251.1Sjmcneill#define GCC_WCSS_DBG_IFC_APB_CLK		214
2261.1Sjmcneill#define GCC_WCSS_DBG_IFC_ATB_CLK		215
2271.1Sjmcneill#define GCC_WCSS_DBG_IFC_NTS_CLK		216
2281.1Sjmcneill#define GCC_WCSS_DBG_IFC_DAPBUS_CLK		217
2291.1Sjmcneill#define GCC_WCSS_DBG_IFC_APB_BDG_CLK		218
2301.1Sjmcneill#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK		219
2311.1Sjmcneill#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK		220
2321.1Sjmcneill#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK		221
2331.1Sjmcneill#define GCC_WCSS_ECAHB_CLK			222
2341.1Sjmcneill#define GCC_WCSS_ACMT_CLK			223
2351.1Sjmcneill#define GCC_WCSS_AHB_S_CLK			224
2361.1Sjmcneill#define GCC_RBCPR_WCSS_CLK			225
2371.1Sjmcneill#define RBCPR_WCSS_CLK_SRC			226
2381.1Sjmcneill#define GCC_RBCPR_WCSS_AHB_CLK			227
2391.1Sjmcneill#define GCC_LPASS_CORE_AXIM_CLK			228
2401.1Sjmcneill#define GCC_LPASS_SNOC_CFG_CLK			229
2411.1Sjmcneill#define GCC_LPASS_Q6_AXIM_CLK			230
2421.1Sjmcneill#define GCC_LPASS_Q6_ATBM_AT_CLK		231
2431.1Sjmcneill#define GCC_LPASS_Q6_PCLKDBG_CLK		232
2441.1Sjmcneill#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK		233
2451.1Sjmcneill#define GCC_LPASS_Q6SS_TRIG_CLK			234
2461.1Sjmcneill#define GCC_LPASS_TBU_CLK			235
2471.1Sjmcneill#define LPASS_CORE_AXIM_CLK_SRC			236
2481.1Sjmcneill#define LPASS_SNOC_CFG_CLK_SRC			237
2491.1Sjmcneill#define LPASS_Q6_AXIM_CLK_SRC			238
2501.1Sjmcneill#define GCC_PCNOC_LPASS_CLK			239
2511.1Sjmcneill#define GCC_UBI0_UTCM_CLK			240
2521.1Sjmcneill#define SNOC_NSSNOC_BFDCD_CLK_SRC		241
2531.1Sjmcneill#define GCC_SNOC_NSSNOC_CLK			242
2541.1Sjmcneill#define GCC_MEM_NOC_Q6_AXI_CLK			243
2551.1Sjmcneill#define GCC_MEM_NOC_UBI32_CLK			244
2561.1Sjmcneill#define GCC_MEM_NOC_LPASS_CLK			245
2571.1Sjmcneill#define GCC_SNOC_LPASS_CFG_CLK			246
2581.1Sjmcneill#define GCC_SYS_NOC_QDSS_STM_AXI_CLK		247
2591.1Sjmcneill#define GCC_QDSS_STM_CLK			248
2601.1Sjmcneill#define GCC_QDSS_TRACECLKIN_CLK			249
2611.1Sjmcneill#define QDSS_STM_CLK_SRC			250
2621.1Sjmcneill#define QDSS_TRACECLKIN_CLK_SRC			251
2631.1Sjmcneill#define GCC_NSSNOC_ATB_CLK			252
2641.1Sjmcneill#endif
265