qcom,gcc-ipq806x.h revision 1.1.1.1
1/* $NetBSD: qcom,gcc-ipq806x.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H 17#define _DT_BINDINGS_CLK_GCC_IPQ806X_H 18 19#define AFAB_CLK_SRC 0 20#define QDSS_STM_CLK 1 21#define SCSS_A_CLK 2 22#define SCSS_H_CLK 3 23#define AFAB_CORE_CLK 4 24#define SCSS_XO_SRC_CLK 5 25#define AFAB_EBI1_CH0_A_CLK 6 26#define AFAB_EBI1_CH1_A_CLK 7 27#define AFAB_AXI_S0_FCLK 8 28#define AFAB_AXI_S1_FCLK 9 29#define AFAB_AXI_S2_FCLK 10 30#define AFAB_AXI_S3_FCLK 11 31#define AFAB_AXI_S4_FCLK 12 32#define SFAB_CORE_CLK 13 33#define SFAB_AXI_S0_FCLK 14 34#define SFAB_AXI_S1_FCLK 15 35#define SFAB_AXI_S2_FCLK 16 36#define SFAB_AXI_S3_FCLK 17 37#define SFAB_AXI_S4_FCLK 18 38#define SFAB_AXI_S5_FCLK 19 39#define SFAB_AHB_S0_FCLK 20 40#define SFAB_AHB_S1_FCLK 21 41#define SFAB_AHB_S2_FCLK 22 42#define SFAB_AHB_S3_FCLK 23 43#define SFAB_AHB_S4_FCLK 24 44#define SFAB_AHB_S5_FCLK 25 45#define SFAB_AHB_S6_FCLK 26 46#define SFAB_AHB_S7_FCLK 27 47#define QDSS_AT_CLK_SRC 28 48#define QDSS_AT_CLK 29 49#define QDSS_TRACECLKIN_CLK_SRC 30 50#define QDSS_TRACECLKIN_CLK 31 51#define QDSS_TSCTR_CLK_SRC 32 52#define QDSS_TSCTR_CLK 33 53#define SFAB_ADM0_M0_A_CLK 34 54#define SFAB_ADM0_M1_A_CLK 35 55#define SFAB_ADM0_M2_H_CLK 36 56#define ADM0_CLK 37 57#define ADM0_PBUS_CLK 38 58#define IMEM0_A_CLK 39 59#define QDSS_H_CLK 40 60#define PCIE_A_CLK 41 61#define PCIE_AUX_CLK 42 62#define PCIE_H_CLK 43 63#define PCIE_PHY_CLK 44 64#define SFAB_CLK_SRC 45 65#define SFAB_LPASS_Q6_A_CLK 46 66#define SFAB_AFAB_M_A_CLK 47 67#define AFAB_SFAB_M0_A_CLK 48 68#define AFAB_SFAB_M1_A_CLK 49 69#define SFAB_SATA_S_H_CLK 50 70#define DFAB_CLK_SRC 51 71#define DFAB_CLK 52 72#define SFAB_DFAB_M_A_CLK 53 73#define DFAB_SFAB_M_A_CLK 54 74#define DFAB_SWAY0_H_CLK 55 75#define DFAB_SWAY1_H_CLK 56 76#define DFAB_ARB0_H_CLK 57 77#define DFAB_ARB1_H_CLK 58 78#define PPSS_H_CLK 59 79#define PPSS_PROC_CLK 60 80#define PPSS_TIMER0_CLK 61 81#define PPSS_TIMER1_CLK 62 82#define PMEM_A_CLK 63 83#define DMA_BAM_H_CLK 64 84#define SIC_H_CLK 65 85#define SPS_TIC_H_CLK 66 86#define CFPB_2X_CLK_SRC 67 87#define CFPB_CLK 68 88#define CFPB0_H_CLK 69 89#define CFPB1_H_CLK 70 90#define CFPB2_H_CLK 71 91#define SFAB_CFPB_M_H_CLK 72 92#define CFPB_MASTER_H_CLK 73 93#define SFAB_CFPB_S_H_CLK 74 94#define CFPB_SPLITTER_H_CLK 75 95#define TSIF_H_CLK 76 96#define TSIF_INACTIVITY_TIMERS_CLK 77 97#define TSIF_REF_SRC 78 98#define TSIF_REF_CLK 79 99#define CE1_H_CLK 80 100#define CE1_CORE_CLK 81 101#define CE1_SLEEP_CLK 82 102#define CE2_H_CLK 83 103#define CE2_CORE_CLK 84 104#define SFPB_H_CLK_SRC 85 105#define SFPB_H_CLK 86 106#define SFAB_SFPB_M_H_CLK 87 107#define SFAB_SFPB_S_H_CLK 88 108#define RPM_PROC_CLK 89 109#define RPM_BUS_H_CLK 90 110#define RPM_SLEEP_CLK 91 111#define RPM_TIMER_CLK 92 112#define RPM_MSG_RAM_H_CLK 93 113#define PMIC_ARB0_H_CLK 94 114#define PMIC_ARB1_H_CLK 95 115#define PMIC_SSBI2_SRC 96 116#define PMIC_SSBI2_CLK 97 117#define SDC1_H_CLK 98 118#define SDC2_H_CLK 99 119#define SDC3_H_CLK 100 120#define SDC4_H_CLK 101 121#define SDC1_SRC 102 122#define SDC1_CLK 103 123#define SDC2_SRC 104 124#define SDC2_CLK 105 125#define SDC3_SRC 106 126#define SDC3_CLK 107 127#define SDC4_SRC 108 128#define SDC4_CLK 109 129#define USB_HS1_H_CLK 110 130#define USB_HS1_XCVR_SRC 111 131#define USB_HS1_XCVR_CLK 112 132#define USB_HSIC_H_CLK 113 133#define USB_HSIC_XCVR_SRC 114 134#define USB_HSIC_XCVR_CLK 115 135#define USB_HSIC_SYSTEM_CLK_SRC 116 136#define USB_HSIC_SYSTEM_CLK 117 137#define CFPB0_C0_H_CLK 118 138#define CFPB0_D0_H_CLK 119 139#define CFPB0_C1_H_CLK 120 140#define CFPB0_D1_H_CLK 121 141#define USB_FS1_H_CLK 122 142#define USB_FS1_XCVR_SRC 123 143#define USB_FS1_XCVR_CLK 124 144#define USB_FS1_SYSTEM_CLK 125 145#define GSBI_COMMON_SIM_SRC 126 146#define GSBI1_H_CLK 127 147#define GSBI2_H_CLK 128 148#define GSBI3_H_CLK 129 149#define GSBI4_H_CLK 130 150#define GSBI5_H_CLK 131 151#define GSBI6_H_CLK 132 152#define GSBI7_H_CLK 133 153#define GSBI1_QUP_SRC 134 154#define GSBI1_QUP_CLK 135 155#define GSBI2_QUP_SRC 136 156#define GSBI2_QUP_CLK 137 157#define GSBI3_QUP_SRC 138 158#define GSBI3_QUP_CLK 139 159#define GSBI4_QUP_SRC 140 160#define GSBI4_QUP_CLK 141 161#define GSBI5_QUP_SRC 142 162#define GSBI5_QUP_CLK 143 163#define GSBI6_QUP_SRC 144 164#define GSBI6_QUP_CLK 145 165#define GSBI7_QUP_SRC 146 166#define GSBI7_QUP_CLK 147 167#define GSBI1_UART_SRC 148 168#define GSBI1_UART_CLK 149 169#define GSBI2_UART_SRC 150 170#define GSBI2_UART_CLK 151 171#define GSBI3_UART_SRC 152 172#define GSBI3_UART_CLK 153 173#define GSBI4_UART_SRC 154 174#define GSBI4_UART_CLK 155 175#define GSBI5_UART_SRC 156 176#define GSBI5_UART_CLK 157 177#define GSBI6_UART_SRC 158 178#define GSBI6_UART_CLK 159 179#define GSBI7_UART_SRC 160 180#define GSBI7_UART_CLK 161 181#define GSBI1_SIM_CLK 162 182#define GSBI2_SIM_CLK 163 183#define GSBI3_SIM_CLK 164 184#define GSBI4_SIM_CLK 165 185#define GSBI5_SIM_CLK 166 186#define GSBI6_SIM_CLK 167 187#define GSBI7_SIM_CLK 168 188#define USB_HSIC_HSIC_CLK_SRC 169 189#define USB_HSIC_HSIC_CLK 170 190#define USB_HSIC_HSIO_CAL_CLK 171 191#define SPDM_CFG_H_CLK 172 192#define SPDM_MSTR_H_CLK 173 193#define SPDM_FF_CLK_SRC 174 194#define SPDM_FF_CLK 175 195#define SEC_CTRL_CLK 176 196#define SEC_CTRL_ACC_CLK_SRC 177 197#define SEC_CTRL_ACC_CLK 178 198#define TLMM_H_CLK 179 199#define TLMM_CLK 180 200#define SATA_H_CLK 181 201#define SATA_CLK_SRC 182 202#define SATA_RXOOB_CLK 183 203#define SATA_PMALIVE_CLK 184 204#define SATA_PHY_REF_CLK 185 205#define SATA_A_CLK 186 206#define SATA_PHY_CFG_CLK 187 207#define TSSC_CLK_SRC 188 208#define TSSC_CLK 189 209#define PDM_SRC 190 210#define PDM_CLK 191 211#define GP0_SRC 192 212#define GP0_CLK 193 213#define GP1_SRC 194 214#define GP1_CLK 195 215#define GP2_SRC 196 216#define GP2_CLK 197 217#define MPM_CLK 198 218#define EBI1_CLK_SRC 199 219#define EBI1_CH0_CLK 200 220#define EBI1_CH1_CLK 201 221#define EBI1_2X_CLK 202 222#define EBI1_CH0_DQ_CLK 203 223#define EBI1_CH1_DQ_CLK 204 224#define EBI1_CH0_CA_CLK 205 225#define EBI1_CH1_CA_CLK 206 226#define EBI1_XO_CLK 207 227#define SFAB_SMPSS_S_H_CLK 208 228#define PRNG_SRC 209 229#define PRNG_CLK 210 230#define PXO_SRC 211 231#define SPDM_CY_PORT0_CLK 212 232#define SPDM_CY_PORT1_CLK 213 233#define SPDM_CY_PORT2_CLK 214 234#define SPDM_CY_PORT3_CLK 215 235#define SPDM_CY_PORT4_CLK 216 236#define SPDM_CY_PORT5_CLK 217 237#define SPDM_CY_PORT6_CLK 218 238#define SPDM_CY_PORT7_CLK 219 239#define PLL0 220 240#define PLL0_VOTE 221 241#define PLL3 222 242#define PLL3_VOTE 223 243#define PLL4_VOTE 225 244#define PLL8 226 245#define PLL8_VOTE 227 246#define PLL9 228 247#define PLL10 229 248#define PLL11 230 249#define PLL12 231 250#define PLL14 232 251#define PLL14_VOTE 233 252#define PLL18 234 253#define CE5_SRC 235 254#define CE5_H_CLK 236 255#define CE5_CORE_CLK 237 256#define CE3_SLEEP_CLK 238 257#define SFAB_AHB_S8_FCLK 239 258#define SPDM_CY_PORT8_CLK 246 259#define PCIE_ALT_REF_SRC 247 260#define PCIE_ALT_REF_CLK 248 261#define PCIE_1_A_CLK 249 262#define PCIE_1_AUX_CLK 250 263#define PCIE_1_H_CLK 251 264#define PCIE_1_PHY_CLK 252 265#define PCIE_1_ALT_REF_SRC 253 266#define PCIE_1_ALT_REF_CLK 254 267#define PCIE_2_A_CLK 255 268#define PCIE_2_AUX_CLK 256 269#define PCIE_2_H_CLK 257 270#define PCIE_2_PHY_CLK 258 271#define PCIE_2_ALT_REF_SRC 259 272#define PCIE_2_ALT_REF_CLK 260 273#define EBI2_CLK 261 274#define USB30_SLEEP_CLK 262 275#define USB30_UTMI_SRC 263 276#define USB30_0_UTMI_CLK 264 277#define USB30_1_UTMI_CLK 265 278#define USB30_MASTER_SRC 266 279#define USB30_0_MASTER_CLK 267 280#define USB30_1_MASTER_CLK 268 281#define GMAC_CORE1_CLK_SRC 269 282#define GMAC_CORE2_CLK_SRC 270 283#define GMAC_CORE3_CLK_SRC 271 284#define GMAC_CORE4_CLK_SRC 272 285#define GMAC_CORE1_CLK 273 286#define GMAC_CORE2_CLK 274 287#define GMAC_CORE3_CLK 275 288#define GMAC_CORE4_CLK 276 289#define UBI32_CORE1_CLK_SRC 277 290#define UBI32_CORE2_CLK_SRC 278 291#define UBI32_CORE1_CLK 279 292#define UBI32_CORE2_CLK 280 293#define EBI2_AON_CLK 281 294#define NSSTCM_CLK_SRC 282 295#define NSSTCM_CLK 283 296 297#endif 298