qcom,gcc-mdm9615.h revision 1.1.1.1
1/* $NetBSD: qcom,gcc-mdm9615.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 * Copyright (c) BayLibre, SAS. 6 * Author : Neil Armstrong <narmstrong@baylibre.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H 19#define _DT_BINDINGS_CLK_MDM_GCC_9615_H 20 21#define AFAB_CLK_SRC 0 22#define AFAB_CORE_CLK 1 23#define SFAB_MSS_Q6_SW_A_CLK 2 24#define SFAB_MSS_Q6_FW_A_CLK 3 25#define QDSS_STM_CLK 4 26#define SCSS_A_CLK 5 27#define SCSS_H_CLK 6 28#define SCSS_XO_SRC_CLK 7 29#define AFAB_EBI1_CH0_A_CLK 8 30#define AFAB_EBI1_CH1_A_CLK 9 31#define AFAB_AXI_S0_FCLK 10 32#define AFAB_AXI_S1_FCLK 11 33#define AFAB_AXI_S2_FCLK 12 34#define AFAB_AXI_S3_FCLK 13 35#define AFAB_AXI_S4_FCLK 14 36#define SFAB_CORE_CLK 15 37#define SFAB_AXI_S0_FCLK 16 38#define SFAB_AXI_S1_FCLK 17 39#define SFAB_AXI_S2_FCLK 18 40#define SFAB_AXI_S3_FCLK 19 41#define SFAB_AXI_S4_FCLK 20 42#define SFAB_AHB_S0_FCLK 21 43#define SFAB_AHB_S1_FCLK 22 44#define SFAB_AHB_S2_FCLK 23 45#define SFAB_AHB_S3_FCLK 24 46#define SFAB_AHB_S4_FCLK 25 47#define SFAB_AHB_S5_FCLK 26 48#define SFAB_AHB_S6_FCLK 27 49#define SFAB_AHB_S7_FCLK 28 50#define QDSS_AT_CLK_SRC 29 51#define QDSS_AT_CLK 30 52#define QDSS_TRACECLKIN_CLK_SRC 31 53#define QDSS_TRACECLKIN_CLK 32 54#define QDSS_TSCTR_CLK_SRC 33 55#define QDSS_TSCTR_CLK 34 56#define SFAB_ADM0_M0_A_CLK 35 57#define SFAB_ADM0_M1_A_CLK 36 58#define SFAB_ADM0_M2_H_CLK 37 59#define ADM0_CLK 38 60#define ADM0_PBUS_CLK 39 61#define MSS_XPU_CLK 40 62#define IMEM0_A_CLK 41 63#define QDSS_H_CLK 42 64#define PCIE_A_CLK 43 65#define PCIE_AUX_CLK 44 66#define PCIE_PHY_REF_CLK 45 67#define PCIE_H_CLK 46 68#define SFAB_CLK_SRC 47 69#define MAHB0_CLK 48 70#define Q6SW_CLK_SRC 49 71#define Q6SW_CLK 50 72#define Q6FW_CLK_SRC 51 73#define Q6FW_CLK 52 74#define SFAB_MSS_M_A_CLK 53 75#define SFAB_USB3_M_A_CLK 54 76#define SFAB_LPASS_Q6_A_CLK 55 77#define SFAB_AFAB_M_A_CLK 56 78#define AFAB_SFAB_M0_A_CLK 57 79#define AFAB_SFAB_M1_A_CLK 58 80#define SFAB_SATA_S_H_CLK 59 81#define DFAB_CLK_SRC 60 82#define DFAB_CLK 61 83#define SFAB_DFAB_M_A_CLK 62 84#define DFAB_SFAB_M_A_CLK 63 85#define DFAB_SWAY0_H_CLK 64 86#define DFAB_SWAY1_H_CLK 65 87#define DFAB_ARB0_H_CLK 66 88#define DFAB_ARB1_H_CLK 67 89#define PPSS_H_CLK 68 90#define PPSS_PROC_CLK 69 91#define PPSS_TIMER0_CLK 70 92#define PPSS_TIMER1_CLK 71 93#define PMEM_A_CLK 72 94#define DMA_BAM_H_CLK 73 95#define SIC_H_CLK 74 96#define SPS_TIC_H_CLK 75 97#define SLIMBUS_H_CLK 76 98#define SLIMBUS_XO_SRC_CLK 77 99#define CFPB_2X_CLK_SRC 78 100#define CFPB_CLK 79 101#define CFPB0_H_CLK 80 102#define CFPB1_H_CLK 81 103#define CFPB2_H_CLK 82 104#define SFAB_CFPB_M_H_CLK 83 105#define CFPB_MASTER_H_CLK 84 106#define SFAB_CFPB_S_H_CLK 85 107#define CFPB_SPLITTER_H_CLK 86 108#define TSIF_H_CLK 87 109#define TSIF_INACTIVITY_TIMERS_CLK 88 110#define TSIF_REF_SRC 89 111#define TSIF_REF_CLK 90 112#define CE1_H_CLK 91 113#define CE1_CORE_CLK 92 114#define CE1_SLEEP_CLK 93 115#define CE2_H_CLK 94 116#define CE2_CORE_CLK 95 117#define SFPB_H_CLK_SRC 97 118#define SFPB_H_CLK 98 119#define SFAB_SFPB_M_H_CLK 99 120#define SFAB_SFPB_S_H_CLK 100 121#define RPM_PROC_CLK 101 122#define RPM_BUS_H_CLK 102 123#define RPM_SLEEP_CLK 103 124#define RPM_TIMER_CLK 104 125#define RPM_MSG_RAM_H_CLK 105 126#define PMIC_ARB0_H_CLK 106 127#define PMIC_ARB1_H_CLK 107 128#define PMIC_SSBI2_SRC 108 129#define PMIC_SSBI2_CLK 109 130#define SDC1_H_CLK 110 131#define SDC2_H_CLK 111 132#define SDC3_H_CLK 112 133#define SDC4_H_CLK 113 134#define SDC5_H_CLK 114 135#define SDC1_SRC 115 136#define SDC2_SRC 116 137#define SDC3_SRC 117 138#define SDC4_SRC 118 139#define SDC5_SRC 119 140#define SDC1_CLK 120 141#define SDC2_CLK 121 142#define SDC3_CLK 122 143#define SDC4_CLK 123 144#define SDC5_CLK 124 145#define DFAB_A2_H_CLK 125 146#define USB_HS1_H_CLK 126 147#define USB_HS1_XCVR_SRC 127 148#define USB_HS1_XCVR_CLK 128 149#define USB_HSIC_H_CLK 129 150#define USB_HSIC_XCVR_FS_SRC 130 151#define USB_HSIC_XCVR_FS_CLK 131 152#define USB_HSIC_SYSTEM_CLK_SRC 132 153#define USB_HSIC_SYSTEM_CLK 133 154#define CFPB0_C0_H_CLK 134 155#define CFPB0_C1_H_CLK 135 156#define CFPB0_D0_H_CLK 136 157#define CFPB0_D1_H_CLK 137 158#define USB_FS1_H_CLK 138 159#define USB_FS1_XCVR_FS_SRC 139 160#define USB_FS1_XCVR_FS_CLK 140 161#define USB_FS1_SYSTEM_CLK 141 162#define USB_FS2_H_CLK 142 163#define USB_FS2_XCVR_FS_SRC 143 164#define USB_FS2_XCVR_FS_CLK 144 165#define USB_FS2_SYSTEM_CLK 145 166#define GSBI_COMMON_SIM_SRC 146 167#define GSBI1_H_CLK 147 168#define GSBI2_H_CLK 148 169#define GSBI3_H_CLK 149 170#define GSBI4_H_CLK 150 171#define GSBI5_H_CLK 151 172#define GSBI6_H_CLK 152 173#define GSBI7_H_CLK 153 174#define GSBI8_H_CLK 154 175#define GSBI9_H_CLK 155 176#define GSBI10_H_CLK 156 177#define GSBI11_H_CLK 157 178#define GSBI12_H_CLK 158 179#define GSBI1_UART_SRC 159 180#define GSBI1_UART_CLK 160 181#define GSBI2_UART_SRC 161 182#define GSBI2_UART_CLK 162 183#define GSBI3_UART_SRC 163 184#define GSBI3_UART_CLK 164 185#define GSBI4_UART_SRC 165 186#define GSBI4_UART_CLK 166 187#define GSBI5_UART_SRC 167 188#define GSBI5_UART_CLK 168 189#define GSBI6_UART_SRC 169 190#define GSBI6_UART_CLK 170 191#define GSBI7_UART_SRC 171 192#define GSBI7_UART_CLK 172 193#define GSBI8_UART_SRC 173 194#define GSBI8_UART_CLK 174 195#define GSBI9_UART_SRC 175 196#define GSBI9_UART_CLK 176 197#define GSBI10_UART_SRC 177 198#define GSBI10_UART_CLK 178 199#define GSBI11_UART_SRC 179 200#define GSBI11_UART_CLK 180 201#define GSBI12_UART_SRC 181 202#define GSBI12_UART_CLK 182 203#define GSBI1_QUP_SRC 183 204#define GSBI1_QUP_CLK 184 205#define GSBI2_QUP_SRC 185 206#define GSBI2_QUP_CLK 186 207#define GSBI3_QUP_SRC 187 208#define GSBI3_QUP_CLK 188 209#define GSBI4_QUP_SRC 189 210#define GSBI4_QUP_CLK 190 211#define GSBI5_QUP_SRC 191 212#define GSBI5_QUP_CLK 192 213#define GSBI6_QUP_SRC 193 214#define GSBI6_QUP_CLK 194 215#define GSBI7_QUP_SRC 195 216#define GSBI7_QUP_CLK 196 217#define GSBI8_QUP_SRC 197 218#define GSBI8_QUP_CLK 198 219#define GSBI9_QUP_SRC 199 220#define GSBI9_QUP_CLK 200 221#define GSBI10_QUP_SRC 201 222#define GSBI10_QUP_CLK 202 223#define GSBI11_QUP_SRC 203 224#define GSBI11_QUP_CLK 204 225#define GSBI12_QUP_SRC 205 226#define GSBI12_QUP_CLK 206 227#define GSBI1_SIM_CLK 207 228#define GSBI2_SIM_CLK 208 229#define GSBI3_SIM_CLK 209 230#define GSBI4_SIM_CLK 210 231#define GSBI5_SIM_CLK 211 232#define GSBI6_SIM_CLK 212 233#define GSBI7_SIM_CLK 213 234#define GSBI8_SIM_CLK 214 235#define GSBI9_SIM_CLK 215 236#define GSBI10_SIM_CLK 216 237#define GSBI11_SIM_CLK 217 238#define GSBI12_SIM_CLK 218 239#define USB_HSIC_HSIC_CLK_SRC 219 240#define USB_HSIC_HSIC_CLK 220 241#define USB_HSIC_HSIO_CAL_CLK 221 242#define SPDM_CFG_H_CLK 222 243#define SPDM_MSTR_H_CLK 223 244#define SPDM_FF_CLK_SRC 224 245#define SPDM_FF_CLK 225 246#define SEC_CTRL_CLK 226 247#define SEC_CTRL_ACC_CLK_SRC 227 248#define SEC_CTRL_ACC_CLK 228 249#define TLMM_H_CLK 229 250#define TLMM_CLK 230 251#define SFAB_MSS_S_H_CLK 231 252#define MSS_SLP_CLK 232 253#define MSS_Q6SW_JTAG_CLK 233 254#define MSS_Q6FW_JTAG_CLK 234 255#define MSS_S_H_CLK 235 256#define MSS_CXO_SRC_CLK 236 257#define SATA_H_CLK 237 258#define SATA_CLK_SRC 238 259#define SATA_RXOOB_CLK 239 260#define SATA_PMALIVE_CLK 240 261#define SATA_PHY_REF_CLK 241 262#define TSSC_CLK_SRC 242 263#define TSSC_CLK 243 264#define PDM_SRC 244 265#define PDM_CLK 245 266#define GP0_SRC 246 267#define GP0_CLK 247 268#define GP1_SRC 248 269#define GP1_CLK 249 270#define GP2_SRC 250 271#define GP2_CLK 251 272#define MPM_CLK 252 273#define EBI1_CLK_SRC 253 274#define EBI1_CH0_CLK 254 275#define EBI1_CH1_CLK 255 276#define EBI1_2X_CLK 256 277#define EBI1_CH0_DQ_CLK 257 278#define EBI1_CH1_DQ_CLK 258 279#define EBI1_CH0_CA_CLK 259 280#define EBI1_CH1_CA_CLK 260 281#define EBI1_XO_CLK 261 282#define SFAB_SMPSS_S_H_CLK 262 283#define PRNG_SRC 263 284#define PRNG_CLK 264 285#define PXO_SRC 265 286#define LPASS_CXO_CLK 266 287#define LPASS_PXO_CLK 267 288#define SPDM_CY_PORT0_CLK 268 289#define SPDM_CY_PORT1_CLK 269 290#define SPDM_CY_PORT2_CLK 270 291#define SPDM_CY_PORT3_CLK 271 292#define SPDM_CY_PORT4_CLK 272 293#define SPDM_CY_PORT5_CLK 273 294#define SPDM_CY_PORT6_CLK 274 295#define SPDM_CY_PORT7_CLK 275 296#define PLL0 276 297#define PLL0_VOTE 277 298#define PLL3 278 299#define PLL3_VOTE 279 300#define PLL4_VOTE 280 301#define PLL5 281 302#define PLL5_VOTE 282 303#define PLL6 283 304#define PLL6_VOTE 284 305#define PLL7_VOTE 285 306#define PLL8 286 307#define PLL8_VOTE 287 308#define PLL9 288 309#define PLL10 289 310#define PLL11 290 311#define PLL12 291 312#define PLL13 292 313#define PLL14 293 314#define PLL14_VOTE 294 315#define USB_HS3_H_CLK 295 316#define USB_HS3_XCVR_SRC 296 317#define USB_HS3_XCVR_CLK 297 318#define USB_HS4_H_CLK 298 319#define USB_HS4_XCVR_SRC 299 320#define USB_HS4_XCVR_CLK 300 321#define SATA_PHY_CFG_CLK 301 322#define SATA_A_CLK 302 323#define CE3_SRC 303 324#define CE3_CORE_CLK 304 325#define CE3_H_CLK 305 326#define USB_HS1_SYSTEM_CLK_SRC 306 327#define USB_HS1_SYSTEM_CLK 307 328#define EBI2_CLK 308 329#define EBI2_AON_CLK 309 330 331#endif 332