11.1Sjmcneill/*	$NetBSD: qcom,gcc-msm8974.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $	*/
21.1Sjmcneill
31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-only */
41.1Sjmcneill/*
51.1Sjmcneill * Copyright (c) 2013, The Linux Foundation. All rights reserved.
61.1Sjmcneill */
71.1Sjmcneill
81.1Sjmcneill#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H
91.1Sjmcneill#define _DT_BINDINGS_CLK_MSM_GCC_8974_H
101.1Sjmcneill
111.1Sjmcneill#define GPLL0							0
121.1Sjmcneill#define GPLL0_VOTE						1
131.1Sjmcneill#define CONFIG_NOC_CLK_SRC					2
141.1Sjmcneill#define GPLL2							3
151.1Sjmcneill#define GPLL2_VOTE						4
161.1Sjmcneill#define GPLL3							5
171.1Sjmcneill#define GPLL3_VOTE						6
181.1Sjmcneill#define PERIPH_NOC_CLK_SRC					7
191.1Sjmcneill#define BLSP_UART_SIM_CLK_SRC					8
201.1Sjmcneill#define QDSS_TSCTR_CLK_SRC					9
211.1Sjmcneill#define BIMC_DDR_CLK_SRC					10
221.1Sjmcneill#define SYSTEM_NOC_CLK_SRC					11
231.1Sjmcneill#define GPLL1							12
241.1Sjmcneill#define GPLL1_VOTE						13
251.1Sjmcneill#define RPM_CLK_SRC						14
261.1Sjmcneill#define GCC_BIMC_CLK						15
271.1Sjmcneill#define BIMC_DDR_CPLL0_ROOT_CLK_SRC				16
281.1Sjmcneill#define KPSS_AHB_CLK_SRC					17
291.1Sjmcneill#define QDSS_AT_CLK_SRC						18
301.1Sjmcneill#define USB30_MASTER_CLK_SRC					19
311.1Sjmcneill#define BIMC_DDR_CPLL1_ROOT_CLK_SRC				20
321.1Sjmcneill#define QDSS_STM_CLK_SRC					21
331.1Sjmcneill#define ACC_CLK_SRC						22
341.1Sjmcneill#define SEC_CTRL_CLK_SRC					23
351.1Sjmcneill#define BLSP1_QUP1_I2C_APPS_CLK_SRC				24
361.1Sjmcneill#define BLSP1_QUP1_SPI_APPS_CLK_SRC				25
371.1Sjmcneill#define BLSP1_QUP2_I2C_APPS_CLK_SRC				26
381.1Sjmcneill#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
391.1Sjmcneill#define BLSP1_QUP3_I2C_APPS_CLK_SRC				28
401.1Sjmcneill#define BLSP1_QUP3_SPI_APPS_CLK_SRC				29
411.1Sjmcneill#define BLSP1_QUP4_I2C_APPS_CLK_SRC				30
421.1Sjmcneill#define BLSP1_QUP4_SPI_APPS_CLK_SRC				31
431.1Sjmcneill#define BLSP1_QUP5_I2C_APPS_CLK_SRC				32
441.1Sjmcneill#define BLSP1_QUP5_SPI_APPS_CLK_SRC				33
451.1Sjmcneill#define BLSP1_QUP6_I2C_APPS_CLK_SRC				34
461.1Sjmcneill#define BLSP1_QUP6_SPI_APPS_CLK_SRC				35
471.1Sjmcneill#define BLSP1_UART1_APPS_CLK_SRC				36
481.1Sjmcneill#define BLSP1_UART2_APPS_CLK_SRC				37
491.1Sjmcneill#define BLSP1_UART3_APPS_CLK_SRC				38
501.1Sjmcneill#define BLSP1_UART4_APPS_CLK_SRC				39
511.1Sjmcneill#define BLSP1_UART5_APPS_CLK_SRC				40
521.1Sjmcneill#define BLSP1_UART6_APPS_CLK_SRC				41
531.1Sjmcneill#define BLSP2_QUP1_I2C_APPS_CLK_SRC				42
541.1Sjmcneill#define BLSP2_QUP1_SPI_APPS_CLK_SRC				43
551.1Sjmcneill#define BLSP2_QUP2_I2C_APPS_CLK_SRC				44
561.1Sjmcneill#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
571.1Sjmcneill#define BLSP2_QUP3_I2C_APPS_CLK_SRC				46
581.1Sjmcneill#define BLSP2_QUP3_SPI_APPS_CLK_SRC				47
591.1Sjmcneill#define BLSP2_QUP4_I2C_APPS_CLK_SRC				48
601.1Sjmcneill#define BLSP2_QUP4_SPI_APPS_CLK_SRC				49
611.1Sjmcneill#define BLSP2_QUP5_I2C_APPS_CLK_SRC				50
621.1Sjmcneill#define BLSP2_QUP5_SPI_APPS_CLK_SRC				51
631.1Sjmcneill#define BLSP2_QUP6_I2C_APPS_CLK_SRC				52
641.1Sjmcneill#define BLSP2_QUP6_SPI_APPS_CLK_SRC				53
651.1Sjmcneill#define BLSP2_UART1_APPS_CLK_SRC				54
661.1Sjmcneill#define BLSP2_UART2_APPS_CLK_SRC				55
671.1Sjmcneill#define BLSP2_UART3_APPS_CLK_SRC				56
681.1Sjmcneill#define BLSP2_UART4_APPS_CLK_SRC				57
691.1Sjmcneill#define BLSP2_UART5_APPS_CLK_SRC				58
701.1Sjmcneill#define BLSP2_UART6_APPS_CLK_SRC				59
711.1Sjmcneill#define CE1_CLK_SRC						60
721.1Sjmcneill#define CE2_CLK_SRC						61
731.1Sjmcneill#define GP1_CLK_SRC						62
741.1Sjmcneill#define GP2_CLK_SRC						63
751.1Sjmcneill#define GP3_CLK_SRC						64
761.1Sjmcneill#define PDM2_CLK_SRC						65
771.1Sjmcneill#define QDSS_TRACECLKIN_CLK_SRC					66
781.1Sjmcneill#define RBCPR_CLK_SRC						67
791.1Sjmcneill#define SDCC1_APPS_CLK_SRC					68
801.1Sjmcneill#define SDCC2_APPS_CLK_SRC					69
811.1Sjmcneill#define SDCC3_APPS_CLK_SRC					70
821.1Sjmcneill#define SDCC4_APPS_CLK_SRC					71
831.1Sjmcneill#define SPMI_AHB_CLK_SRC					72
841.1Sjmcneill#define SPMI_SER_CLK_SRC					73
851.1Sjmcneill#define TSIF_REF_CLK_SRC					74
861.1Sjmcneill#define USB30_MOCK_UTMI_CLK_SRC					75
871.1Sjmcneill#define USB_HS_SYSTEM_CLK_SRC					76
881.1Sjmcneill#define USB_HSIC_CLK_SRC					77
891.1Sjmcneill#define USB_HSIC_IO_CAL_CLK_SRC					78
901.1Sjmcneill#define USB_HSIC_SYSTEM_CLK_SRC					79
911.1Sjmcneill#define GCC_BAM_DMA_AHB_CLK					80
921.1Sjmcneill#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK			81
931.1Sjmcneill#define GCC_BIMC_CFG_AHB_CLK					82
941.1Sjmcneill#define GCC_BIMC_KPSS_AXI_CLK					83
951.1Sjmcneill#define GCC_BIMC_SLEEP_CLK					84
961.1Sjmcneill#define GCC_BIMC_SYSNOC_AXI_CLK					85
971.1Sjmcneill#define GCC_BIMC_XO_CLK						86
981.1Sjmcneill#define GCC_BLSP1_AHB_CLK					87
991.1Sjmcneill#define GCC_BLSP1_SLEEP_CLK					88
1001.1Sjmcneill#define GCC_BLSP1_QUP1_I2C_APPS_CLK				89
1011.1Sjmcneill#define GCC_BLSP1_QUP1_SPI_APPS_CLK				90
1021.1Sjmcneill#define GCC_BLSP1_QUP2_I2C_APPS_CLK				91
1031.1Sjmcneill#define GCC_BLSP1_QUP2_SPI_APPS_CLK				92
1041.1Sjmcneill#define GCC_BLSP1_QUP3_I2C_APPS_CLK				93
1051.1Sjmcneill#define GCC_BLSP1_QUP3_SPI_APPS_CLK				94
1061.1Sjmcneill#define GCC_BLSP1_QUP4_I2C_APPS_CLK				95
1071.1Sjmcneill#define GCC_BLSP1_QUP4_SPI_APPS_CLK				96
1081.1Sjmcneill#define GCC_BLSP1_QUP5_I2C_APPS_CLK				97
1091.1Sjmcneill#define GCC_BLSP1_QUP5_SPI_APPS_CLK				98
1101.1Sjmcneill#define GCC_BLSP1_QUP6_I2C_APPS_CLK				99
1111.1Sjmcneill#define GCC_BLSP1_QUP6_SPI_APPS_CLK				100
1121.1Sjmcneill#define GCC_BLSP1_UART1_APPS_CLK				101
1131.1Sjmcneill#define GCC_BLSP1_UART1_SIM_CLK					102
1141.1Sjmcneill#define GCC_BLSP1_UART2_APPS_CLK				103
1151.1Sjmcneill#define GCC_BLSP1_UART2_SIM_CLK					104
1161.1Sjmcneill#define GCC_BLSP1_UART3_APPS_CLK				105
1171.1Sjmcneill#define GCC_BLSP1_UART3_SIM_CLK					106
1181.1Sjmcneill#define GCC_BLSP1_UART4_APPS_CLK				107
1191.1Sjmcneill#define GCC_BLSP1_UART4_SIM_CLK					108
1201.1Sjmcneill#define GCC_BLSP1_UART5_APPS_CLK				109
1211.1Sjmcneill#define GCC_BLSP1_UART5_SIM_CLK					110
1221.1Sjmcneill#define GCC_BLSP1_UART6_APPS_CLK				111
1231.1Sjmcneill#define GCC_BLSP1_UART6_SIM_CLK					112
1241.1Sjmcneill#define GCC_BLSP2_AHB_CLK					113
1251.1Sjmcneill#define GCC_BLSP2_SLEEP_CLK					114
1261.1Sjmcneill#define GCC_BLSP2_QUP1_I2C_APPS_CLK				115
1271.1Sjmcneill#define GCC_BLSP2_QUP1_SPI_APPS_CLK				116
1281.1Sjmcneill#define GCC_BLSP2_QUP2_I2C_APPS_CLK				117
1291.1Sjmcneill#define GCC_BLSP2_QUP2_SPI_APPS_CLK				118
1301.1Sjmcneill#define GCC_BLSP2_QUP3_I2C_APPS_CLK				119
1311.1Sjmcneill#define GCC_BLSP2_QUP3_SPI_APPS_CLK				120
1321.1Sjmcneill#define GCC_BLSP2_QUP4_I2C_APPS_CLK				121
1331.1Sjmcneill#define GCC_BLSP2_QUP4_SPI_APPS_CLK				122
1341.1Sjmcneill#define GCC_BLSP2_QUP5_I2C_APPS_CLK				123
1351.1Sjmcneill#define GCC_BLSP2_QUP5_SPI_APPS_CLK				124
1361.1Sjmcneill#define GCC_BLSP2_QUP6_I2C_APPS_CLK				125
1371.1Sjmcneill#define GCC_BLSP2_QUP6_SPI_APPS_CLK				126
1381.1Sjmcneill#define GCC_BLSP2_UART1_APPS_CLK				127
1391.1Sjmcneill#define GCC_BLSP2_UART1_SIM_CLK					128
1401.1Sjmcneill#define GCC_BLSP2_UART2_APPS_CLK				129
1411.1Sjmcneill#define GCC_BLSP2_UART2_SIM_CLK					130
1421.1Sjmcneill#define GCC_BLSP2_UART3_APPS_CLK				131
1431.1Sjmcneill#define GCC_BLSP2_UART3_SIM_CLK					132
1441.1Sjmcneill#define GCC_BLSP2_UART4_APPS_CLK				133
1451.1Sjmcneill#define GCC_BLSP2_UART4_SIM_CLK					134
1461.1Sjmcneill#define GCC_BLSP2_UART5_APPS_CLK				135
1471.1Sjmcneill#define GCC_BLSP2_UART5_SIM_CLK					136
1481.1Sjmcneill#define GCC_BLSP2_UART6_APPS_CLK				137
1491.1Sjmcneill#define GCC_BLSP2_UART6_SIM_CLK					138
1501.1Sjmcneill#define GCC_BOOT_ROM_AHB_CLK					139
1511.1Sjmcneill#define GCC_CE1_AHB_CLK						140
1521.1Sjmcneill#define GCC_CE1_AXI_CLK						141
1531.1Sjmcneill#define GCC_CE1_CLK						142
1541.1Sjmcneill#define GCC_CE2_AHB_CLK						143
1551.1Sjmcneill#define GCC_CE2_AXI_CLK						144
1561.1Sjmcneill#define GCC_CE2_CLK						145
1571.1Sjmcneill#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK				146
1581.1Sjmcneill#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK				147
1591.1Sjmcneill#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK				148
1601.1Sjmcneill#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK				149
1611.1Sjmcneill#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK				150
1621.1Sjmcneill#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK				151
1631.1Sjmcneill#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK				152
1641.1Sjmcneill#define GCC_CFG_NOC_AHB_CLK					153
1651.1Sjmcneill#define GCC_CFG_NOC_DDR_CFG_CLK					154
1661.1Sjmcneill#define GCC_CFG_NOC_RPM_AHB_CLK					155
1671.1Sjmcneill#define GCC_BIMC_DDR_CPLL0_CLK					156
1681.1Sjmcneill#define GCC_BIMC_DDR_CPLL1_CLK					157
1691.1Sjmcneill#define GCC_DDR_DIM_CFG_CLK					158
1701.1Sjmcneill#define GCC_DDR_DIM_SLEEP_CLK					159
1711.1Sjmcneill#define GCC_DEHR_CLK						160
1721.1Sjmcneill#define GCC_AHB_CLK						161
1731.1Sjmcneill#define GCC_IM_SLEEP_CLK					162
1741.1Sjmcneill#define GCC_XO_CLK						163
1751.1Sjmcneill#define GCC_XO_DIV4_CLK						164
1761.1Sjmcneill#define GCC_GP1_CLK						165
1771.1Sjmcneill#define GCC_GP2_CLK						166
1781.1Sjmcneill#define GCC_GP3_CLK						167
1791.1Sjmcneill#define GCC_IMEM_AXI_CLK					168
1801.1Sjmcneill#define GCC_IMEM_CFG_AHB_CLK					169
1811.1Sjmcneill#define GCC_KPSS_AHB_CLK					170
1821.1Sjmcneill#define GCC_KPSS_AXI_CLK					171
1831.1Sjmcneill#define GCC_LPASS_Q6_AXI_CLK					172
1841.1Sjmcneill#define GCC_MMSS_NOC_AT_CLK					173
1851.1Sjmcneill#define GCC_MMSS_NOC_CFG_AHB_CLK				174
1861.1Sjmcneill#define GCC_OCMEM_NOC_CFG_AHB_CLK				175
1871.1Sjmcneill#define GCC_OCMEM_SYS_NOC_AXI_CLK				176
1881.1Sjmcneill#define GCC_MPM_AHB_CLK						177
1891.1Sjmcneill#define GCC_MSG_RAM_AHB_CLK					178
1901.1Sjmcneill#define GCC_MSS_CFG_AHB_CLK					179
1911.1Sjmcneill#define GCC_MSS_Q6_BIMC_AXI_CLK					180
1921.1Sjmcneill#define GCC_NOC_CONF_XPU_AHB_CLK				181
1931.1Sjmcneill#define GCC_PDM2_CLK						182
1941.1Sjmcneill#define GCC_PDM_AHB_CLK						183
1951.1Sjmcneill#define GCC_PDM_XO4_CLK						184
1961.1Sjmcneill#define GCC_PERIPH_NOC_AHB_CLK					185
1971.1Sjmcneill#define GCC_PERIPH_NOC_AT_CLK					186
1981.1Sjmcneill#define GCC_PERIPH_NOC_CFG_AHB_CLK				187
1991.1Sjmcneill#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK				188
2001.1Sjmcneill#define GCC_PERIPH_XPU_AHB_CLK					189
2011.1Sjmcneill#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK				190
2021.1Sjmcneill#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK				191
2031.1Sjmcneill#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK				192
2041.1Sjmcneill#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK				193
2051.1Sjmcneill#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK				194
2061.1Sjmcneill#define GCC_PRNG_AHB_CLK					195
2071.1Sjmcneill#define GCC_QDSS_AT_CLK						196
2081.1Sjmcneill#define GCC_QDSS_CFG_AHB_CLK					197
2091.1Sjmcneill#define GCC_QDSS_DAP_AHB_CLK					198
2101.1Sjmcneill#define GCC_QDSS_DAP_CLK					199
2111.1Sjmcneill#define GCC_QDSS_ETR_USB_CLK					200
2121.1Sjmcneill#define GCC_QDSS_STM_CLK					201
2131.1Sjmcneill#define GCC_QDSS_TRACECLKIN_CLK					202
2141.1Sjmcneill#define GCC_QDSS_TSCTR_DIV16_CLK				203
2151.1Sjmcneill#define GCC_QDSS_TSCTR_DIV2_CLK					204
2161.1Sjmcneill#define GCC_QDSS_TSCTR_DIV3_CLK					205
2171.1Sjmcneill#define GCC_QDSS_TSCTR_DIV4_CLK					206
2181.1Sjmcneill#define GCC_QDSS_TSCTR_DIV8_CLK					207
2191.1Sjmcneill#define GCC_QDSS_RBCPR_XPU_AHB_CLK				208
2201.1Sjmcneill#define GCC_RBCPR_AHB_CLK					209
2211.1Sjmcneill#define GCC_RBCPR_CLK						210
2221.1Sjmcneill#define GCC_RPM_BUS_AHB_CLK					211
2231.1Sjmcneill#define GCC_RPM_PROC_HCLK					212
2241.1Sjmcneill#define GCC_RPM_SLEEP_CLK					213
2251.1Sjmcneill#define GCC_RPM_TIMER_CLK					214
2261.1Sjmcneill#define GCC_SDCC1_AHB_CLK					215
2271.1Sjmcneill#define GCC_SDCC1_APPS_CLK					216
2281.1Sjmcneill#define GCC_SDCC1_INACTIVITY_TIMERS_CLK				217
2291.1Sjmcneill#define GCC_SDCC2_AHB_CLK					218
2301.1Sjmcneill#define GCC_SDCC2_APPS_CLK					219
2311.1Sjmcneill#define GCC_SDCC2_INACTIVITY_TIMERS_CLK				220
2321.1Sjmcneill#define GCC_SDCC3_AHB_CLK					221
2331.1Sjmcneill#define GCC_SDCC3_APPS_CLK					222
2341.1Sjmcneill#define GCC_SDCC3_INACTIVITY_TIMERS_CLK				223
2351.1Sjmcneill#define GCC_SDCC4_AHB_CLK					224
2361.1Sjmcneill#define GCC_SDCC4_APPS_CLK					225
2371.1Sjmcneill#define GCC_SDCC4_INACTIVITY_TIMERS_CLK				226
2381.1Sjmcneill#define GCC_SEC_CTRL_ACC_CLK					227
2391.1Sjmcneill#define GCC_SEC_CTRL_AHB_CLK					228
2401.1Sjmcneill#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK				229
2411.1Sjmcneill#define GCC_SEC_CTRL_CLK					230
2421.1Sjmcneill#define GCC_SEC_CTRL_SENSE_CLK					231
2431.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK				232
2441.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK				233
2451.1Sjmcneill#define GCC_SPDM_BIMC_CY_CLK					234
2461.1Sjmcneill#define GCC_SPDM_CFG_AHB_CLK					235
2471.1Sjmcneill#define GCC_SPDM_DEBUG_CY_CLK					236
2481.1Sjmcneill#define GCC_SPDM_FF_CLK						237
2491.1Sjmcneill#define GCC_SPDM_MSTR_AHB_CLK					238
2501.1Sjmcneill#define GCC_SPDM_PNOC_CY_CLK					239
2511.1Sjmcneill#define GCC_SPDM_RPM_CY_CLK					240
2521.1Sjmcneill#define GCC_SPDM_SNOC_CY_CLK					241
2531.1Sjmcneill#define GCC_SPMI_AHB_CLK					242
2541.1Sjmcneill#define GCC_SPMI_CNOC_AHB_CLK					243
2551.1Sjmcneill#define GCC_SPMI_SER_CLK					244
2561.1Sjmcneill#define GCC_SNOC_CNOC_AHB_CLK					245
2571.1Sjmcneill#define GCC_SNOC_PNOC_AHB_CLK					246
2581.1Sjmcneill#define GCC_SYS_NOC_AT_CLK					247
2591.1Sjmcneill#define GCC_SYS_NOC_AXI_CLK					248
2601.1Sjmcneill#define GCC_SYS_NOC_KPSS_AHB_CLK				249
2611.1Sjmcneill#define GCC_SYS_NOC_QDSS_STM_AXI_CLK				250
2621.1Sjmcneill#define GCC_SYS_NOC_USB3_AXI_CLK				251
2631.1Sjmcneill#define GCC_TCSR_AHB_CLK					252
2641.1Sjmcneill#define GCC_TLMM_AHB_CLK					253
2651.1Sjmcneill#define GCC_TLMM_CLK						254
2661.1Sjmcneill#define GCC_TSIF_AHB_CLK					255
2671.1Sjmcneill#define GCC_TSIF_INACTIVITY_TIMERS_CLK				256
2681.1Sjmcneill#define GCC_TSIF_REF_CLK					257
2691.1Sjmcneill#define GCC_USB2A_PHY_SLEEP_CLK					258
2701.1Sjmcneill#define GCC_USB2B_PHY_SLEEP_CLK					259
2711.1Sjmcneill#define GCC_USB30_MASTER_CLK					260
2721.1Sjmcneill#define GCC_USB30_MOCK_UTMI_CLK					261
2731.1Sjmcneill#define GCC_USB30_SLEEP_CLK					262
2741.1Sjmcneill#define GCC_USB_HS_AHB_CLK					263
2751.1Sjmcneill#define GCC_USB_HS_INACTIVITY_TIMERS_CLK			264
2761.1Sjmcneill#define GCC_USB_HS_SYSTEM_CLK					265
2771.1Sjmcneill#define GCC_USB_HSIC_AHB_CLK					266
2781.1Sjmcneill#define GCC_USB_HSIC_CLK					267
2791.1Sjmcneill#define GCC_USB_HSIC_IO_CAL_CLK					268
2801.1Sjmcneill#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK				269
2811.1Sjmcneill#define GCC_USB_HSIC_SYSTEM_CLK					270
2821.1Sjmcneill#define GCC_WCSS_GPLL1_CLK_SRC					271
2831.1Sjmcneill#define GCC_MMSS_GPLL0_CLK_SRC					272
2841.1Sjmcneill#define GCC_LPASS_GPLL0_CLK_SRC					273
2851.1Sjmcneill#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA			274
2861.1Sjmcneill#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA			275
2871.1Sjmcneill#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA			276
2881.1Sjmcneill#define GCC_IMEM_AXI_CLK_SLEEP_ENA				277
2891.1Sjmcneill#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA			278
2901.1Sjmcneill#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA				279
2911.1Sjmcneill#define GCC_KPSS_AHB_CLK_SLEEP_ENA				280
2921.1Sjmcneill#define GCC_KPSS_AXI_CLK_SLEEP_ENA				281
2931.1Sjmcneill#define GCC_MPM_AHB_CLK_SLEEP_ENA				282
2941.1Sjmcneill#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA			283
2951.1Sjmcneill#define GCC_BLSP1_AHB_CLK_SLEEP_ENA				284
2961.1Sjmcneill#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA				285
2971.1Sjmcneill#define GCC_BLSP2_AHB_CLK_SLEEP_ENA				286
2981.1Sjmcneill#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA				287
2991.1Sjmcneill#define GCC_PRNG_AHB_CLK_SLEEP_ENA				288
3001.1Sjmcneill#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA				289
3011.1Sjmcneill#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA		290
3021.1Sjmcneill#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA				291
3031.1Sjmcneill#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA				292
3041.1Sjmcneill#define GCC_TLMM_AHB_CLK_SLEEP_ENA				293
3051.1Sjmcneill#define GCC_TLMM_CLK_SLEEP_ENA					294
3061.1Sjmcneill#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA				295
3071.1Sjmcneill#define GCC_CE1_CLK_SLEEP_ENA					296
3081.1Sjmcneill#define GCC_CE1_AXI_CLK_SLEEP_ENA				297
3091.1Sjmcneill#define GCC_CE1_AHB_CLK_SLEEP_ENA				298
3101.1Sjmcneill#define GCC_CE2_CLK_SLEEP_ENA					299
3111.1Sjmcneill#define GCC_CE2_AXI_CLK_SLEEP_ENA				300
3121.1Sjmcneill#define GCC_CE2_AHB_CLK_SLEEP_ENA				301
3131.1Sjmcneill#define GPLL4							302
3141.1Sjmcneill#define GPLL4_VOTE						303
3151.1Sjmcneill#define GCC_SDCC1_CDCCAL_SLEEP_CLK				304
3161.1Sjmcneill#define GCC_SDCC1_CDCCAL_FF_CLK					305
3171.1Sjmcneill
3181.1Sjmcneill/* gdscs */
3191.1Sjmcneill#define USB_HS_HSIC_GDSC					0
3201.1Sjmcneill
3211.1Sjmcneill#endif
322