11.1Sjmcneill/* $NetBSD: qcom,gpucc-sm8250.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H 91.1Sjmcneill#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H 101.1Sjmcneill 111.1Sjmcneill/* GPU_CC clock registers */ 121.1Sjmcneill#define GPU_CC_AHB_CLK 0 131.1Sjmcneill#define GPU_CC_CRC_AHB_CLK 1 141.1Sjmcneill#define GPU_CC_CX_APB_CLK 2 151.1Sjmcneill#define GPU_CC_CX_GMU_CLK 3 161.1Sjmcneill#define GPU_CC_CX_SNOC_DVM_CLK 4 171.1Sjmcneill#define GPU_CC_CXO_AON_CLK 5 181.1Sjmcneill#define GPU_CC_CXO_CLK 6 191.1Sjmcneill#define GPU_CC_GMU_CLK_SRC 7 201.1Sjmcneill#define GPU_CC_GX_GMU_CLK 8 211.1Sjmcneill#define GPU_CC_PLL1 9 221.1Sjmcneill#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10 231.1Sjmcneill 241.1Sjmcneill/* GPU_CC Resets */ 251.1Sjmcneill#define GPUCC_GPU_CC_ACD_BCR 0 261.1Sjmcneill#define GPUCC_GPU_CC_CX_BCR 1 271.1Sjmcneill#define GPUCC_GPU_CC_GFX3D_AON_BCR 2 281.1Sjmcneill#define GPUCC_GPU_CC_GMU_BCR 3 291.1Sjmcneill#define GPUCC_GPU_CC_GX_BCR 4 301.1Sjmcneill#define GPUCC_GPU_CC_XO_BCR 5 311.1Sjmcneill 321.1Sjmcneill/* GPU_CC GDSCRs */ 331.1Sjmcneill#define GPU_CX_GDSC 0 341.1Sjmcneill#define GPU_GX_GDSC 1 351.1Sjmcneill 361.1Sjmcneill#endif 37