11.1Sskrll/* $NetBSD: qcom,sm6375-dispcc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 41.1Sskrll/* 51.1Sskrll * Copyright (c) 2021, The Linux Foundation. All rights reserved. 61.1Sskrll * Copyright (c) 2022, Linaro Limited 71.1Sskrll */ 81.1Sskrll 91.1Sskrll#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H 101.1Sskrll#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H 111.1Sskrll 121.1Sskrll/* Clocks */ 131.1Sskrll#define DISP_CC_PLL0 0 141.1Sskrll#define DISP_CC_MDSS_AHB_CLK 1 151.1Sskrll#define DISP_CC_MDSS_AHB_CLK_SRC 2 161.1Sskrll#define DISP_CC_MDSS_BYTE0_CLK 3 171.1Sskrll#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 181.1Sskrll#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 191.1Sskrll#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 201.1Sskrll#define DISP_CC_MDSS_ESC0_CLK 7 211.1Sskrll#define DISP_CC_MDSS_ESC0_CLK_SRC 8 221.1Sskrll#define DISP_CC_MDSS_MDP_CLK 9 231.1Sskrll#define DISP_CC_MDSS_MDP_CLK_SRC 10 241.1Sskrll#define DISP_CC_MDSS_MDP_LUT_CLK 11 251.1Sskrll#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 261.1Sskrll#define DISP_CC_MDSS_PCLK0_CLK 13 271.1Sskrll#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 281.1Sskrll#define DISP_CC_MDSS_ROT_CLK 15 291.1Sskrll#define DISP_CC_MDSS_ROT_CLK_SRC 16 301.1Sskrll#define DISP_CC_MDSS_RSCC_AHB_CLK 17 311.1Sskrll#define DISP_CC_MDSS_RSCC_VSYNC_CLK 18 321.1Sskrll#define DISP_CC_MDSS_VSYNC_CLK 19 331.1Sskrll#define DISP_CC_MDSS_VSYNC_CLK_SRC 20 341.1Sskrll#define DISP_CC_SLEEP_CLK 21 351.1Sskrll#define DISP_CC_XO_CLK 22 361.1Sskrll 371.1Sskrll/* Resets */ 381.1Sskrll#define DISP_CC_MDSS_CORE_BCR 0 391.1Sskrll#define DISP_CC_MDSS_RSCC_BCR 1 401.1Sskrll 411.1Sskrll/* GDSCs */ 421.1Sskrll#define MDSS_GDSC 0 431.1Sskrll 441.1Sskrll#endif 45