qcom,sm6375-dispcc.h revision 1.1.1.1
1/* $NetBSD: qcom,sm6375-dispcc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Linaro Limited 7 */ 8 9#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H 10#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H 11 12/* Clocks */ 13#define DISP_CC_PLL0 0 14#define DISP_CC_MDSS_AHB_CLK 1 15#define DISP_CC_MDSS_AHB_CLK_SRC 2 16#define DISP_CC_MDSS_BYTE0_CLK 3 17#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 18#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 19#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 20#define DISP_CC_MDSS_ESC0_CLK 7 21#define DISP_CC_MDSS_ESC0_CLK_SRC 8 22#define DISP_CC_MDSS_MDP_CLK 9 23#define DISP_CC_MDSS_MDP_CLK_SRC 10 24#define DISP_CC_MDSS_MDP_LUT_CLK 11 25#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 26#define DISP_CC_MDSS_PCLK0_CLK 13 27#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 28#define DISP_CC_MDSS_ROT_CLK 15 29#define DISP_CC_MDSS_ROT_CLK_SRC 16 30#define DISP_CC_MDSS_RSCC_AHB_CLK 17 31#define DISP_CC_MDSS_RSCC_VSYNC_CLK 18 32#define DISP_CC_MDSS_VSYNC_CLK 19 33#define DISP_CC_MDSS_VSYNC_CLK_SRC 20 34#define DISP_CC_SLEEP_CLK 21 35#define DISP_CC_XO_CLK 22 36 37/* Resets */ 38#define DISP_CC_MDSS_CORE_BCR 0 39#define DISP_CC_MDSS_RSCC_BCR 1 40 41/* GDSCs */ 42#define MDSS_GDSC 0 43 44#endif 45