qcom,sm7150-camcc.h revision 1.1.1.1 
1/*	$NetBSD: qcom,sm7150-camcc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4/*
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
7 */
8
9#ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H
10#define _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H
11
12/* Hardware clocks */
13#define CAMCC_PLL0_OUT_EVEN					0
14#define CAMCC_PLL0_OUT_ODD					1
15#define CAMCC_PLL1_OUT_EVEN					2
16#define CAMCC_PLL2_OUT_EARLY					3
17#define CAMCC_PLL3_OUT_EVEN					4
18#define CAMCC_PLL4_OUT_EVEN					5
19
20/* CAMCC clock registers */
21#define CAMCC_PLL0						6
22#define CAMCC_PLL1						7
23#define CAMCC_PLL2						8
24#define CAMCC_PLL2_OUT_AUX					9
25#define CAMCC_PLL2_OUT_MAIN					10
26#define CAMCC_PLL3						11
27#define CAMCC_PLL4						12
28#define CAMCC_BPS_AHB_CLK					13
29#define CAMCC_BPS_AREG_CLK					14
30#define CAMCC_BPS_AXI_CLK					15
31#define CAMCC_BPS_CLK						16
32#define CAMCC_BPS_CLK_SRC					17
33#define CAMCC_CAMNOC_AXI_CLK					18
34#define CAMCC_CAMNOC_AXI_CLK_SRC				19
35#define CAMCC_CAMNOC_DCD_XO_CLK					20
36#define CAMCC_CCI_0_CLK						21
37#define CAMCC_CCI_0_CLK_SRC					22
38#define CAMCC_CCI_1_CLK						23
39#define CAMCC_CCI_1_CLK_SRC					24
40#define CAMCC_CORE_AHB_CLK					25
41#define CAMCC_CPAS_AHB_CLK					26
42#define CAMCC_CPHY_RX_CLK_SRC					27
43#define CAMCC_CSI0PHYTIMER_CLK					28
44#define CAMCC_CSI0PHYTIMER_CLK_SRC				29
45#define CAMCC_CSI1PHYTIMER_CLK					30
46#define CAMCC_CSI1PHYTIMER_CLK_SRC				31
47#define CAMCC_CSI2PHYTIMER_CLK					32
48#define CAMCC_CSI2PHYTIMER_CLK_SRC				33
49#define CAMCC_CSI3PHYTIMER_CLK					34
50#define CAMCC_CSI3PHYTIMER_CLK_SRC				35
51#define CAMCC_CSIPHY0_CLK					36
52#define CAMCC_CSIPHY1_CLK					37
53#define CAMCC_CSIPHY2_CLK					38
54#define CAMCC_CSIPHY3_CLK					39
55#define CAMCC_FAST_AHB_CLK_SRC					40
56#define CAMCC_FD_CORE_CLK					41
57#define CAMCC_FD_CORE_CLK_SRC					42
58#define CAMCC_FD_CORE_UAR_CLK					43
59#define CAMCC_ICP_AHB_CLK					44
60#define CAMCC_ICP_CLK						45
61#define CAMCC_ICP_CLK_SRC					46
62#define CAMCC_IFE_0_AXI_CLK					47
63#define CAMCC_IFE_0_CLK						48
64#define CAMCC_IFE_0_CLK_SRC					49
65#define CAMCC_IFE_0_CPHY_RX_CLK					50
66#define CAMCC_IFE_0_CSID_CLK					51
67#define CAMCC_IFE_0_CSID_CLK_SRC				52
68#define CAMCC_IFE_0_DSP_CLK					53
69#define CAMCC_IFE_1_AXI_CLK					54
70#define CAMCC_IFE_1_CLK						55
71#define CAMCC_IFE_1_CLK_SRC					56
72#define CAMCC_IFE_1_CPHY_RX_CLK					57
73#define CAMCC_IFE_1_CSID_CLK					58
74#define CAMCC_IFE_1_CSID_CLK_SRC				59
75#define CAMCC_IFE_1_DSP_CLK					60
76#define CAMCC_IFE_LITE_CLK					61
77#define CAMCC_IFE_LITE_CLK_SRC					62
78#define CAMCC_IFE_LITE_CPHY_RX_CLK				63
79#define CAMCC_IFE_LITE_CSID_CLK					64
80#define CAMCC_IFE_LITE_CSID_CLK_SRC				65
81#define CAMCC_IPE_0_AHB_CLK					66
82#define CAMCC_IPE_0_AREG_CLK					67
83#define CAMCC_IPE_0_AXI_CLK					68
84#define CAMCC_IPE_0_CLK						69
85#define CAMCC_IPE_0_CLK_SRC					70
86#define CAMCC_IPE_1_AHB_CLK					71
87#define CAMCC_IPE_1_AREG_CLK					72
88#define CAMCC_IPE_1_AXI_CLK					73
89#define CAMCC_IPE_1_CLK						74
90#define CAMCC_JPEG_CLK						75
91#define CAMCC_JPEG_CLK_SRC					76
92#define CAMCC_LRME_CLK						77
93#define CAMCC_LRME_CLK_SRC					78
94#define CAMCC_MCLK0_CLK						79
95#define CAMCC_MCLK0_CLK_SRC					80
96#define CAMCC_MCLK1_CLK						81
97#define CAMCC_MCLK1_CLK_SRC					82
98#define CAMCC_MCLK2_CLK						83
99#define CAMCC_MCLK2_CLK_SRC					84
100#define CAMCC_MCLK3_CLK						85
101#define CAMCC_MCLK3_CLK_SRC					86
102#define CAMCC_SLEEP_CLK						87
103#define CAMCC_SLEEP_CLK_SRC					88
104#define CAMCC_SLOW_AHB_CLK_SRC					89
105#define CAMCC_XO_CLK_SRC					90
106
107/* CAMCC GDSCRs */
108#define BPS_GDSC						0
109#define IFE_0_GDSC						1
110#define IFE_1_GDSC						2
111#define IPE_0_GDSC						3
112#define IPE_1_GDSC						4
113#define TITAN_TOP_GDSC						5
114
115#endif
116