qcom,sm8550-gpucc.h revision 1.1.1.1
1/* $NetBSD: qcom,sm8550-gpucc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H 9#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H 10 11/* GPU_CC clocks */ 12#define GPU_CC_AHB_CLK 0 13#define GPU_CC_CRC_AHB_CLK 1 14#define GPU_CC_CX_FF_CLK 2 15#define GPU_CC_CX_GMU_CLK 3 16#define GPU_CC_CXO_AON_CLK 4 17#define GPU_CC_CXO_CLK 5 18#define GPU_CC_DEMET_CLK 6 19#define GPU_CC_DEMET_DIV_CLK_SRC 7 20#define GPU_CC_FF_CLK_SRC 8 21#define GPU_CC_FREQ_MEASURE_CLK 9 22#define GPU_CC_GMU_CLK_SRC 10 23#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11 24#define GPU_CC_HUB_AON_CLK 12 25#define GPU_CC_HUB_CLK_SRC 13 26#define GPU_CC_HUB_CX_INT_CLK 14 27#define GPU_CC_MEMNOC_GFX_CLK 15 28#define GPU_CC_MND1X_0_GFX3D_CLK 16 29#define GPU_CC_MND1X_1_GFX3D_CLK 17 30#define GPU_CC_PLL0 18 31#define GPU_CC_PLL1 19 32#define GPU_CC_SLEEP_CLK 20 33#define GPU_CC_XO_CLK_SRC 21 34#define GPU_CC_XO_DIV_CLK_SRC 22 35 36/* GPU_CC power domains */ 37#define GPU_CC_CX_GDSC 0 38#define GPU_CC_GX_GDSC 1 39 40/* GPU_CC resets */ 41#define GPUCC_GPU_CC_ACD_BCR 0 42#define GPUCC_GPU_CC_CX_BCR 1 43#define GPUCC_GPU_CC_FAST_HUB_BCR 2 44#define GPUCC_GPU_CC_FF_BCR 3 45#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 46#define GPUCC_GPU_CC_GMU_BCR 5 47#define GPUCC_GPU_CC_GX_BCR 6 48#define GPUCC_GPU_CC_XO_BCR 7 49 50#endif 51