1 1.1 jmcneill /* $NetBSD: qcom,gcc-apq8084.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 2 1.1 jmcneill 3 1.1.1.2 skrll /* SPDX-License-Identifier: GPL-2.0-only */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (c) 2014, The Linux Foundation. All rights reserved. 6 1.1 jmcneill */ 7 1.1 jmcneill 8 1.1 jmcneill #ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H 9 1.1 jmcneill #define _DT_BINDINGS_CLK_APQ_GCC_8084_H 10 1.1 jmcneill 11 1.1 jmcneill #define GPLL0 0 12 1.1 jmcneill #define GPLL0_VOTE 1 13 1.1 jmcneill #define GPLL1 2 14 1.1 jmcneill #define GPLL1_VOTE 3 15 1.1 jmcneill #define GPLL2 4 16 1.1 jmcneill #define GPLL2_VOTE 5 17 1.1 jmcneill #define GPLL3 6 18 1.1 jmcneill #define GPLL3_VOTE 7 19 1.1 jmcneill #define GPLL4 8 20 1.1 jmcneill #define GPLL4_VOTE 9 21 1.1 jmcneill #define CONFIG_NOC_CLK_SRC 10 22 1.1 jmcneill #define PERIPH_NOC_CLK_SRC 11 23 1.1 jmcneill #define SYSTEM_NOC_CLK_SRC 12 24 1.1 jmcneill #define BLSP_UART_SIM_CLK_SRC 13 25 1.1 jmcneill #define QDSS_TSCTR_CLK_SRC 14 26 1.1 jmcneill #define UFS_AXI_CLK_SRC 15 27 1.1 jmcneill #define RPM_CLK_SRC 16 28 1.1 jmcneill #define KPSS_AHB_CLK_SRC 17 29 1.1 jmcneill #define QDSS_AT_CLK_SRC 18 30 1.1 jmcneill #define BIMC_DDR_CLK_SRC 19 31 1.1 jmcneill #define USB30_MASTER_CLK_SRC 20 32 1.1 jmcneill #define USB30_SEC_MASTER_CLK_SRC 21 33 1.1 jmcneill #define USB_HSIC_AHB_CLK_SRC 22 34 1.1 jmcneill #define MMSS_BIMC_GFX_CLK_SRC 23 35 1.1 jmcneill #define QDSS_STM_CLK_SRC 24 36 1.1 jmcneill #define ACC_CLK_SRC 25 37 1.1 jmcneill #define SEC_CTRL_CLK_SRC 26 38 1.1 jmcneill #define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 39 1.1 jmcneill #define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 40 1.1 jmcneill #define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 41 1.1 jmcneill #define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 42 1.1 jmcneill #define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 43 1.1 jmcneill #define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 44 1.1 jmcneill #define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 45 1.1 jmcneill #define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 46 1.1 jmcneill #define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 47 1.1 jmcneill #define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 48 1.1 jmcneill #define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 49 1.1 jmcneill #define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 50 1.1 jmcneill #define BLSP1_UART1_APPS_CLK_SRC 39 51 1.1 jmcneill #define BLSP1_UART2_APPS_CLK_SRC 40 52 1.1 jmcneill #define BLSP1_UART3_APPS_CLK_SRC 41 53 1.1 jmcneill #define BLSP1_UART4_APPS_CLK_SRC 42 54 1.1 jmcneill #define BLSP1_UART5_APPS_CLK_SRC 43 55 1.1 jmcneill #define BLSP1_UART6_APPS_CLK_SRC 44 56 1.1 jmcneill #define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 57 1.1 jmcneill #define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 58 1.1 jmcneill #define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 59 1.1 jmcneill #define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 60 1.1 jmcneill #define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 61 1.1 jmcneill #define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 62 1.1 jmcneill #define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 63 1.1 jmcneill #define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 64 1.1 jmcneill #define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 65 1.1 jmcneill #define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 66 1.1 jmcneill #define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 67 1.1 jmcneill #define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 68 1.1 jmcneill #define BLSP2_UART1_APPS_CLK_SRC 57 69 1.1 jmcneill #define BLSP2_UART2_APPS_CLK_SRC 58 70 1.1 jmcneill #define BLSP2_UART3_APPS_CLK_SRC 59 71 1.1 jmcneill #define BLSP2_UART4_APPS_CLK_SRC 60 72 1.1 jmcneill #define BLSP2_UART5_APPS_CLK_SRC 61 73 1.1 jmcneill #define BLSP2_UART6_APPS_CLK_SRC 62 74 1.1 jmcneill #define CE1_CLK_SRC 63 75 1.1 jmcneill #define CE2_CLK_SRC 64 76 1.1 jmcneill #define CE3_CLK_SRC 65 77 1.1 jmcneill #define GP1_CLK_SRC 66 78 1.1 jmcneill #define GP2_CLK_SRC 67 79 1.1 jmcneill #define GP3_CLK_SRC 68 80 1.1 jmcneill #define PDM2_CLK_SRC 69 81 1.1 jmcneill #define QDSS_TRACECLKIN_CLK_SRC 70 82 1.1 jmcneill #define RBCPR_CLK_SRC 71 83 1.1 jmcneill #define SATA_ASIC0_CLK_SRC 72 84 1.1 jmcneill #define SATA_PMALIVE_CLK_SRC 73 85 1.1 jmcneill #define SATA_RX_CLK_SRC 74 86 1.1 jmcneill #define SATA_RX_OOB_CLK_SRC 75 87 1.1 jmcneill #define SDCC1_APPS_CLK_SRC 76 88 1.1 jmcneill #define SDCC2_APPS_CLK_SRC 77 89 1.1 jmcneill #define SDCC3_APPS_CLK_SRC 78 90 1.1 jmcneill #define SDCC4_APPS_CLK_SRC 79 91 1.1 jmcneill #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 92 1.1 jmcneill #define SPMI_AHB_CLK_SRC 81 93 1.1 jmcneill #define SPMI_SER_CLK_SRC 82 94 1.1 jmcneill #define TSIF_REF_CLK_SRC 83 95 1.1 jmcneill #define USB30_MOCK_UTMI_CLK_SRC 84 96 1.1 jmcneill #define USB30_SEC_MOCK_UTMI_CLK_SRC 85 97 1.1 jmcneill #define USB_HS_SYSTEM_CLK_SRC 86 98 1.1 jmcneill #define USB_HSIC_CLK_SRC 87 99 1.1 jmcneill #define USB_HSIC_IO_CAL_CLK_SRC 88 100 1.1 jmcneill #define USB_HSIC_MOCK_UTMI_CLK_SRC 89 101 1.1 jmcneill #define USB_HSIC_SYSTEM_CLK_SRC 90 102 1.1 jmcneill #define GCC_BAM_DMA_AHB_CLK 91 103 1.1 jmcneill #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 104 1.1 jmcneill #define DDR_CLK_SRC 93 105 1.1 jmcneill #define GCC_BIMC_CFG_AHB_CLK 94 106 1.1 jmcneill #define GCC_BIMC_CLK 95 107 1.1 jmcneill #define GCC_BIMC_KPSS_AXI_CLK 96 108 1.1 jmcneill #define GCC_BIMC_SLEEP_CLK 97 109 1.1 jmcneill #define GCC_BIMC_SYSNOC_AXI_CLK 98 110 1.1 jmcneill #define GCC_BIMC_XO_CLK 99 111 1.1 jmcneill #define GCC_BLSP1_AHB_CLK 100 112 1.1 jmcneill #define GCC_BLSP1_SLEEP_CLK 101 113 1.1 jmcneill #define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 114 1.1 jmcneill #define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 115 1.1 jmcneill #define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 116 1.1 jmcneill #define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 117 1.1 jmcneill #define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 118 1.1 jmcneill #define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 119 1.1 jmcneill #define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 120 1.1 jmcneill #define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 121 1.1 jmcneill #define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 122 1.1 jmcneill #define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 123 1.1 jmcneill #define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 124 1.1 jmcneill #define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 125 1.1 jmcneill #define GCC_BLSP1_UART1_APPS_CLK 114 126 1.1 jmcneill #define GCC_BLSP1_UART1_SIM_CLK 115 127 1.1 jmcneill #define GCC_BLSP1_UART2_APPS_CLK 116 128 1.1 jmcneill #define GCC_BLSP1_UART2_SIM_CLK 117 129 1.1 jmcneill #define GCC_BLSP1_UART3_APPS_CLK 118 130 1.1 jmcneill #define GCC_BLSP1_UART3_SIM_CLK 119 131 1.1 jmcneill #define GCC_BLSP1_UART4_APPS_CLK 120 132 1.1 jmcneill #define GCC_BLSP1_UART4_SIM_CLK 121 133 1.1 jmcneill #define GCC_BLSP1_UART5_APPS_CLK 122 134 1.1 jmcneill #define GCC_BLSP1_UART5_SIM_CLK 123 135 1.1 jmcneill #define GCC_BLSP1_UART6_APPS_CLK 124 136 1.1 jmcneill #define GCC_BLSP1_UART6_SIM_CLK 125 137 1.1 jmcneill #define GCC_BLSP2_AHB_CLK 126 138 1.1 jmcneill #define GCC_BLSP2_SLEEP_CLK 127 139 1.1 jmcneill #define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 140 1.1 jmcneill #define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 141 1.1 jmcneill #define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 142 1.1 jmcneill #define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 143 1.1 jmcneill #define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 144 1.1 jmcneill #define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 145 1.1 jmcneill #define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 146 1.1 jmcneill #define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 147 1.1 jmcneill #define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 148 1.1 jmcneill #define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 149 1.1 jmcneill #define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 150 1.1 jmcneill #define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 151 1.1 jmcneill #define GCC_BLSP2_UART1_APPS_CLK 140 152 1.1 jmcneill #define GCC_BLSP2_UART1_SIM_CLK 141 153 1.1 jmcneill #define GCC_BLSP2_UART2_APPS_CLK 142 154 1.1 jmcneill #define GCC_BLSP2_UART2_SIM_CLK 143 155 1.1 jmcneill #define GCC_BLSP2_UART3_APPS_CLK 144 156 1.1 jmcneill #define GCC_BLSP2_UART3_SIM_CLK 145 157 1.1 jmcneill #define GCC_BLSP2_UART4_APPS_CLK 146 158 1.1 jmcneill #define GCC_BLSP2_UART4_SIM_CLK 147 159 1.1 jmcneill #define GCC_BLSP2_UART5_APPS_CLK 148 160 1.1 jmcneill #define GCC_BLSP2_UART5_SIM_CLK 149 161 1.1 jmcneill #define GCC_BLSP2_UART6_APPS_CLK 150 162 1.1 jmcneill #define GCC_BLSP2_UART6_SIM_CLK 151 163 1.1 jmcneill #define GCC_BOOT_ROM_AHB_CLK 152 164 1.1 jmcneill #define GCC_CE1_AHB_CLK 153 165 1.1 jmcneill #define GCC_CE1_AXI_CLK 154 166 1.1 jmcneill #define GCC_CE1_CLK 155 167 1.1 jmcneill #define GCC_CE2_AHB_CLK 156 168 1.1 jmcneill #define GCC_CE2_AXI_CLK 157 169 1.1 jmcneill #define GCC_CE2_CLK 158 170 1.1 jmcneill #define GCC_CE3_AHB_CLK 159 171 1.1 jmcneill #define GCC_CE3_AXI_CLK 160 172 1.1 jmcneill #define GCC_CE3_CLK 161 173 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 174 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 175 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 176 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 177 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 178 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 179 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 180 1.1 jmcneill #define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 181 1.1 jmcneill #define GCC_CFG_NOC_AHB_CLK 170 182 1.1 jmcneill #define GCC_CFG_NOC_DDR_CFG_CLK 171 183 1.1 jmcneill #define GCC_CFG_NOC_RPM_AHB_CLK 172 184 1.1 jmcneill #define GCC_COPSS_SMMU_AHB_CLK 173 185 1.1 jmcneill #define GCC_COPSS_SMMU_AXI_CLK 174 186 1.1 jmcneill #define GCC_DCD_XO_CLK 175 187 1.1 jmcneill #define GCC_BIMC_DDR_CH0_CLK 176 188 1.1 jmcneill #define GCC_BIMC_DDR_CH1_CLK 177 189 1.1 jmcneill #define GCC_BIMC_DDR_CPLL0_CLK 178 190 1.1 jmcneill #define GCC_BIMC_DDR_CPLL1_CLK 179 191 1.1 jmcneill #define GCC_BIMC_GFX_CLK 180 192 1.1 jmcneill #define GCC_DDR_DIM_CFG_CLK 181 193 1.1 jmcneill #define GCC_DDR_DIM_SLEEP_CLK 182 194 1.1 jmcneill #define GCC_DEHR_CLK 183 195 1.1 jmcneill #define GCC_AHB_CLK 184 196 1.1 jmcneill #define GCC_IM_SLEEP_CLK 185 197 1.1 jmcneill #define GCC_XO_CLK 186 198 1.1 jmcneill #define GCC_XO_DIV4_CLK 187 199 1.1 jmcneill #define GCC_GP1_CLK 188 200 1.1 jmcneill #define GCC_GP2_CLK 189 201 1.1 jmcneill #define GCC_GP3_CLK 190 202 1.1 jmcneill #define GCC_IMEM_AXI_CLK 191 203 1.1 jmcneill #define GCC_IMEM_CFG_AHB_CLK 192 204 1.1 jmcneill #define GCC_KPSS_AHB_CLK 193 205 1.1 jmcneill #define GCC_KPSS_AXI_CLK 194 206 1.1 jmcneill #define GCC_LPASS_MPORT_AXI_CLK 195 207 1.1 jmcneill #define GCC_LPASS_Q6_AXI_CLK 196 208 1.1 jmcneill #define GCC_LPASS_SWAY_CLK 197 209 1.1 jmcneill #define GCC_MMSS_BIMC_GFX_CLK 198 210 1.1 jmcneill #define GCC_MMSS_NOC_AT_CLK 199 211 1.1 jmcneill #define GCC_MMSS_NOC_CFG_AHB_CLK 200 212 1.1 jmcneill #define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 213 1.1 jmcneill #define GCC_OCMEM_NOC_CFG_AHB_CLK 202 214 1.1 jmcneill #define GCC_OCMEM_SYS_NOC_AXI_CLK 203 215 1.1 jmcneill #define GCC_MPM_AHB_CLK 204 216 1.1 jmcneill #define GCC_MSG_RAM_AHB_CLK 205 217 1.1 jmcneill #define GCC_NOC_CONF_XPU_AHB_CLK 206 218 1.1 jmcneill #define GCC_PDM2_CLK 207 219 1.1 jmcneill #define GCC_PDM_AHB_CLK 208 220 1.1 jmcneill #define GCC_PDM_XO4_CLK 209 221 1.1 jmcneill #define GCC_PERIPH_NOC_AHB_CLK 210 222 1.1 jmcneill #define GCC_PERIPH_NOC_AT_CLK 211 223 1.1 jmcneill #define GCC_PERIPH_NOC_CFG_AHB_CLK 212 224 1.1 jmcneill #define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 225 1.1 jmcneill #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 226 1.1 jmcneill #define GCC_PERIPH_XPU_AHB_CLK 215 227 1.1 jmcneill #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 228 1.1 jmcneill #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 229 1.1 jmcneill #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 230 1.1 jmcneill #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 231 1.1 jmcneill #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 232 1.1 jmcneill #define GCC_PRNG_AHB_CLK 221 233 1.1 jmcneill #define GCC_QDSS_AT_CLK 222 234 1.1 jmcneill #define GCC_QDSS_CFG_AHB_CLK 223 235 1.1 jmcneill #define GCC_QDSS_DAP_AHB_CLK 224 236 1.1 jmcneill #define GCC_QDSS_DAP_CLK 225 237 1.1 jmcneill #define GCC_QDSS_ETR_USB_CLK 226 238 1.1 jmcneill #define GCC_QDSS_STM_CLK 227 239 1.1 jmcneill #define GCC_QDSS_TRACECLKIN_CLK 228 240 1.1 jmcneill #define GCC_QDSS_TSCTR_DIV16_CLK 229 241 1.1 jmcneill #define GCC_QDSS_TSCTR_DIV2_CLK 230 242 1.1 jmcneill #define GCC_QDSS_TSCTR_DIV3_CLK 231 243 1.1 jmcneill #define GCC_QDSS_TSCTR_DIV4_CLK 232 244 1.1 jmcneill #define GCC_QDSS_TSCTR_DIV8_CLK 233 245 1.1 jmcneill #define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 246 1.1 jmcneill #define GCC_RBCPR_AHB_CLK 235 247 1.1 jmcneill #define GCC_RBCPR_CLK 236 248 1.1 jmcneill #define GCC_RPM_BUS_AHB_CLK 237 249 1.1 jmcneill #define GCC_RPM_PROC_HCLK 238 250 1.1 jmcneill #define GCC_RPM_SLEEP_CLK 239 251 1.1 jmcneill #define GCC_RPM_TIMER_CLK 240 252 1.1 jmcneill #define GCC_SATA_ASIC0_CLK 241 253 1.1 jmcneill #define GCC_SATA_AXI_CLK 242 254 1.1 jmcneill #define GCC_SATA_CFG_AHB_CLK 243 255 1.1 jmcneill #define GCC_SATA_PMALIVE_CLK 244 256 1.1 jmcneill #define GCC_SATA_RX_CLK 245 257 1.1 jmcneill #define GCC_SATA_RX_OOB_CLK 246 258 1.1 jmcneill #define GCC_SDCC1_AHB_CLK 247 259 1.1 jmcneill #define GCC_SDCC1_APPS_CLK 248 260 1.1 jmcneill #define GCC_SDCC1_CDCCAL_FF_CLK 249 261 1.1 jmcneill #define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 262 1.1 jmcneill #define GCC_SDCC2_AHB_CLK 251 263 1.1 jmcneill #define GCC_SDCC2_APPS_CLK 252 264 1.1 jmcneill #define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 265 1.1 jmcneill #define GCC_SDCC3_AHB_CLK 254 266 1.1 jmcneill #define GCC_SDCC3_APPS_CLK 255 267 1.1 jmcneill #define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 268 1.1 jmcneill #define GCC_SDCC4_AHB_CLK 257 269 1.1 jmcneill #define GCC_SDCC4_APPS_CLK 258 270 1.1 jmcneill #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 271 1.1 jmcneill #define GCC_SEC_CTRL_ACC_CLK 260 272 1.1 jmcneill #define GCC_SEC_CTRL_AHB_CLK 261 273 1.1 jmcneill #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 274 1.1 jmcneill #define GCC_SEC_CTRL_CLK 263 275 1.1 jmcneill #define GCC_SEC_CTRL_SENSE_CLK 264 276 1.1 jmcneill #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 277 1.1 jmcneill #define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 278 1.1 jmcneill #define GCC_SPDM_BIMC_CY_CLK 267 279 1.1 jmcneill #define GCC_SPDM_CFG_AHB_CLK 268 280 1.1 jmcneill #define GCC_SPDM_DEBUG_CY_CLK 269 281 1.1 jmcneill #define GCC_SPDM_FF_CLK 270 282 1.1 jmcneill #define GCC_SPDM_MSTR_AHB_CLK 271 283 1.1 jmcneill #define GCC_SPDM_PNOC_CY_CLK 272 284 1.1 jmcneill #define GCC_SPDM_RPM_CY_CLK 273 285 1.1 jmcneill #define GCC_SPDM_SNOC_CY_CLK 274 286 1.1 jmcneill #define GCC_SPMI_AHB_CLK 275 287 1.1 jmcneill #define GCC_SPMI_CNOC_AHB_CLK 276 288 1.1 jmcneill #define GCC_SPMI_SER_CLK 277 289 1.1 jmcneill #define GCC_SPSS_AHB_CLK 278 290 1.1 jmcneill #define GCC_SNOC_CNOC_AHB_CLK 279 291 1.1 jmcneill #define GCC_SNOC_PNOC_AHB_CLK 280 292 1.1 jmcneill #define GCC_SYS_NOC_AT_CLK 281 293 1.1 jmcneill #define GCC_SYS_NOC_AXI_CLK 282 294 1.1 jmcneill #define GCC_SYS_NOC_KPSS_AHB_CLK 283 295 1.1 jmcneill #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 296 1.1 jmcneill #define GCC_SYS_NOC_UFS_AXI_CLK 285 297 1.1 jmcneill #define GCC_SYS_NOC_USB3_AXI_CLK 286 298 1.1 jmcneill #define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 299 1.1 jmcneill #define GCC_TCSR_AHB_CLK 288 300 1.1 jmcneill #define GCC_TLMM_AHB_CLK 289 301 1.1 jmcneill #define GCC_TLMM_CLK 290 302 1.1 jmcneill #define GCC_TSIF_AHB_CLK 291 303 1.1 jmcneill #define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 304 1.1 jmcneill #define GCC_TSIF_REF_CLK 293 305 1.1 jmcneill #define GCC_UFS_AHB_CLK 294 306 1.1 jmcneill #define GCC_UFS_AXI_CLK 295 307 1.1 jmcneill #define GCC_UFS_RX_CFG_CLK 296 308 1.1 jmcneill #define GCC_UFS_RX_SYMBOL_0_CLK 297 309 1.1 jmcneill #define GCC_UFS_RX_SYMBOL_1_CLK 298 310 1.1 jmcneill #define GCC_UFS_TX_CFG_CLK 299 311 1.1 jmcneill #define GCC_UFS_TX_SYMBOL_0_CLK 300 312 1.1 jmcneill #define GCC_UFS_TX_SYMBOL_1_CLK 301 313 1.1 jmcneill #define GCC_USB2A_PHY_SLEEP_CLK 302 314 1.1 jmcneill #define GCC_USB2B_PHY_SLEEP_CLK 303 315 1.1 jmcneill #define GCC_USB30_MASTER_CLK 304 316 1.1 jmcneill #define GCC_USB30_MOCK_UTMI_CLK 305 317 1.1 jmcneill #define GCC_USB30_SLEEP_CLK 306 318 1.1 jmcneill #define GCC_USB30_SEC_MASTER_CLK 307 319 1.1 jmcneill #define GCC_USB30_SEC_MOCK_UTMI_CLK 308 320 1.1 jmcneill #define GCC_USB30_SEC_SLEEP_CLK 309 321 1.1 jmcneill #define GCC_USB_HS_AHB_CLK 310 322 1.1 jmcneill #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 323 1.1 jmcneill #define GCC_USB_HS_SYSTEM_CLK 312 324 1.1 jmcneill #define GCC_USB_HSIC_AHB_CLK 313 325 1.1 jmcneill #define GCC_USB_HSIC_CLK 314 326 1.1 jmcneill #define GCC_USB_HSIC_IO_CAL_CLK 315 327 1.1 jmcneill #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 328 1.1 jmcneill #define GCC_USB_HSIC_MOCK_UTMI_CLK 317 329 1.1 jmcneill #define GCC_USB_HSIC_SYSTEM_CLK 318 330 1.1 jmcneill #define PCIE_0_AUX_CLK_SRC 319 331 1.1 jmcneill #define PCIE_0_PIPE_CLK_SRC 320 332 1.1 jmcneill #define PCIE_1_AUX_CLK_SRC 321 333 1.1 jmcneill #define PCIE_1_PIPE_CLK_SRC 322 334 1.1 jmcneill #define GCC_PCIE_0_AUX_CLK 323 335 1.1 jmcneill #define GCC_PCIE_0_CFG_AHB_CLK 324 336 1.1 jmcneill #define GCC_PCIE_0_MSTR_AXI_CLK 325 337 1.1 jmcneill #define GCC_PCIE_0_PIPE_CLK 326 338 1.1 jmcneill #define GCC_PCIE_0_SLV_AXI_CLK 327 339 1.1 jmcneill #define GCC_PCIE_1_AUX_CLK 328 340 1.1 jmcneill #define GCC_PCIE_1_CFG_AHB_CLK 329 341 1.1 jmcneill #define GCC_PCIE_1_MSTR_AXI_CLK 330 342 1.1 jmcneill #define GCC_PCIE_1_PIPE_CLK 331 343 1.1 jmcneill #define GCC_PCIE_1_SLV_AXI_CLK 332 344 1.1 jmcneill 345 1.1 jmcneill /* gdscs */ 346 1.1 jmcneill #define USB_HS_HSIC_GDSC 0 347 1.1 jmcneill #define PCIE0_GDSC 1 348 1.1 jmcneill #define PCIE1_GDSC 2 349 1.1 jmcneill #define USB30_GDSC 3 350 1.1 jmcneill 351 1.1 jmcneill #endif 352