1 1.1 jmcneill /* $NetBSD: qcom,gcc-ipq6018.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 1.1 jmcneill */ 7 1.1 jmcneill 8 1.1 jmcneill #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H 9 1.1 jmcneill #define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H 10 1.1 jmcneill 11 1.1 jmcneill #define GPLL0 0 12 1.1 jmcneill #define UBI32_PLL 1 13 1.1 jmcneill #define GPLL6 2 14 1.1 jmcneill #define GPLL4 3 15 1.1 jmcneill #define PCNOC_BFDCD_CLK_SRC 4 16 1.1 jmcneill #define GPLL2 5 17 1.1 jmcneill #define NSS_CRYPTO_PLL 6 18 1.1 jmcneill #define NSS_PPE_CLK_SRC 7 19 1.1 jmcneill #define GCC_XO_CLK_SRC 8 20 1.1 jmcneill #define NSS_CE_CLK_SRC 9 21 1.1 jmcneill #define GCC_SLEEP_CLK_SRC 10 22 1.1 jmcneill #define APSS_AHB_CLK_SRC 11 23 1.1 jmcneill #define NSS_PORT5_RX_CLK_SRC 12 24 1.1 jmcneill #define NSS_PORT5_TX_CLK_SRC 13 25 1.1 jmcneill #define PCIE0_AXI_CLK_SRC 14 26 1.1 jmcneill #define USB0_MASTER_CLK_SRC 15 27 1.1 jmcneill #define APSS_AHB_POSTDIV_CLK_SRC 16 28 1.1 jmcneill #define NSS_PORT1_RX_CLK_SRC 17 29 1.1 jmcneill #define NSS_PORT1_TX_CLK_SRC 18 30 1.1 jmcneill #define NSS_PORT2_RX_CLK_SRC 19 31 1.1 jmcneill #define NSS_PORT2_TX_CLK_SRC 20 32 1.1 jmcneill #define NSS_PORT3_RX_CLK_SRC 21 33 1.1 jmcneill #define NSS_PORT3_TX_CLK_SRC 22 34 1.1 jmcneill #define NSS_PORT4_RX_CLK_SRC 23 35 1.1 jmcneill #define NSS_PORT4_TX_CLK_SRC 24 36 1.1 jmcneill #define NSS_PORT5_RX_DIV_CLK_SRC 25 37 1.1 jmcneill #define NSS_PORT5_TX_DIV_CLK_SRC 26 38 1.1 jmcneill #define APSS_AXI_CLK_SRC 27 39 1.1 jmcneill #define NSS_CRYPTO_CLK_SRC 28 40 1.1 jmcneill #define NSS_PORT1_RX_DIV_CLK_SRC 29 41 1.1 jmcneill #define NSS_PORT1_TX_DIV_CLK_SRC 30 42 1.1 jmcneill #define NSS_PORT2_RX_DIV_CLK_SRC 31 43 1.1 jmcneill #define NSS_PORT2_TX_DIV_CLK_SRC 32 44 1.1 jmcneill #define NSS_PORT3_RX_DIV_CLK_SRC 33 45 1.1 jmcneill #define NSS_PORT3_TX_DIV_CLK_SRC 34 46 1.1 jmcneill #define NSS_PORT4_RX_DIV_CLK_SRC 35 47 1.1 jmcneill #define NSS_PORT4_TX_DIV_CLK_SRC 36 48 1.1 jmcneill #define NSS_UBI0_CLK_SRC 37 49 1.1 jmcneill #define BLSP1_QUP1_I2C_APPS_CLK_SRC 38 50 1.1 jmcneill #define BLSP1_QUP1_SPI_APPS_CLK_SRC 39 51 1.1 jmcneill #define BLSP1_QUP2_I2C_APPS_CLK_SRC 40 52 1.1 jmcneill #define BLSP1_QUP2_SPI_APPS_CLK_SRC 41 53 1.1 jmcneill #define BLSP1_QUP3_I2C_APPS_CLK_SRC 42 54 1.1 jmcneill #define BLSP1_QUP3_SPI_APPS_CLK_SRC 43 55 1.1 jmcneill #define BLSP1_QUP4_I2C_APPS_CLK_SRC 44 56 1.1 jmcneill #define BLSP1_QUP4_SPI_APPS_CLK_SRC 45 57 1.1 jmcneill #define BLSP1_QUP5_I2C_APPS_CLK_SRC 46 58 1.1 jmcneill #define BLSP1_QUP5_SPI_APPS_CLK_SRC 47 59 1.1 jmcneill #define BLSP1_QUP6_I2C_APPS_CLK_SRC 48 60 1.1 jmcneill #define BLSP1_QUP6_SPI_APPS_CLK_SRC 49 61 1.1 jmcneill #define BLSP1_UART1_APPS_CLK_SRC 50 62 1.1 jmcneill #define BLSP1_UART2_APPS_CLK_SRC 51 63 1.1 jmcneill #define BLSP1_UART3_APPS_CLK_SRC 52 64 1.1 jmcneill #define BLSP1_UART4_APPS_CLK_SRC 53 65 1.1 jmcneill #define BLSP1_UART5_APPS_CLK_SRC 54 66 1.1 jmcneill #define BLSP1_UART6_APPS_CLK_SRC 55 67 1.1 jmcneill #define CRYPTO_CLK_SRC 56 68 1.1 jmcneill #define NSS_UBI0_DIV_CLK_SRC 57 69 1.1 jmcneill #define PCIE0_AUX_CLK_SRC 58 70 1.1 jmcneill #define PCIE0_PIPE_CLK_SRC 59 71 1.1 jmcneill #define SDCC1_APPS_CLK_SRC 60 72 1.1 jmcneill #define USB0_AUX_CLK_SRC 61 73 1.1 jmcneill #define USB0_MOCK_UTMI_CLK_SRC 62 74 1.1 jmcneill #define USB0_PIPE_CLK_SRC 63 75 1.1 jmcneill #define USB1_MOCK_UTMI_CLK_SRC 64 76 1.1 jmcneill #define GCC_APSS_AHB_CLK 65 77 1.1 jmcneill #define GCC_APSS_AXI_CLK 66 78 1.1 jmcneill #define GCC_BLSP1_AHB_CLK 67 79 1.1 jmcneill #define GCC_BLSP1_QUP1_I2C_APPS_CLK 68 80 1.1 jmcneill #define GCC_BLSP1_QUP1_SPI_APPS_CLK 69 81 1.1 jmcneill #define GCC_BLSP1_QUP2_I2C_APPS_CLK 70 82 1.1 jmcneill #define GCC_BLSP1_QUP2_SPI_APPS_CLK 71 83 1.1 jmcneill #define GCC_BLSP1_QUP3_I2C_APPS_CLK 72 84 1.1 jmcneill #define GCC_BLSP1_QUP3_SPI_APPS_CLK 73 85 1.1 jmcneill #define GCC_BLSP1_QUP4_I2C_APPS_CLK 74 86 1.1 jmcneill #define GCC_BLSP1_QUP4_SPI_APPS_CLK 75 87 1.1 jmcneill #define GCC_BLSP1_QUP5_I2C_APPS_CLK 76 88 1.1 jmcneill #define GCC_BLSP1_QUP5_SPI_APPS_CLK 77 89 1.1 jmcneill #define GCC_BLSP1_QUP6_I2C_APPS_CLK 78 90 1.1 jmcneill #define GCC_BLSP1_QUP6_SPI_APPS_CLK 79 91 1.1 jmcneill #define GCC_BLSP1_UART1_APPS_CLK 80 92 1.1 jmcneill #define GCC_BLSP1_UART2_APPS_CLK 81 93 1.1 jmcneill #define GCC_BLSP1_UART3_APPS_CLK 82 94 1.1 jmcneill #define GCC_BLSP1_UART4_APPS_CLK 83 95 1.1 jmcneill #define GCC_BLSP1_UART5_APPS_CLK 84 96 1.1 jmcneill #define GCC_BLSP1_UART6_APPS_CLK 85 97 1.1 jmcneill #define GCC_CRYPTO_AHB_CLK 86 98 1.1 jmcneill #define GCC_CRYPTO_AXI_CLK 87 99 1.1 jmcneill #define GCC_CRYPTO_CLK 88 100 1.1 jmcneill #define GCC_XO_CLK 89 101 1.1 jmcneill #define GCC_XO_DIV4_CLK 90 102 1.1 jmcneill #define GCC_MDIO_AHB_CLK 91 103 1.1 jmcneill #define GCC_CRYPTO_PPE_CLK 92 104 1.1 jmcneill #define GCC_NSS_CE_APB_CLK 93 105 1.1 jmcneill #define GCC_NSS_CE_AXI_CLK 94 106 1.1 jmcneill #define GCC_NSS_CFG_CLK 95 107 1.1 jmcneill #define GCC_NSS_CRYPTO_CLK 96 108 1.1 jmcneill #define GCC_NSS_CSR_CLK 97 109 1.1 jmcneill #define GCC_NSS_EDMA_CFG_CLK 98 110 1.1 jmcneill #define GCC_NSS_EDMA_CLK 99 111 1.1 jmcneill #define GCC_NSS_NOC_CLK 100 112 1.1 jmcneill #define GCC_NSS_PORT1_RX_CLK 101 113 1.1 jmcneill #define GCC_NSS_PORT1_TX_CLK 102 114 1.1 jmcneill #define GCC_NSS_PORT2_RX_CLK 103 115 1.1 jmcneill #define GCC_NSS_PORT2_TX_CLK 104 116 1.1 jmcneill #define GCC_NSS_PORT3_RX_CLK 105 117 1.1 jmcneill #define GCC_NSS_PORT3_TX_CLK 106 118 1.1 jmcneill #define GCC_NSS_PORT4_RX_CLK 107 119 1.1 jmcneill #define GCC_NSS_PORT4_TX_CLK 108 120 1.1 jmcneill #define GCC_NSS_PORT5_RX_CLK 109 121 1.1 jmcneill #define GCC_NSS_PORT5_TX_CLK 110 122 1.1 jmcneill #define GCC_NSS_PPE_CFG_CLK 111 123 1.1 jmcneill #define GCC_NSS_PPE_CLK 112 124 1.1 jmcneill #define GCC_NSS_PPE_IPE_CLK 113 125 1.1 jmcneill #define GCC_NSS_PTP_REF_CLK 114 126 1.1 jmcneill #define GCC_NSSNOC_CE_APB_CLK 115 127 1.1 jmcneill #define GCC_NSSNOC_CE_AXI_CLK 116 128 1.1 jmcneill #define GCC_NSSNOC_CRYPTO_CLK 117 129 1.1 jmcneill #define GCC_NSSNOC_PPE_CFG_CLK 118 130 1.1 jmcneill #define GCC_NSSNOC_PPE_CLK 119 131 1.1 jmcneill #define GCC_NSSNOC_QOSGEN_REF_CLK 120 132 1.1 jmcneill #define GCC_NSSNOC_TIMEOUT_REF_CLK 121 133 1.1 jmcneill #define GCC_NSSNOC_UBI0_AHB_CLK 122 134 1.1 jmcneill #define GCC_PORT1_MAC_CLK 123 135 1.1 jmcneill #define GCC_PORT2_MAC_CLK 124 136 1.1 jmcneill #define GCC_PORT3_MAC_CLK 125 137 1.1 jmcneill #define GCC_PORT4_MAC_CLK 126 138 1.1 jmcneill #define GCC_PORT5_MAC_CLK 127 139 1.1 jmcneill #define GCC_UBI0_AHB_CLK 128 140 1.1 jmcneill #define GCC_UBI0_AXI_CLK 129 141 1.1 jmcneill #define GCC_UBI0_CORE_CLK 130 142 1.1 jmcneill #define GCC_PCIE0_AHB_CLK 131 143 1.1 jmcneill #define GCC_PCIE0_AUX_CLK 132 144 1.1 jmcneill #define GCC_PCIE0_AXI_M_CLK 133 145 1.1 jmcneill #define GCC_PCIE0_AXI_S_CLK 134 146 1.1 jmcneill #define GCC_PCIE0_PIPE_CLK 135 147 1.1 jmcneill #define GCC_PRNG_AHB_CLK 136 148 1.1 jmcneill #define GCC_QPIC_AHB_CLK 137 149 1.1 jmcneill #define GCC_QPIC_CLK 138 150 1.1 jmcneill #define GCC_SDCC1_AHB_CLK 139 151 1.1 jmcneill #define GCC_SDCC1_APPS_CLK 140 152 1.1 jmcneill #define GCC_UNIPHY0_AHB_CLK 141 153 1.1 jmcneill #define GCC_UNIPHY0_PORT1_RX_CLK 142 154 1.1 jmcneill #define GCC_UNIPHY0_PORT1_TX_CLK 143 155 1.1 jmcneill #define GCC_UNIPHY0_PORT2_RX_CLK 144 156 1.1 jmcneill #define GCC_UNIPHY0_PORT2_TX_CLK 145 157 1.1 jmcneill #define GCC_UNIPHY0_PORT3_RX_CLK 146 158 1.1 jmcneill #define GCC_UNIPHY0_PORT3_TX_CLK 147 159 1.1 jmcneill #define GCC_UNIPHY0_PORT4_RX_CLK 148 160 1.1 jmcneill #define GCC_UNIPHY0_PORT4_TX_CLK 149 161 1.1 jmcneill #define GCC_UNIPHY0_PORT5_RX_CLK 150 162 1.1 jmcneill #define GCC_UNIPHY0_PORT5_TX_CLK 151 163 1.1 jmcneill #define GCC_UNIPHY0_SYS_CLK 152 164 1.1 jmcneill #define GCC_UNIPHY1_AHB_CLK 153 165 1.1 jmcneill #define GCC_UNIPHY1_PORT5_RX_CLK 154 166 1.1 jmcneill #define GCC_UNIPHY1_PORT5_TX_CLK 155 167 1.1 jmcneill #define GCC_UNIPHY1_SYS_CLK 156 168 1.1 jmcneill #define GCC_USB0_AUX_CLK 157 169 1.1 jmcneill #define GCC_USB0_MASTER_CLK 158 170 1.1 jmcneill #define GCC_USB0_MOCK_UTMI_CLK 159 171 1.1 jmcneill #define GCC_USB0_PHY_CFG_AHB_CLK 160 172 1.1 jmcneill #define GCC_USB0_PIPE_CLK 161 173 1.1 jmcneill #define GCC_USB0_SLEEP_CLK 162 174 1.1 jmcneill #define GCC_USB1_MASTER_CLK 163 175 1.1 jmcneill #define GCC_USB1_MOCK_UTMI_CLK 164 176 1.1 jmcneill #define GCC_USB1_PHY_CFG_AHB_CLK 165 177 1.1 jmcneill #define GCC_USB1_SLEEP_CLK 166 178 1.1 jmcneill #define GP1_CLK_SRC 167 179 1.1 jmcneill #define GP2_CLK_SRC 168 180 1.1 jmcneill #define GP3_CLK_SRC 169 181 1.1 jmcneill #define GCC_GP1_CLK 170 182 1.1 jmcneill #define GCC_GP2_CLK 171 183 1.1 jmcneill #define GCC_GP3_CLK 172 184 1.1 jmcneill #define SYSTEM_NOC_BFDCD_CLK_SRC 173 185 1.1 jmcneill #define GCC_NSSNOC_SNOC_CLK 174 186 1.1 jmcneill #define GCC_UBI0_NC_AXI_CLK 175 187 1.1 jmcneill #define GCC_UBI1_NC_AXI_CLK 176 188 1.1 jmcneill #define GPLL0_MAIN 177 189 1.1 jmcneill #define UBI32_PLL_MAIN 178 190 1.1 jmcneill #define GPLL6_MAIN 179 191 1.1 jmcneill #define GPLL4_MAIN 180 192 1.1 jmcneill #define GPLL2_MAIN 181 193 1.1 jmcneill #define NSS_CRYPTO_PLL_MAIN 182 194 1.1 jmcneill #define GCC_CMN_12GPLL_AHB_CLK 183 195 1.1 jmcneill #define GCC_CMN_12GPLL_SYS_CLK 184 196 1.1 jmcneill #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185 197 1.1 jmcneill #define GCC_SYS_NOC_USB0_AXI_CLK 186 198 1.1 jmcneill #define GCC_SYS_NOC_PCIE0_AXI_CLK 187 199 1.1 jmcneill #define QDSS_TSCTR_CLK_SRC 188 200 1.1 jmcneill #define QDSS_AT_CLK_SRC 189 201 1.1 jmcneill #define GCC_QDSS_AT_CLK 190 202 1.1 jmcneill #define GCC_QDSS_DAP_CLK 191 203 1.1 jmcneill #define ADSS_PWM_CLK_SRC 192 204 1.1 jmcneill #define GCC_ADSS_PWM_CLK 193 205 1.1 jmcneill #define SDCC1_ICE_CORE_CLK_SRC 194 206 1.1 jmcneill #define GCC_SDCC1_ICE_CORE_CLK 195 207 1.1 jmcneill #define GCC_DCC_CLK 196 208 1.1 jmcneill #define PCIE0_RCHNG_CLK_SRC 197 209 1.1 jmcneill #define GCC_PCIE0_AXI_S_BRIDGE_CLK 198 210 1.1 jmcneill #define PCIE0_RCHNG_CLK 199 211 1.1 jmcneill #define UBI32_MEM_NOC_BFDCD_CLK_SRC 200 212 1.1 jmcneill #define WCSS_AHB_CLK_SRC 201 213 1.1 jmcneill #define Q6_AXI_CLK_SRC 202 214 1.1 jmcneill #define GCC_Q6SS_PCLKDBG_CLK 203 215 1.1 jmcneill #define GCC_Q6_TSCTR_1TO2_CLK 204 216 1.1 jmcneill #define GCC_WCSS_CORE_TBU_CLK 205 217 1.1 jmcneill #define GCC_WCSS_AXI_M_CLK 206 218 1.1 jmcneill #define GCC_SYS_NOC_WCSS_AHB_CLK 207 219 1.1 jmcneill #define GCC_Q6_AXIM_CLK 208 220 1.1 jmcneill #define GCC_Q6SS_ATBM_CLK 209 221 1.1 jmcneill #define GCC_WCSS_Q6_TBU_CLK 210 222 1.1 jmcneill #define GCC_Q6_AXIM2_CLK 211 223 1.1 jmcneill #define GCC_Q6_AHB_CLK 212 224 1.1 jmcneill #define GCC_Q6_AHB_S_CLK 213 225 1.1 jmcneill #define GCC_WCSS_DBG_IFC_APB_CLK 214 226 1.1 jmcneill #define GCC_WCSS_DBG_IFC_ATB_CLK 215 227 1.1 jmcneill #define GCC_WCSS_DBG_IFC_NTS_CLK 216 228 1.1 jmcneill #define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217 229 1.1 jmcneill #define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218 230 1.1 jmcneill #define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219 231 1.1 jmcneill #define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220 232 1.1 jmcneill #define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221 233 1.1 jmcneill #define GCC_WCSS_ECAHB_CLK 222 234 1.1 jmcneill #define GCC_WCSS_ACMT_CLK 223 235 1.1 jmcneill #define GCC_WCSS_AHB_S_CLK 224 236 1.1 jmcneill #define GCC_RBCPR_WCSS_CLK 225 237 1.1 jmcneill #define RBCPR_WCSS_CLK_SRC 226 238 1.1 jmcneill #define GCC_RBCPR_WCSS_AHB_CLK 227 239 1.1 jmcneill #define GCC_LPASS_CORE_AXIM_CLK 228 240 1.1 jmcneill #define GCC_LPASS_SNOC_CFG_CLK 229 241 1.1 jmcneill #define GCC_LPASS_Q6_AXIM_CLK 230 242 1.1 jmcneill #define GCC_LPASS_Q6_ATBM_AT_CLK 231 243 1.1 jmcneill #define GCC_LPASS_Q6_PCLKDBG_CLK 232 244 1.1 jmcneill #define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233 245 1.1 jmcneill #define GCC_LPASS_Q6SS_TRIG_CLK 234 246 1.1 jmcneill #define GCC_LPASS_TBU_CLK 235 247 1.1 jmcneill #define LPASS_CORE_AXIM_CLK_SRC 236 248 1.1 jmcneill #define LPASS_SNOC_CFG_CLK_SRC 237 249 1.1 jmcneill #define LPASS_Q6_AXIM_CLK_SRC 238 250 1.1 jmcneill #define GCC_PCNOC_LPASS_CLK 239 251 1.1 jmcneill #define GCC_UBI0_UTCM_CLK 240 252 1.1 jmcneill #define SNOC_NSSNOC_BFDCD_CLK_SRC 241 253 1.1 jmcneill #define GCC_SNOC_NSSNOC_CLK 242 254 1.1 jmcneill #define GCC_MEM_NOC_Q6_AXI_CLK 243 255 1.1 jmcneill #define GCC_MEM_NOC_UBI32_CLK 244 256 1.1 jmcneill #define GCC_MEM_NOC_LPASS_CLK 245 257 1.1 jmcneill #define GCC_SNOC_LPASS_CFG_CLK 246 258 1.1 jmcneill #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247 259 1.1 jmcneill #define GCC_QDSS_STM_CLK 248 260 1.1 jmcneill #define GCC_QDSS_TRACECLKIN_CLK 249 261 1.1 jmcneill #define QDSS_STM_CLK_SRC 250 262 1.1 jmcneill #define QDSS_TRACECLKIN_CLK_SRC 251 263 1.1 jmcneill #define GCC_NSSNOC_ATB_CLK 252 264 1.1 jmcneill #endif 265