qcom,gcc-msm8998.h revision 1.1
1 /* $NetBSD: qcom,gcc-msm8998.h,v 1.1 2018/06/27 16:27:08 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H 17 #define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H 18 19 #define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 20 #define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 21 #define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 22 #define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 23 #define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 24 #define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 25 #define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 26 #define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 27 #define BLSP1_QUP5_I2C_APPS_CLK_SRC 8 28 #define BLSP1_QUP5_SPI_APPS_CLK_SRC 9 29 #define BLSP1_QUP6_I2C_APPS_CLK_SRC 10 30 #define BLSP1_QUP6_SPI_APPS_CLK_SRC 11 31 #define BLSP1_UART1_APPS_CLK_SRC 12 32 #define BLSP1_UART2_APPS_CLK_SRC 13 33 #define BLSP1_UART3_APPS_CLK_SRC 14 34 #define BLSP2_QUP1_I2C_APPS_CLK_SRC 15 35 #define BLSP2_QUP1_SPI_APPS_CLK_SRC 16 36 #define BLSP2_QUP2_I2C_APPS_CLK_SRC 17 37 #define BLSP2_QUP2_SPI_APPS_CLK_SRC 18 38 #define BLSP2_QUP3_I2C_APPS_CLK_SRC 19 39 #define BLSP2_QUP3_SPI_APPS_CLK_SRC 20 40 #define BLSP2_QUP4_I2C_APPS_CLK_SRC 21 41 #define BLSP2_QUP4_SPI_APPS_CLK_SRC 22 42 #define BLSP2_QUP5_I2C_APPS_CLK_SRC 23 43 #define BLSP2_QUP5_SPI_APPS_CLK_SRC 24 44 #define BLSP2_QUP6_I2C_APPS_CLK_SRC 25 45 #define BLSP2_QUP6_SPI_APPS_CLK_SRC 26 46 #define BLSP2_UART1_APPS_CLK_SRC 27 47 #define BLSP2_UART2_APPS_CLK_SRC 28 48 #define BLSP2_UART3_APPS_CLK_SRC 29 49 #define GCC_AGGRE1_NOC_XO_CLK 30 50 #define GCC_AGGRE1_UFS_AXI_CLK 31 51 #define GCC_AGGRE1_USB3_AXI_CLK 32 52 #define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33 53 #define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34 54 #define GCC_BIMC_HMSS_AXI_CLK 35 55 #define GCC_BIMC_MSS_Q6_AXI_CLK 36 56 #define GCC_BLSP1_AHB_CLK 37 57 #define GCC_BLSP1_QUP1_I2C_APPS_CLK 38 58 #define GCC_BLSP1_QUP1_SPI_APPS_CLK 39 59 #define GCC_BLSP1_QUP2_I2C_APPS_CLK 40 60 #define GCC_BLSP1_QUP2_SPI_APPS_CLK 41 61 #define GCC_BLSP1_QUP3_I2C_APPS_CLK 42 62 #define GCC_BLSP1_QUP3_SPI_APPS_CLK 43 63 #define GCC_BLSP1_QUP4_I2C_APPS_CLK 44 64 #define GCC_BLSP1_QUP4_SPI_APPS_CLK 45 65 #define GCC_BLSP1_QUP5_I2C_APPS_CLK 46 66 #define GCC_BLSP1_QUP5_SPI_APPS_CLK 47 67 #define GCC_BLSP1_QUP6_I2C_APPS_CLK 48 68 #define GCC_BLSP1_QUP6_SPI_APPS_CLK 49 69 #define GCC_BLSP1_SLEEP_CLK 50 70 #define GCC_BLSP1_UART1_APPS_CLK 51 71 #define GCC_BLSP1_UART2_APPS_CLK 52 72 #define GCC_BLSP1_UART3_APPS_CLK 53 73 #define GCC_BLSP2_AHB_CLK 54 74 #define GCC_BLSP2_QUP1_I2C_APPS_CLK 55 75 #define GCC_BLSP2_QUP1_SPI_APPS_CLK 56 76 #define GCC_BLSP2_QUP2_I2C_APPS_CLK 57 77 #define GCC_BLSP2_QUP2_SPI_APPS_CLK 58 78 #define GCC_BLSP2_QUP3_I2C_APPS_CLK 59 79 #define GCC_BLSP2_QUP3_SPI_APPS_CLK 60 80 #define GCC_BLSP2_QUP4_I2C_APPS_CLK 61 81 #define GCC_BLSP2_QUP4_SPI_APPS_CLK 62 82 #define GCC_BLSP2_QUP5_I2C_APPS_CLK 63 83 #define GCC_BLSP2_QUP5_SPI_APPS_CLK 64 84 #define GCC_BLSP2_QUP6_I2C_APPS_CLK 65 85 #define GCC_BLSP2_QUP6_SPI_APPS_CLK 66 86 #define GCC_BLSP2_SLEEP_CLK 67 87 #define GCC_BLSP2_UART1_APPS_CLK 68 88 #define GCC_BLSP2_UART2_APPS_CLK 69 89 #define GCC_BLSP2_UART3_APPS_CLK 70 90 #define GCC_CFG_NOC_USB3_AXI_CLK 71 91 #define GCC_GP1_CLK 72 92 #define GCC_GP2_CLK 73 93 #define GCC_GP3_CLK 74 94 #define GCC_GPU_BIMC_GFX_CLK 75 95 #define GCC_GPU_BIMC_GFX_SRC_CLK 76 96 #define GCC_GPU_CFG_AHB_CLK 77 97 #define GCC_GPU_SNOC_DVM_GFX_CLK 78 98 #define GCC_HMSS_AHB_CLK 79 99 #define GCC_HMSS_AT_CLK 80 100 #define GCC_HMSS_DVM_BUS_CLK 81 101 #define GCC_HMSS_RBCPR_CLK 82 102 #define GCC_HMSS_TRIG_CLK 83 103 #define GCC_LPASS_AT_CLK 84 104 #define GCC_LPASS_TRIG_CLK 85 105 #define GCC_MMSS_NOC_CFG_AHB_CLK 86 106 #define GCC_MMSS_QM_AHB_CLK 87 107 #define GCC_MMSS_QM_CORE_CLK 88 108 #define GCC_MMSS_SYS_NOC_AXI_CLK 89 109 #define GCC_MSS_AT_CLK 90 110 #define GCC_PCIE_0_AUX_CLK 91 111 #define GCC_PCIE_0_CFG_AHB_CLK 92 112 #define GCC_PCIE_0_MSTR_AXI_CLK 93 113 #define GCC_PCIE_0_PIPE_CLK 94 114 #define GCC_PCIE_0_SLV_AXI_CLK 95 115 #define GCC_PCIE_PHY_AUX_CLK 96 116 #define GCC_PDM2_CLK 97 117 #define GCC_PDM_AHB_CLK 98 118 #define GCC_PDM_XO4_CLK 99 119 #define GCC_PRNG_AHB_CLK 100 120 #define GCC_SDCC2_AHB_CLK 101 121 #define GCC_SDCC2_APPS_CLK 102 122 #define GCC_SDCC4_AHB_CLK 103 123 #define GCC_SDCC4_APPS_CLK 104 124 #define GCC_TSIF_AHB_CLK 105 125 #define GCC_TSIF_INACTIVITY_TIMERS_CLK 106 126 #define GCC_TSIF_REF_CLK 107 127 #define GCC_UFS_AHB_CLK 108 128 #define GCC_UFS_AXI_CLK 109 129 #define GCC_UFS_ICE_CORE_CLK 110 130 #define GCC_UFS_PHY_AUX_CLK 111 131 #define GCC_UFS_RX_SYMBOL_0_CLK 112 132 #define GCC_UFS_RX_SYMBOL_1_CLK 113 133 #define GCC_UFS_TX_SYMBOL_0_CLK 114 134 #define GCC_UFS_UNIPRO_CORE_CLK 115 135 #define GCC_USB30_MASTER_CLK 116 136 #define GCC_USB30_MOCK_UTMI_CLK 117 137 #define GCC_USB30_SLEEP_CLK 118 138 #define GCC_USB3_PHY_AUX_CLK 119 139 #define GCC_USB3_PHY_PIPE_CLK 120 140 #define GCC_USB_PHY_CFG_AHB2PHY_CLK 121 141 #define GP1_CLK_SRC 122 142 #define GP2_CLK_SRC 123 143 #define GP3_CLK_SRC 124 144 #define GPLL0 125 145 #define GPLL0_OUT_EVEN 126 146 #define GPLL0_OUT_MAIN 127 147 #define GPLL0_OUT_ODD 128 148 #define GPLL0_OUT_TEST 129 149 #define GPLL1 130 150 #define GPLL1_OUT_EVEN 131 151 #define GPLL1_OUT_MAIN 132 152 #define GPLL1_OUT_ODD 133 153 #define GPLL1_OUT_TEST 134 154 #define GPLL2 135 155 #define GPLL2_OUT_EVEN 136 156 #define GPLL2_OUT_MAIN 137 157 #define GPLL2_OUT_ODD 138 158 #define GPLL2_OUT_TEST 139 159 #define GPLL3 140 160 #define GPLL3_OUT_EVEN 141 161 #define GPLL3_OUT_MAIN 142 162 #define GPLL3_OUT_ODD 143 163 #define GPLL3_OUT_TEST 144 164 #define GPLL4 145 165 #define GPLL4_OUT_EVEN 146 166 #define GPLL4_OUT_MAIN 147 167 #define GPLL4_OUT_ODD 148 168 #define GPLL4_OUT_TEST 149 169 #define GPLL6 150 170 #define GPLL6_OUT_EVEN 151 171 #define GPLL6_OUT_MAIN 152 172 #define GPLL6_OUT_ODD 153 173 #define GPLL6_OUT_TEST 154 174 #define HMSS_AHB_CLK_SRC 155 175 #define HMSS_RBCPR_CLK_SRC 156 176 #define PCIE_AUX_CLK_SRC 157 177 #define PDM2_CLK_SRC 158 178 #define SDCC2_APPS_CLK_SRC 159 179 #define SDCC4_APPS_CLK_SRC 160 180 #define TSIF_REF_CLK_SRC 161 181 #define UFS_AXI_CLK_SRC 162 182 #define USB30_MASTER_CLK_SRC 163 183 #define USB30_MOCK_UTMI_CLK_SRC 164 184 #define USB3_PHY_AUX_CLK_SRC 165 185 186 #define PCIE_0_GDSC 0 187 #define UFS_GDSC 1 188 #define USB_30_GDSC 2 189 190 #define GCC_BLSP1_QUP1_BCR 0 191 #define GCC_BLSP1_QUP2_BCR 1 192 #define GCC_BLSP1_QUP3_BCR 2 193 #define GCC_BLSP1_QUP4_BCR 3 194 #define GCC_BLSP1_QUP5_BCR 4 195 #define GCC_BLSP1_QUP6_BCR 5 196 #define GCC_BLSP2_QUP1_BCR 6 197 #define GCC_BLSP2_QUP2_BCR 7 198 #define GCC_BLSP2_QUP3_BCR 8 199 #define GCC_BLSP2_QUP4_BCR 9 200 #define GCC_BLSP2_QUP5_BCR 10 201 #define GCC_BLSP2_QUP6_BCR 11 202 #define GCC_PCIE_0_BCR 12 203 #define GCC_PDM_BCR 13 204 #define GCC_SDCC2_BCR 14 205 #define GCC_SDCC4_BCR 15 206 #define GCC_TSIF_BCR 16 207 #define GCC_UFS_BCR 17 208 #define GCC_USB_30_BCR 18 209 210 #endif 211
Indexes created Sun Oct 19 02:09:48 GMT 2025