1 1.1 jmcneill /* $NetBSD: qcom,gcc-qcs404.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 1.1 jmcneill */ 7 1.1 jmcneill 8 1.1 jmcneill #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 9 1.1 jmcneill #define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 10 1.1 jmcneill 11 1.1 jmcneill #define GCC_APSS_AHB_CLK_SRC 0 12 1.1 jmcneill #define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 13 1.1 jmcneill #define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 14 1.1 jmcneill #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 15 1.1 jmcneill #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 16 1.1 jmcneill #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 17 1.1 jmcneill #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 18 1.1 jmcneill #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 19 1.1 jmcneill #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 20 1.1 jmcneill #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 21 1.1 jmcneill #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 22 1.1 jmcneill #define GCC_BLSP1_UART0_APPS_CLK_SRC 11 23 1.1 jmcneill #define GCC_BLSP1_UART1_APPS_CLK_SRC 12 24 1.1 jmcneill #define GCC_BLSP1_UART2_APPS_CLK_SRC 13 25 1.1 jmcneill #define GCC_BLSP1_UART3_APPS_CLK_SRC 14 26 1.1 jmcneill #define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 27 1.1 jmcneill #define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 28 1.1 jmcneill #define GCC_BLSP2_UART0_APPS_CLK_SRC 17 29 1.1 jmcneill #define GCC_BYTE0_CLK_SRC 18 30 1.1 jmcneill #define GCC_EMAC_CLK_SRC 19 31 1.1 jmcneill #define GCC_EMAC_PTP_CLK_SRC 20 32 1.1 jmcneill #define GCC_ESC0_CLK_SRC 21 33 1.1 jmcneill #define GCC_APSS_AHB_CLK 22 34 1.1 jmcneill #define GCC_APSS_AXI_CLK 23 35 1.1 jmcneill #define GCC_BIMC_APSS_AXI_CLK 24 36 1.1 jmcneill #define GCC_BIMC_GFX_CLK 25 37 1.1 jmcneill #define GCC_BIMC_MDSS_CLK 26 38 1.1 jmcneill #define GCC_BLSP1_AHB_CLK 27 39 1.1 jmcneill #define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 40 1.1 jmcneill #define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 41 1.1 jmcneill #define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 42 1.1 jmcneill #define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 43 1.1 jmcneill #define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 44 1.1 jmcneill #define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 45 1.1 jmcneill #define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 46 1.1 jmcneill #define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 47 1.1 jmcneill #define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 48 1.1 jmcneill #define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 49 1.1 jmcneill #define GCC_BLSP1_UART0_APPS_CLK 38 50 1.1 jmcneill #define GCC_BLSP1_UART1_APPS_CLK 39 51 1.1 jmcneill #define GCC_BLSP1_UART2_APPS_CLK 40 52 1.1 jmcneill #define GCC_BLSP1_UART3_APPS_CLK 41 53 1.1 jmcneill #define GCC_BLSP2_AHB_CLK 42 54 1.1 jmcneill #define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 55 1.1 jmcneill #define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 56 1.1 jmcneill #define GCC_BLSP2_UART0_APPS_CLK 45 57 1.1 jmcneill #define GCC_BOOT_ROM_AHB_CLK 46 58 1.1 jmcneill #define GCC_DCC_CLK 47 59 1.1 jmcneill #define GCC_GENI_IR_H_CLK 48 60 1.1 jmcneill #define GCC_ETH_AXI_CLK 49 61 1.1 jmcneill #define GCC_ETH_PTP_CLK 50 62 1.1 jmcneill #define GCC_ETH_RGMII_CLK 51 63 1.1 jmcneill #define GCC_ETH_SLAVE_AHB_CLK 52 64 1.1 jmcneill #define GCC_GENI_IR_S_CLK 53 65 1.1 jmcneill #define GCC_GP1_CLK 54 66 1.1 jmcneill #define GCC_GP2_CLK 55 67 1.1 jmcneill #define GCC_GP3_CLK 56 68 1.1 jmcneill #define GCC_MDSS_AHB_CLK 57 69 1.1 jmcneill #define GCC_MDSS_AXI_CLK 58 70 1.1 jmcneill #define GCC_MDSS_BYTE0_CLK 59 71 1.1 jmcneill #define GCC_MDSS_ESC0_CLK 60 72 1.1 jmcneill #define GCC_MDSS_HDMI_APP_CLK 61 73 1.1 jmcneill #define GCC_MDSS_HDMI_PCLK_CLK 62 74 1.1 jmcneill #define GCC_MDSS_MDP_CLK 63 75 1.1 jmcneill #define GCC_MDSS_PCLK0_CLK 64 76 1.1 jmcneill #define GCC_MDSS_VSYNC_CLK 65 77 1.1 jmcneill #define GCC_OXILI_AHB_CLK 66 78 1.1 jmcneill #define GCC_OXILI_GFX3D_CLK 67 79 1.1 jmcneill #define GCC_PCIE_0_AUX_CLK 68 80 1.1 jmcneill #define GCC_PCIE_0_CFG_AHB_CLK 69 81 1.1 jmcneill #define GCC_PCIE_0_MSTR_AXI_CLK 70 82 1.1 jmcneill #define GCC_PCIE_0_PIPE_CLK 71 83 1.1 jmcneill #define GCC_PCIE_0_SLV_AXI_CLK 72 84 1.1 jmcneill #define GCC_PCNOC_USB2_CLK 73 85 1.1 jmcneill #define GCC_PCNOC_USB3_CLK 74 86 1.1 jmcneill #define GCC_PDM2_CLK 75 87 1.1 jmcneill #define GCC_PDM_AHB_CLK 76 88 1.1 jmcneill #define GCC_VSYNC_CLK_SRC 77 89 1.1 jmcneill #define GCC_PRNG_AHB_CLK 78 90 1.1 jmcneill #define GCC_PWM0_XO512_CLK 79 91 1.1 jmcneill #define GCC_PWM1_XO512_CLK 80 92 1.1 jmcneill #define GCC_PWM2_XO512_CLK 81 93 1.1 jmcneill #define GCC_SDCC1_AHB_CLK 82 94 1.1 jmcneill #define GCC_SDCC1_APPS_CLK 83 95 1.1 jmcneill #define GCC_SDCC1_ICE_CORE_CLK 84 96 1.1 jmcneill #define GCC_SDCC2_AHB_CLK 85 97 1.1 jmcneill #define GCC_SDCC2_APPS_CLK 86 98 1.1 jmcneill #define GCC_SYS_NOC_USB3_CLK 87 99 1.1 jmcneill #define GCC_USB20_MOCK_UTMI_CLK 88 100 1.1 jmcneill #define GCC_USB2A_PHY_SLEEP_CLK 89 101 1.1 jmcneill #define GCC_USB30_MASTER_CLK 90 102 1.1 jmcneill #define GCC_USB30_MOCK_UTMI_CLK 91 103 1.1 jmcneill #define GCC_USB30_SLEEP_CLK 92 104 1.1 jmcneill #define GCC_USB3_PHY_AUX_CLK 93 105 1.1 jmcneill #define GCC_USB3_PHY_PIPE_CLK 94 106 1.1 jmcneill #define GCC_USB_HS_PHY_CFG_AHB_CLK 95 107 1.1 jmcneill #define GCC_USB_HS_SYSTEM_CLK 96 108 1.1 jmcneill #define GCC_GFX3D_CLK_SRC 97 109 1.1 jmcneill #define GCC_GP1_CLK_SRC 98 110 1.1 jmcneill #define GCC_GP2_CLK_SRC 99 111 1.1 jmcneill #define GCC_GP3_CLK_SRC 100 112 1.1 jmcneill #define GCC_GPLL0_OUT_MAIN 101 113 1.1 jmcneill #define GCC_GPLL1_OUT_MAIN 102 114 1.1 jmcneill #define GCC_GPLL3_OUT_MAIN 103 115 1.1 jmcneill #define GCC_GPLL4_OUT_MAIN 104 116 1.1 jmcneill #define GCC_HDMI_APP_CLK_SRC 105 117 1.1 jmcneill #define GCC_HDMI_PCLK_CLK_SRC 106 118 1.1 jmcneill #define GCC_MDP_CLK_SRC 107 119 1.1 jmcneill #define GCC_PCIE_0_AUX_CLK_SRC 108 120 1.1 jmcneill #define GCC_PCIE_0_PIPE_CLK_SRC 109 121 1.1 jmcneill #define GCC_PCLK0_CLK_SRC 110 122 1.1 jmcneill #define GCC_PDM2_CLK_SRC 111 123 1.1 jmcneill #define GCC_SDCC1_APPS_CLK_SRC 112 124 1.1 jmcneill #define GCC_SDCC1_ICE_CORE_CLK_SRC 113 125 1.1 jmcneill #define GCC_SDCC2_APPS_CLK_SRC 114 126 1.1 jmcneill #define GCC_USB20_MOCK_UTMI_CLK_SRC 115 127 1.1 jmcneill #define GCC_USB30_MASTER_CLK_SRC 116 128 1.1 jmcneill #define GCC_USB30_MOCK_UTMI_CLK_SRC 117 129 1.1 jmcneill #define GCC_USB3_PHY_AUX_CLK_SRC 118 130 1.1 jmcneill #define GCC_USB_HS_SYSTEM_CLK_SRC 119 131 1.1 jmcneill #define GCC_GPLL0_AO_CLK_SRC 120 132 1.1 jmcneill #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 133 1.1 jmcneill #define GCC_GPLL0_AO_OUT_MAIN 123 134 1.1 jmcneill #define GCC_GPLL0_SLEEP_CLK_SRC 124 135 1.1 jmcneill #define GCC_GPLL6 125 136 1.1 jmcneill #define GCC_GPLL6_OUT_AUX 126 137 1.1 jmcneill #define GCC_MDSS_MDP_VOTE_CLK 127 138 1.1 jmcneill #define GCC_MDSS_ROTATOR_VOTE_CLK 128 139 1.1 jmcneill #define GCC_BIMC_GPU_CLK 129 140 1.1 jmcneill #define GCC_GTCU_AHB_CLK 130 141 1.1 jmcneill #define GCC_GFX_TCU_CLK 131 142 1.1 jmcneill #define GCC_GFX_TBU_CLK 132 143 1.1 jmcneill #define GCC_SMMU_CFG_CLK 133 144 1.1 jmcneill #define GCC_APSS_TCU_CLK 134 145 1.1 jmcneill #define GCC_CRYPTO_AHB_CLK 135 146 1.1 jmcneill #define GCC_CRYPTO_AXI_CLK 136 147 1.1 jmcneill #define GCC_CRYPTO_CLK 137 148 1.1 jmcneill #define GCC_MDP_TBU_CLK 138 149 1.1 jmcneill #define GCC_QDSS_DAP_CLK 139 150 1.1 jmcneill #define GCC_DCC_XO_CLK 140 151 1.1.1.2 skrll #define GCC_WCSS_Q6_AHB_CLK 141 152 1.1.1.2 skrll #define GCC_WCSS_Q6_AXIM_CLK 142 153 1.1.1.2 skrll #define GCC_CDSP_CFG_AHB_CLK 143 154 1.1.1.2 skrll #define GCC_BIMC_CDSP_CLK 144 155 1.1.1.2 skrll #define GCC_CDSP_TBU_CLK 145 156 1.1.1.2 skrll #define GCC_CDSP_BIMC_CLK_SRC 146 157 1.1 jmcneill 158 1.1 jmcneill #define GCC_GENI_IR_BCR 0 159 1.1 jmcneill #define GCC_USB_HS_BCR 1 160 1.1 jmcneill #define GCC_USB2_HS_PHY_ONLY_BCR 2 161 1.1 jmcneill #define GCC_QUSB2_PHY_BCR 3 162 1.1 jmcneill #define GCC_USB_HS_PHY_CFG_AHB_BCR 4 163 1.1 jmcneill #define GCC_USB2A_PHY_BCR 5 164 1.1 jmcneill #define GCC_USB3_PHY_BCR 6 165 1.1 jmcneill #define GCC_USB_30_BCR 7 166 1.1 jmcneill #define GCC_USB3PHY_PHY_BCR 8 167 1.1 jmcneill #define GCC_PCIE_0_BCR 9 168 1.1 jmcneill #define GCC_PCIE_0_PHY_BCR 10 169 1.1 jmcneill #define GCC_PCIE_0_LINK_DOWN_BCR 11 170 1.1 jmcneill #define GCC_PCIEPHY_0_PHY_BCR 12 171 1.1 jmcneill #define GCC_EMAC_BCR 13 172 1.1.1.2 skrll #define GCC_CDSP_RESTART 14 173 1.1.1.2 skrll #define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 174 1.1.1.2 skrll #define GCC_PCIE_0_AHB_ARES 16 175 1.1.1.2 skrll #define GCC_PCIE_0_AXI_SLAVE_ARES 17 176 1.1.1.2 skrll #define GCC_PCIE_0_AXI_MASTER_ARES 18 177 1.1.1.2 skrll #define GCC_PCIE_0_CORE_STICKY_ARES 19 178 1.1.1.2 skrll #define GCC_PCIE_0_SLEEP_ARES 20 179 1.1.1.2 skrll #define GCC_PCIE_0_PIPE_ARES 21 180 1.1.1.2 skrll #define GCC_WDSP_RESTART 22 181 1.1 jmcneill 182 1.1 jmcneill #endif 183