1 1.1 jmcneill /* $NetBSD: qcom,gcc-sc8180x.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 1.1 jmcneill * Copyright (c) 2021, Linaro Ltd. 7 1.1 jmcneill */ 8 1.1 jmcneill 9 1.1 jmcneill #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H 10 1.1 jmcneill #define _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H 11 1.1 jmcneill 12 1.1 jmcneill #define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 13 1.1 jmcneill #define GCC_AGGRE_UFS_CARD_AXI_CLK 1 14 1.1 jmcneill #define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 15 1.1 jmcneill #define GCC_AGGRE_UFS_PHY_AXI_CLK 3 16 1.1 jmcneill #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 17 1.1 jmcneill #define GCC_AGGRE_USB3_MP_AXI_CLK 5 18 1.1 jmcneill #define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 19 1.1 jmcneill #define GCC_AGGRE_USB3_SEC_AXI_CLK 7 20 1.1 jmcneill #define GCC_BOOT_ROM_AHB_CLK 8 21 1.1 jmcneill #define GCC_CAMERA_HF_AXI_CLK 9 22 1.1 jmcneill #define GCC_CAMERA_SF_AXI_CLK 10 23 1.1 jmcneill #define GCC_CFG_NOC_USB3_MP_AXI_CLK 11 24 1.1 jmcneill #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 25 1.1 jmcneill #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 26 1.1 jmcneill #define GCC_CPUSS_AHB_CLK 14 27 1.1 jmcneill #define GCC_CPUSS_AHB_CLK_SRC 15 28 1.1 jmcneill #define GCC_CPUSS_RBCPR_CLK 16 29 1.1 jmcneill #define GCC_DDRSS_GPU_AXI_CLK 17 30 1.1 jmcneill #define GCC_DISP_HF_AXI_CLK 18 31 1.1 jmcneill #define GCC_DISP_SF_AXI_CLK 19 32 1.1 jmcneill #define GCC_EMAC_AXI_CLK 20 33 1.1 jmcneill #define GCC_EMAC_PTP_CLK 21 34 1.1 jmcneill #define GCC_EMAC_PTP_CLK_SRC 22 35 1.1 jmcneill #define GCC_EMAC_RGMII_CLK 23 36 1.1 jmcneill #define GCC_EMAC_RGMII_CLK_SRC 24 37 1.1 jmcneill #define GCC_EMAC_SLV_AHB_CLK 25 38 1.1 jmcneill #define GCC_GP1_CLK 26 39 1.1 jmcneill #define GCC_GP1_CLK_SRC 27 40 1.1 jmcneill #define GCC_GP2_CLK 28 41 1.1 jmcneill #define GCC_GP2_CLK_SRC 29 42 1.1 jmcneill #define GCC_GP3_CLK 30 43 1.1 jmcneill #define GCC_GP3_CLK_SRC 31 44 1.1 jmcneill #define GCC_GP4_CLK 32 45 1.1 jmcneill #define GCC_GP4_CLK_SRC 33 46 1.1 jmcneill #define GCC_GP5_CLK 34 47 1.1 jmcneill #define GCC_GP5_CLK_SRC 35 48 1.1 jmcneill #define GCC_GPU_GPLL0_CLK_SRC 36 49 1.1 jmcneill #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 50 1.1 jmcneill #define GCC_GPU_MEMNOC_GFX_CLK 38 51 1.1 jmcneill #define GCC_GPU_SNOC_DVM_GFX_CLK 39 52 1.1 jmcneill #define GCC_NPU_AT_CLK 40 53 1.1 jmcneill #define GCC_NPU_AXI_CLK 41 54 1.1 jmcneill #define GCC_NPU_AXI_CLK_SRC 42 55 1.1 jmcneill #define GCC_NPU_GPLL0_CLK_SRC 43 56 1.1 jmcneill #define GCC_NPU_GPLL0_DIV_CLK_SRC 44 57 1.1 jmcneill #define GCC_NPU_TRIG_CLK 45 58 1.1 jmcneill #define GCC_PCIE0_PHY_REFGEN_CLK 46 59 1.1 jmcneill #define GCC_PCIE1_PHY_REFGEN_CLK 47 60 1.1 jmcneill #define GCC_PCIE2_PHY_REFGEN_CLK 48 61 1.1 jmcneill #define GCC_PCIE3_PHY_REFGEN_CLK 49 62 1.1 jmcneill #define GCC_PCIE_0_AUX_CLK 50 63 1.1 jmcneill #define GCC_PCIE_0_AUX_CLK_SRC 51 64 1.1 jmcneill #define GCC_PCIE_0_CFG_AHB_CLK 52 65 1.1 jmcneill #define GCC_PCIE_0_MSTR_AXI_CLK 53 66 1.1 jmcneill #define GCC_PCIE_0_PIPE_CLK 54 67 1.1 jmcneill #define GCC_PCIE_0_SLV_AXI_CLK 55 68 1.1 jmcneill #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56 69 1.1 jmcneill #define GCC_PCIE_1_AUX_CLK 57 70 1.1 jmcneill #define GCC_PCIE_1_AUX_CLK_SRC 58 71 1.1 jmcneill #define GCC_PCIE_1_CFG_AHB_CLK 59 72 1.1 jmcneill #define GCC_PCIE_1_MSTR_AXI_CLK 60 73 1.1 jmcneill #define GCC_PCIE_1_PIPE_CLK 61 74 1.1 jmcneill #define GCC_PCIE_1_SLV_AXI_CLK 62 75 1.1 jmcneill #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63 76 1.1 jmcneill #define GCC_PCIE_2_AUX_CLK 64 77 1.1 jmcneill #define GCC_PCIE_2_AUX_CLK_SRC 65 78 1.1 jmcneill #define GCC_PCIE_2_CFG_AHB_CLK 66 79 1.1 jmcneill #define GCC_PCIE_2_MSTR_AXI_CLK 67 80 1.1 jmcneill #define GCC_PCIE_2_PIPE_CLK 68 81 1.1 jmcneill #define GCC_PCIE_2_SLV_AXI_CLK 69 82 1.1 jmcneill #define GCC_PCIE_2_SLV_Q2A_AXI_CLK 70 83 1.1 jmcneill #define GCC_PCIE_3_AUX_CLK 71 84 1.1 jmcneill #define GCC_PCIE_3_AUX_CLK_SRC 72 85 1.1 jmcneill #define GCC_PCIE_3_CFG_AHB_CLK 73 86 1.1 jmcneill #define GCC_PCIE_3_MSTR_AXI_CLK 74 87 1.1 jmcneill #define GCC_PCIE_3_PIPE_CLK 75 88 1.1 jmcneill #define GCC_PCIE_3_SLV_AXI_CLK 76 89 1.1 jmcneill #define GCC_PCIE_3_SLV_Q2A_AXI_CLK 77 90 1.1 jmcneill #define GCC_PCIE_PHY_AUX_CLK 78 91 1.1 jmcneill #define GCC_PCIE_PHY_REFGEN_CLK_SRC 79 92 1.1 jmcneill #define GCC_PDM2_CLK 80 93 1.1 jmcneill #define GCC_PDM2_CLK_SRC 81 94 1.1 jmcneill #define GCC_PDM_AHB_CLK 82 95 1.1 jmcneill #define GCC_PDM_XO4_CLK 83 96 1.1 jmcneill #define GCC_PRNG_AHB_CLK 84 97 1.1 jmcneill #define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 98 1.1 jmcneill #define GCC_QMIP_CAMERA_RT_AHB_CLK 86 99 1.1 jmcneill #define GCC_QMIP_DISP_AHB_CLK 87 100 1.1 jmcneill #define GCC_QMIP_VIDEO_CVP_AHB_CLK 88 101 1.1 jmcneill #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 102 1.1 jmcneill #define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK 90 103 1.1 jmcneill #define GCC_QSPI_1_CORE_CLK 91 104 1.1 jmcneill #define GCC_QSPI_1_CORE_CLK_SRC 92 105 1.1 jmcneill #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 93 106 1.1 jmcneill #define GCC_QSPI_CORE_CLK 94 107 1.1 jmcneill #define GCC_QSPI_CORE_CLK_SRC 95 108 1.1 jmcneill #define GCC_QUPV3_WRAP0_S0_CLK 96 109 1.1 jmcneill #define GCC_QUPV3_WRAP0_S0_CLK_SRC 97 110 1.1 jmcneill #define GCC_QUPV3_WRAP0_S1_CLK 98 111 1.1 jmcneill #define GCC_QUPV3_WRAP0_S1_CLK_SRC 99 112 1.1 jmcneill #define GCC_QUPV3_WRAP0_S2_CLK 100 113 1.1 jmcneill #define GCC_QUPV3_WRAP0_S2_CLK_SRC 101 114 1.1 jmcneill #define GCC_QUPV3_WRAP0_S3_CLK 102 115 1.1 jmcneill #define GCC_QUPV3_WRAP0_S3_CLK_SRC 103 116 1.1 jmcneill #define GCC_QUPV3_WRAP0_S4_CLK 104 117 1.1 jmcneill #define GCC_QUPV3_WRAP0_S4_CLK_SRC 105 118 1.1 jmcneill #define GCC_QUPV3_WRAP0_S5_CLK 106 119 1.1 jmcneill #define GCC_QUPV3_WRAP0_S5_CLK_SRC 107 120 1.1 jmcneill #define GCC_QUPV3_WRAP0_S6_CLK 108 121 1.1 jmcneill #define GCC_QUPV3_WRAP0_S6_CLK_SRC 109 122 1.1 jmcneill #define GCC_QUPV3_WRAP0_S7_CLK 110 123 1.1 jmcneill #define GCC_QUPV3_WRAP0_S7_CLK_SRC 111 124 1.1 jmcneill #define GCC_QUPV3_WRAP1_S0_CLK 112 125 1.1 jmcneill #define GCC_QUPV3_WRAP1_S0_CLK_SRC 113 126 1.1 jmcneill #define GCC_QUPV3_WRAP1_S1_CLK 114 127 1.1 jmcneill #define GCC_QUPV3_WRAP1_S1_CLK_SRC 115 128 1.1 jmcneill #define GCC_QUPV3_WRAP1_S2_CLK 116 129 1.1 jmcneill #define GCC_QUPV3_WRAP1_S2_CLK_SRC 117 130 1.1 jmcneill #define GCC_QUPV3_WRAP1_S3_CLK 118 131 1.1 jmcneill #define GCC_QUPV3_WRAP1_S3_CLK_SRC 119 132 1.1 jmcneill #define GCC_QUPV3_WRAP1_S4_CLK 120 133 1.1 jmcneill #define GCC_QUPV3_WRAP1_S4_CLK_SRC 121 134 1.1 jmcneill #define GCC_QUPV3_WRAP1_S5_CLK 122 135 1.1 jmcneill #define GCC_QUPV3_WRAP1_S5_CLK_SRC 123 136 1.1 jmcneill #define GCC_QUPV3_WRAP2_S0_CLK 124 137 1.1 jmcneill #define GCC_QUPV3_WRAP2_S0_CLK_SRC 125 138 1.1 jmcneill #define GCC_QUPV3_WRAP2_S1_CLK 126 139 1.1 jmcneill #define GCC_QUPV3_WRAP2_S1_CLK_SRC 127 140 1.1 jmcneill #define GCC_QUPV3_WRAP2_S2_CLK 128 141 1.1 jmcneill #define GCC_QUPV3_WRAP2_S2_CLK_SRC 129 142 1.1 jmcneill #define GCC_QUPV3_WRAP2_S3_CLK 130 143 1.1 jmcneill #define GCC_QUPV3_WRAP2_S3_CLK_SRC 131 144 1.1 jmcneill #define GCC_QUPV3_WRAP2_S4_CLK 132 145 1.1 jmcneill #define GCC_QUPV3_WRAP2_S4_CLK_SRC 133 146 1.1 jmcneill #define GCC_QUPV3_WRAP2_S5_CLK 134 147 1.1 jmcneill #define GCC_QUPV3_WRAP2_S5_CLK_SRC 135 148 1.1 jmcneill #define GCC_QUPV3_WRAP_0_M_AHB_CLK 136 149 1.1 jmcneill #define GCC_QUPV3_WRAP_0_S_AHB_CLK 137 150 1.1 jmcneill #define GCC_QUPV3_WRAP_1_M_AHB_CLK 138 151 1.1 jmcneill #define GCC_QUPV3_WRAP_1_S_AHB_CLK 139 152 1.1 jmcneill #define GCC_QUPV3_WRAP_2_M_AHB_CLK 140 153 1.1 jmcneill #define GCC_QUPV3_WRAP_2_S_AHB_CLK 141 154 1.1 jmcneill #define GCC_SDCC2_AHB_CLK 142 155 1.1 jmcneill #define GCC_SDCC2_APPS_CLK 143 156 1.1 jmcneill #define GCC_SDCC2_APPS_CLK_SRC 144 157 1.1 jmcneill #define GCC_SDCC4_AHB_CLK 145 158 1.1 jmcneill #define GCC_SDCC4_APPS_CLK 146 159 1.1 jmcneill #define GCC_SDCC4_APPS_CLK_SRC 147 160 1.1 jmcneill #define GCC_SYS_NOC_CPUSS_AHB_CLK 148 161 1.1 jmcneill #define GCC_TSIF_AHB_CLK 149 162 1.1 jmcneill #define GCC_TSIF_INACTIVITY_TIMERS_CLK 150 163 1.1 jmcneill #define GCC_TSIF_REF_CLK 151 164 1.1 jmcneill #define GCC_TSIF_REF_CLK_SRC 152 165 1.1 jmcneill #define GCC_UFS_CARD_2_AHB_CLK 153 166 1.1 jmcneill #define GCC_UFS_CARD_2_AXI_CLK 154 167 1.1 jmcneill #define GCC_UFS_CARD_2_AXI_CLK_SRC 155 168 1.1 jmcneill #define GCC_UFS_CARD_2_ICE_CORE_CLK 156 169 1.1 jmcneill #define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC 157 170 1.1 jmcneill #define GCC_UFS_CARD_2_PHY_AUX_CLK 158 171 1.1 jmcneill #define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC 159 172 1.1 jmcneill #define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK 160 173 1.1 jmcneill #define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK 161 174 1.1 jmcneill #define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK 162 175 1.1 jmcneill #define GCC_UFS_CARD_2_UNIPRO_CORE_CLK 163 176 1.1 jmcneill #define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC 164 177 1.1 jmcneill #define GCC_UFS_CARD_AHB_CLK 165 178 1.1 jmcneill #define GCC_UFS_CARD_AXI_CLK 166 179 1.1 jmcneill #define GCC_UFS_CARD_AXI_CLK_SRC 167 180 1.1 jmcneill #define GCC_UFS_CARD_AXI_HW_CTL_CLK 168 181 1.1 jmcneill #define GCC_UFS_CARD_ICE_CORE_CLK 169 182 1.1 jmcneill #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 170 183 1.1 jmcneill #define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 171 184 1.1 jmcneill #define GCC_UFS_CARD_PHY_AUX_CLK 172 185 1.1 jmcneill #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 173 186 1.1 jmcneill #define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 174 187 1.1 jmcneill #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 175 188 1.1 jmcneill #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 176 189 1.1 jmcneill #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 177 190 1.1 jmcneill #define GCC_UFS_CARD_UNIPRO_CORE_CLK 178 191 1.1 jmcneill #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 179 192 1.1 jmcneill #define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 180 193 1.1 jmcneill #define GCC_UFS_PHY_AHB_CLK 181 194 1.1 jmcneill #define GCC_UFS_PHY_AXI_CLK 182 195 1.1 jmcneill #define GCC_UFS_PHY_AXI_CLK_SRC 183 196 1.1 jmcneill #define GCC_UFS_PHY_AXI_HW_CTL_CLK 184 197 1.1 jmcneill #define GCC_UFS_PHY_ICE_CORE_CLK 185 198 1.1 jmcneill #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 186 199 1.1 jmcneill #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 187 200 1.1 jmcneill #define GCC_UFS_PHY_PHY_AUX_CLK 188 201 1.1 jmcneill #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 189 202 1.1 jmcneill #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 190 203 1.1 jmcneill #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 191 204 1.1 jmcneill #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 192 205 1.1 jmcneill #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 193 206 1.1 jmcneill #define GCC_UFS_PHY_UNIPRO_CORE_CLK 194 207 1.1 jmcneill #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 195 208 1.1 jmcneill #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 196 209 1.1 jmcneill #define GCC_USB30_MP_MASTER_CLK 197 210 1.1 jmcneill #define GCC_USB30_MP_MASTER_CLK_SRC 198 211 1.1 jmcneill #define GCC_USB30_MP_MOCK_UTMI_CLK 199 212 1.1 jmcneill #define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 200 213 1.1 jmcneill #define GCC_USB30_MP_SLEEP_CLK 201 214 1.1 jmcneill #define GCC_USB30_PRIM_MASTER_CLK 202 215 1.1 jmcneill #define GCC_USB30_PRIM_MASTER_CLK_SRC 203 216 1.1 jmcneill #define GCC_USB30_PRIM_MOCK_UTMI_CLK 204 217 1.1 jmcneill #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 205 218 1.1 jmcneill #define GCC_USB30_PRIM_SLEEP_CLK 206 219 1.1 jmcneill #define GCC_USB30_SEC_MASTER_CLK 207 220 1.1 jmcneill #define GCC_USB30_SEC_MASTER_CLK_SRC 208 221 1.1 jmcneill #define GCC_USB30_SEC_MOCK_UTMI_CLK 209 222 1.1 jmcneill #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 210 223 1.1 jmcneill #define GCC_USB30_SEC_SLEEP_CLK 211 224 1.1 jmcneill #define GCC_USB3_MP_PHY_AUX_CLK 212 225 1.1 jmcneill #define GCC_USB3_MP_PHY_AUX_CLK_SRC 213 226 1.1 jmcneill #define GCC_USB3_MP_PHY_COM_AUX_CLK 214 227 1.1 jmcneill #define GCC_USB3_MP_PHY_PIPE_0_CLK 215 228 1.1 jmcneill #define GCC_USB3_MP_PHY_PIPE_1_CLK 216 229 1.1 jmcneill #define GCC_USB3_PRIM_PHY_AUX_CLK 217 230 1.1 jmcneill #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 218 231 1.1 jmcneill #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 219 232 1.1 jmcneill #define GCC_USB3_PRIM_PHY_PIPE_CLK 220 233 1.1 jmcneill #define GCC_USB3_SEC_PHY_AUX_CLK 221 234 1.1 jmcneill #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 222 235 1.1 jmcneill #define GCC_USB3_SEC_PHY_COM_AUX_CLK 223 236 1.1 jmcneill #define GCC_USB3_SEC_PHY_PIPE_CLK 224 237 1.1 jmcneill #define GCC_VIDEO_AXI0_CLK 225 238 1.1 jmcneill #define GCC_VIDEO_AXI1_CLK 226 239 1.1 jmcneill #define GCC_VIDEO_AXIC_CLK 227 240 1.1 jmcneill #define GPLL0 228 241 1.1 jmcneill #define GPLL0_OUT_EVEN 229 242 1.1 jmcneill #define GPLL1 230 243 1.1 jmcneill #define GPLL4 231 244 1.1 jmcneill #define GPLL7 232 245 1.1 jmcneill #define GCC_PCIE_0_CLKREF_CLK 233 246 1.1 jmcneill #define GCC_PCIE_1_CLKREF_CLK 234 247 1.1 jmcneill #define GCC_PCIE_2_CLKREF_CLK 235 248 1.1 jmcneill #define GCC_PCIE_3_CLKREF_CLK 236 249 1.1 jmcneill #define GCC_USB3_PRIM_CLKREF_CLK 237 250 1.1 jmcneill #define GCC_USB3_SEC_CLKREF_CLK 238 251 1.1 jmcneill 252 1.1 jmcneill #define GCC_EMAC_BCR 0 253 1.1 jmcneill #define GCC_GPU_BCR 1 254 1.1 jmcneill #define GCC_MMSS_BCR 2 255 1.1 jmcneill #define GCC_NPU_BCR 3 256 1.1 jmcneill #define GCC_PCIE_0_BCR 4 257 1.1 jmcneill #define GCC_PCIE_0_PHY_BCR 5 258 1.1 jmcneill #define GCC_PCIE_1_BCR 6 259 1.1 jmcneill #define GCC_PCIE_1_PHY_BCR 7 260 1.1 jmcneill #define GCC_PCIE_2_BCR 8 261 1.1 jmcneill #define GCC_PCIE_2_PHY_BCR 9 262 1.1 jmcneill #define GCC_PCIE_3_BCR 10 263 1.1 jmcneill #define GCC_PCIE_3_PHY_BCR 11 264 1.1 jmcneill #define GCC_PCIE_PHY_BCR 12 265 1.1 jmcneill #define GCC_PDM_BCR 13 266 1.1 jmcneill #define GCC_PRNG_BCR 14 267 1.1 jmcneill #define GCC_QSPI_1_BCR 15 268 1.1 jmcneill #define GCC_QSPI_BCR 16 269 1.1 jmcneill #define GCC_QUPV3_WRAPPER_0_BCR 17 270 1.1 jmcneill #define GCC_QUPV3_WRAPPER_1_BCR 18 271 1.1 jmcneill #define GCC_QUPV3_WRAPPER_2_BCR 19 272 1.1 jmcneill #define GCC_QUSB2PHY_5_BCR 20 273 1.1 jmcneill #define GCC_QUSB2PHY_MP0_BCR 21 274 1.1 jmcneill #define GCC_QUSB2PHY_MP1_BCR 22 275 1.1 jmcneill #define GCC_QUSB2PHY_PRIM_BCR 23 276 1.1 jmcneill #define GCC_QUSB2PHY_SEC_BCR 24 277 1.1 jmcneill #define GCC_USB3_PHY_PRIM_SP0_BCR 25 278 1.1 jmcneill #define GCC_USB3_PHY_PRIM_SP1_BCR 26 279 1.1 jmcneill #define GCC_USB3_DP_PHY_PRIM_SP0_BCR 27 280 1.1 jmcneill #define GCC_USB3_DP_PHY_PRIM_SP1_BCR 28 281 1.1 jmcneill #define GCC_USB3_PHY_SEC_BCR 29 282 1.1 jmcneill #define GCC_USB3PHY_PHY_SEC_BCR 30 283 1.1 jmcneill #define GCC_SDCC2_BCR 31 284 1.1 jmcneill #define GCC_SDCC4_BCR 32 285 1.1 jmcneill #define GCC_TSIF_BCR 33 286 1.1 jmcneill #define GCC_UFS_CARD_2_BCR 34 287 1.1 jmcneill #define GCC_UFS_CARD_BCR 35 288 1.1 jmcneill #define GCC_UFS_PHY_BCR 36 289 1.1 jmcneill #define GCC_USB30_MP_BCR 37 290 1.1 jmcneill #define GCC_USB30_PRIM_BCR 38 291 1.1 jmcneill #define GCC_USB30_SEC_BCR 39 292 1.1 jmcneill #define GCC_USB_PHY_CFG_AHB2PHY_BCR 40 293 1.1 jmcneill #define GCC_VIDEO_AXIC_CLK_BCR 41 294 1.1 jmcneill #define GCC_VIDEO_AXI0_CLK_BCR 42 295 1.1 jmcneill #define GCC_VIDEO_AXI1_CLK_BCR 43 296 1.1 jmcneill #define GCC_USB3_DP_PHY_SEC_BCR 44 297 1.1 jmcneill 298 1.1 jmcneill /* GCC GDSCRs */ 299 1.1 jmcneill #define EMAC_GDSC 0 300 1.1 jmcneill #define PCIE_0_GDSC 1 301 1.1 jmcneill #define PCIE_1_GDSC 2 302 1.1 jmcneill #define PCIE_2_GDSC 3 303 1.1 jmcneill #define PCIE_3_GDSC 4 304 1.1 jmcneill #define UFS_CARD_2_GDSC 5 305 1.1 jmcneill #define UFS_CARD_GDSC 6 306 1.1 jmcneill #define UFS_PHY_GDSC 7 307 1.1 jmcneill #define USB30_MP_GDSC 8 308 1.1 jmcneill #define USB30_PRIM_GDSC 9 309 1.1 jmcneill #define USB30_SEC_GDSC 10 310 1.1 jmcneill 311 1.1 jmcneill #endif 312