Home | History | Annotate | Line # | Download | only in clock
      1  1.1  jmcneill /*	$NetBSD: qcom,gcc-sdx55.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4  1.1  jmcneill /*
      5  1.1  jmcneill  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
      6  1.1  jmcneill  * Copyright (c) 2020, Linaro Ltd.
      7  1.1  jmcneill  */
      8  1.1  jmcneill 
      9  1.1  jmcneill #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H
     10  1.1  jmcneill #define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H
     11  1.1  jmcneill 
     12  1.1  jmcneill #define GPLL0							3
     13  1.1  jmcneill #define GPLL0_OUT_EVEN						4
     14  1.1  jmcneill #define GPLL4							5
     15  1.1  jmcneill #define GPLL4_OUT_EVEN						6
     16  1.1  jmcneill #define GPLL5							7
     17  1.1  jmcneill #define GCC_AHB_PCIE_LINK_CLK					8
     18  1.1  jmcneill #define GCC_BLSP1_AHB_CLK					9
     19  1.1  jmcneill #define GCC_BLSP1_QUP1_I2C_APPS_CLK				10
     20  1.1  jmcneill #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC				11
     21  1.1  jmcneill #define GCC_BLSP1_QUP1_SPI_APPS_CLK				12
     22  1.1  jmcneill #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC				13
     23  1.1  jmcneill #define GCC_BLSP1_QUP2_I2C_APPS_CLK				14
     24  1.1  jmcneill #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC				15
     25  1.1  jmcneill #define GCC_BLSP1_QUP2_SPI_APPS_CLK				16
     26  1.1  jmcneill #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC				17
     27  1.1  jmcneill #define GCC_BLSP1_QUP3_I2C_APPS_CLK				18
     28  1.1  jmcneill #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC				19
     29  1.1  jmcneill #define GCC_BLSP1_QUP3_SPI_APPS_CLK				20
     30  1.1  jmcneill #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC				21
     31  1.1  jmcneill #define GCC_BLSP1_QUP4_I2C_APPS_CLK				22
     32  1.1  jmcneill #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC				23
     33  1.1  jmcneill #define GCC_BLSP1_QUP4_SPI_APPS_CLK				24
     34  1.1  jmcneill #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC				25
     35  1.1  jmcneill #define GCC_BLSP1_UART1_APPS_CLK				26
     36  1.1  jmcneill #define GCC_BLSP1_UART1_APPS_CLK_SRC				27
     37  1.1  jmcneill #define GCC_BLSP1_UART2_APPS_CLK				28
     38  1.1  jmcneill #define GCC_BLSP1_UART2_APPS_CLK_SRC				29
     39  1.1  jmcneill #define GCC_BLSP1_UART3_APPS_CLK				30
     40  1.1  jmcneill #define GCC_BLSP1_UART3_APPS_CLK_SRC				31
     41  1.1  jmcneill #define GCC_BLSP1_UART4_APPS_CLK				32
     42  1.1  jmcneill #define GCC_BLSP1_UART4_APPS_CLK_SRC				33
     43  1.1  jmcneill #define GCC_BOOT_ROM_AHB_CLK					34
     44  1.1  jmcneill #define GCC_CE1_AHB_CLK						35
     45  1.1  jmcneill #define GCC_CE1_AXI_CLK						36
     46  1.1  jmcneill #define GCC_CE1_CLK						37
     47  1.1  jmcneill #define GCC_CPUSS_AHB_CLK					38
     48  1.1  jmcneill #define GCC_CPUSS_AHB_CLK_SRC					39
     49  1.1  jmcneill #define GCC_CPUSS_GNOC_CLK					40
     50  1.1  jmcneill #define GCC_CPUSS_RBCPR_CLK					41
     51  1.1  jmcneill #define GCC_CPUSS_RBCPR_CLK_SRC					42
     52  1.1  jmcneill #define GCC_EMAC_CLK_SRC					43
     53  1.1  jmcneill #define GCC_EMAC_PTP_CLK_SRC					44
     54  1.1  jmcneill #define GCC_ETH_AXI_CLK						45
     55  1.1  jmcneill #define GCC_ETH_PTP_CLK						46
     56  1.1  jmcneill #define GCC_ETH_RGMII_CLK					47
     57  1.1  jmcneill #define GCC_ETH_SLAVE_AHB_CLK					48
     58  1.1  jmcneill #define GCC_GP1_CLK						49
     59  1.1  jmcneill #define GCC_GP1_CLK_SRC						50
     60  1.1  jmcneill #define GCC_GP2_CLK						51
     61  1.1  jmcneill #define GCC_GP2_CLK_SRC						52
     62  1.1  jmcneill #define GCC_GP3_CLK						53
     63  1.1  jmcneill #define GCC_GP3_CLK_SRC						54
     64  1.1  jmcneill #define GCC_PCIE_0_CLKREF_CLK					55
     65  1.1  jmcneill #define GCC_PCIE_AUX_CLK					56
     66  1.1  jmcneill #define GCC_PCIE_AUX_PHY_CLK_SRC				57
     67  1.1  jmcneill #define GCC_PCIE_CFG_AHB_CLK					58
     68  1.1  jmcneill #define GCC_PCIE_MSTR_AXI_CLK					59
     69  1.1  jmcneill #define GCC_PCIE_PIPE_CLK					60
     70  1.1  jmcneill #define GCC_PCIE_RCHNG_PHY_CLK					61
     71  1.1  jmcneill #define GCC_PCIE_RCHNG_PHY_CLK_SRC				62
     72  1.1  jmcneill #define GCC_PCIE_SLEEP_CLK					63
     73  1.1  jmcneill #define GCC_PCIE_SLV_AXI_CLK					64
     74  1.1  jmcneill #define GCC_PCIE_SLV_Q2A_AXI_CLK				65
     75  1.1  jmcneill #define GCC_PDM2_CLK						66
     76  1.1  jmcneill #define GCC_PDM2_CLK_SRC					67
     77  1.1  jmcneill #define GCC_PDM_AHB_CLK						68
     78  1.1  jmcneill #define GCC_PDM_XO4_CLK						69
     79  1.1  jmcneill #define GCC_SDCC1_AHB_CLK					70
     80  1.1  jmcneill #define GCC_SDCC1_APPS_CLK					71
     81  1.1  jmcneill #define GCC_SDCC1_APPS_CLK_SRC					72
     82  1.1  jmcneill #define GCC_SYS_NOC_CPUSS_AHB_CLK				73
     83  1.1  jmcneill #define GCC_USB30_MASTER_CLK					74
     84  1.1  jmcneill #define GCC_USB30_MASTER_CLK_SRC				75
     85  1.1  jmcneill #define GCC_USB30_MOCK_UTMI_CLK					76
     86  1.1  jmcneill #define GCC_USB30_MOCK_UTMI_CLK_SRC				77
     87  1.1  jmcneill #define GCC_USB30_MSTR_AXI_CLK					78
     88  1.1  jmcneill #define GCC_USB30_SLEEP_CLK					79
     89  1.1  jmcneill #define GCC_USB30_SLV_AHB_CLK					80
     90  1.1  jmcneill #define GCC_USB3_PHY_AUX_CLK					81
     91  1.1  jmcneill #define GCC_USB3_PHY_AUX_CLK_SRC				82
     92  1.1  jmcneill #define GCC_USB3_PHY_PIPE_CLK					83
     93  1.1  jmcneill #define GCC_USB3_PRIM_CLKREF_CLK				84
     94  1.1  jmcneill #define GCC_USB_PHY_CFG_AHB2PHY_CLK				85
     95  1.1  jmcneill #define GCC_XO_DIV4_CLK						86
     96  1.1  jmcneill #define GCC_XO_PCIE_LINK_CLK					87
     97  1.1  jmcneill 
     98  1.1  jmcneill #define GCC_EMAC_BCR						0
     99  1.1  jmcneill #define GCC_PCIE_BCR						1
    100  1.1  jmcneill #define GCC_PCIE_LINK_DOWN_BCR					2
    101  1.1  jmcneill #define GCC_PCIE_NOCSR_COM_PHY_BCR				3
    102  1.1  jmcneill #define GCC_PCIE_PHY_BCR					4
    103  1.1  jmcneill #define GCC_PCIE_PHY_CFG_AHB_BCR				5
    104  1.1  jmcneill #define GCC_PCIE_PHY_COM_BCR					6
    105  1.1  jmcneill #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				7
    106  1.1  jmcneill #define GCC_PDM_BCR						8
    107  1.1  jmcneill #define GCC_QUSB2PHY_BCR					9
    108  1.1  jmcneill #define GCC_TCSR_PCIE_BCR					10
    109  1.1  jmcneill #define GCC_USB30_BCR						11
    110  1.1  jmcneill #define GCC_USB3_PHY_BCR					12
    111  1.1  jmcneill #define GCC_USB3PHY_PHY_BCR					13
    112  1.1  jmcneill #define GCC_USB_PHY_CFG_AHB2PHY_BCR				14
    113  1.1  jmcneill 
    114  1.1  jmcneill /* GCC power domains */
    115  1.1  jmcneill #define USB30_GDSC						0
    116  1.1  jmcneill #define PCIE_GDSC						1
    117  1.1  jmcneill #define EMAC_GDSC						2
    118  1.1  jmcneill 
    119  1.1  jmcneill #endif
    120