11.1Sskrll/*	$NetBSD: qcom,ipq5332-gcc.h,v 1.1.1.1 2026/01/18 05:21:36 skrll Exp $	*/
21.1Sskrll
31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
41.1Sskrll/*
51.1Sskrll * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
61.1Sskrll */
71.1Sskrll
81.1Sskrll#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
91.1Sskrll#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
101.1Sskrll
111.1Sskrll#define GPLL0_MAIN					0
121.1Sskrll#define GPLL0						1
131.1Sskrll#define GPLL2_MAIN					2
141.1Sskrll#define GPLL2						3
151.1Sskrll#define GPLL4_MAIN					4
161.1Sskrll#define GPLL4						5
171.1Sskrll#define GCC_ADSS_PWM_CLK				6
181.1Sskrll#define GCC_ADSS_PWM_CLK_SRC				7
191.1Sskrll#define GCC_AHB_CLK					8
201.1Sskrll#define GCC_APSS_AXI_CLK_SRC				9
211.1Sskrll#define GCC_BLSP1_AHB_CLK				10
221.1Sskrll#define GCC_BLSP1_QUP1_I2C_APPS_CLK			11
231.1Sskrll#define GCC_BLSP1_QUP1_SPI_APPS_CLK			12
241.1Sskrll#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC			13
251.1Sskrll#define GCC_BLSP1_QUP2_I2C_APPS_CLK			14
261.1Sskrll#define GCC_BLSP1_QUP2_SPI_APPS_CLK			15
271.1Sskrll#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC			16
281.1Sskrll#define GCC_BLSP1_QUP3_I2C_APPS_CLK			17
291.1Sskrll#define GCC_BLSP1_QUP3_SPI_APPS_CLK			18
301.1Sskrll#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC			19
311.1Sskrll#define GCC_BLSP1_SLEEP_CLK				20
321.1Sskrll#define GCC_BLSP1_UART1_APPS_CLK			21
331.1Sskrll#define GCC_BLSP1_UART1_APPS_CLK_SRC			22
341.1Sskrll#define GCC_BLSP1_UART2_APPS_CLK			23
351.1Sskrll#define GCC_BLSP1_UART2_APPS_CLK_SRC			24
361.1Sskrll#define GCC_BLSP1_UART3_APPS_CLK			25
371.1Sskrll#define GCC_BLSP1_UART3_APPS_CLK_SRC			26
381.1Sskrll#define GCC_CE_AHB_CLK					27
391.1Sskrll#define GCC_CE_AXI_CLK					28
401.1Sskrll#define GCC_CE_PCNOC_AHB_CLK				29
411.1Sskrll#define GCC_CMN_12GPLL_AHB_CLK				30
421.1Sskrll#define GCC_CMN_12GPLL_APU_CLK				31
431.1Sskrll#define GCC_CMN_12GPLL_SYS_CLK				32
441.1Sskrll#define GCC_GP1_CLK					33
451.1Sskrll#define GCC_GP1_CLK_SRC					34
461.1Sskrll#define GCC_GP2_CLK					35
471.1Sskrll#define GCC_GP2_CLK_SRC					36
481.1Sskrll#define GCC_LPASS_CORE_AXIM_CLK				37
491.1Sskrll#define GCC_LPASS_SWAY_CLK				38
501.1Sskrll#define GCC_LPASS_SWAY_CLK_SRC				39
511.1Sskrll#define GCC_MDIO_AHB_CLK				40
521.1Sskrll#define GCC_MDIO_SLAVE_AHB_CLK				41
531.1Sskrll#define GCC_MEM_NOC_Q6_AXI_CLK				42
541.1Sskrll#define GCC_MEM_NOC_TS_CLK				43
551.1Sskrll#define GCC_NSS_TS_CLK					44
561.1Sskrll#define GCC_NSS_TS_CLK_SRC				45
571.1Sskrll#define GCC_NSSCC_CLK					46
581.1Sskrll#define GCC_NSSCFG_CLK					47
591.1Sskrll#define GCC_NSSNOC_ATB_CLK				48
601.1Sskrll#define GCC_NSSNOC_NSSCC_CLK				49
611.1Sskrll#define GCC_NSSNOC_QOSGEN_REF_CLK			50
621.1Sskrll#define GCC_NSSNOC_SNOC_1_CLK				51
631.1Sskrll#define GCC_NSSNOC_SNOC_CLK				52
641.1Sskrll#define GCC_NSSNOC_TIMEOUT_REF_CLK			53
651.1Sskrll#define GCC_NSSNOC_XO_DCD_CLK				54
661.1Sskrll#define GCC_PCIE3X1_0_AHB_CLK				55
671.1Sskrll#define GCC_PCIE3X1_0_AUX_CLK				56
681.1Sskrll#define GCC_PCIE3X1_0_AXI_CLK_SRC			57
691.1Sskrll#define GCC_PCIE3X1_0_AXI_M_CLK				58
701.1Sskrll#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK			59
711.1Sskrll#define GCC_PCIE3X1_0_AXI_S_CLK				60
721.1Sskrll#define GCC_PCIE3X1_0_PIPE_CLK				61
731.1Sskrll#define GCC_PCIE3X1_0_RCHG_CLK				62
741.1Sskrll#define GCC_PCIE3X1_0_RCHG_CLK_SRC			63
751.1Sskrll#define GCC_PCIE3X1_1_AHB_CLK				64
761.1Sskrll#define GCC_PCIE3X1_1_AUX_CLK				65
771.1Sskrll#define GCC_PCIE3X1_1_AXI_CLK_SRC			66
781.1Sskrll#define GCC_PCIE3X1_1_AXI_M_CLK				67
791.1Sskrll#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK			68
801.1Sskrll#define GCC_PCIE3X1_1_AXI_S_CLK				69
811.1Sskrll#define GCC_PCIE3X1_1_PIPE_CLK				70
821.1Sskrll#define GCC_PCIE3X1_1_RCHG_CLK				71
831.1Sskrll#define GCC_PCIE3X1_1_RCHG_CLK_SRC			72
841.1Sskrll#define GCC_PCIE3X1_PHY_AHB_CLK				73
851.1Sskrll#define GCC_PCIE3X2_AHB_CLK				74
861.1Sskrll#define GCC_PCIE3X2_AUX_CLK				75
871.1Sskrll#define GCC_PCIE3X2_AXI_M_CLK				76
881.1Sskrll#define GCC_PCIE3X2_AXI_M_CLK_SRC			77
891.1Sskrll#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK			78
901.1Sskrll#define GCC_PCIE3X2_AXI_S_CLK				79
911.1Sskrll#define GCC_PCIE3X2_AXI_S_CLK_SRC			80
921.1Sskrll#define GCC_PCIE3X2_PHY_AHB_CLK				81
931.1Sskrll#define GCC_PCIE3X2_PIPE_CLK				82
941.1Sskrll#define GCC_PCIE3X2_RCHG_CLK				83
951.1Sskrll#define GCC_PCIE3X2_RCHG_CLK_SRC			84
961.1Sskrll#define GCC_PCIE_AUX_CLK_SRC				85
971.1Sskrll#define GCC_PCNOC_AT_CLK				86
981.1Sskrll#define GCC_PCNOC_BFDCD_CLK_SRC				87
991.1Sskrll#define GCC_PCNOC_LPASS_CLK				88
1001.1Sskrll#define GCC_PRNG_AHB_CLK				89
1011.1Sskrll#define GCC_Q6_AHB_CLK					90
1021.1Sskrll#define GCC_Q6_AHB_S_CLK				91
1031.1Sskrll#define GCC_Q6_AXIM_CLK					92
1041.1Sskrll#define GCC_Q6_AXIM_CLK_SRC				93
1051.1Sskrll#define GCC_Q6_AXIS_CLK					94
1061.1Sskrll#define GCC_Q6_TSCTR_1TO2_CLK				95
1071.1Sskrll#define GCC_Q6SS_ATBM_CLK				96
1081.1Sskrll#define GCC_Q6SS_PCLKDBG_CLK				97
1091.1Sskrll#define GCC_Q6SS_TRIG_CLK				98
1101.1Sskrll#define GCC_QDSS_AT_CLK					99
1111.1Sskrll#define GCC_QDSS_AT_CLK_SRC				100
1121.1Sskrll#define GCC_QDSS_CFG_AHB_CLK				101
1131.1Sskrll#define GCC_QDSS_DAP_AHB_CLK				102
1141.1Sskrll#define GCC_QDSS_DAP_CLK				103
1151.1Sskrll#define GCC_QDSS_DAP_DIV_CLK_SRC			104
1161.1Sskrll#define GCC_QDSS_ETR_USB_CLK				105
1171.1Sskrll#define GCC_QDSS_EUD_AT_CLK				106
1181.1Sskrll#define GCC_QDSS_TSCTR_CLK_SRC				107
1191.1Sskrll#define GCC_QPIC_AHB_CLK				108
1201.1Sskrll#define GCC_QPIC_CLK					109
1211.1Sskrll#define GCC_QPIC_IO_MACRO_CLK				110
1221.1Sskrll#define GCC_QPIC_IO_MACRO_CLK_SRC			111
1231.1Sskrll#define GCC_QPIC_SLEEP_CLK				112
1241.1Sskrll#define GCC_SDCC1_AHB_CLK				113
1251.1Sskrll#define GCC_SDCC1_APPS_CLK				114
1261.1Sskrll#define GCC_SDCC1_APPS_CLK_SRC				115
1271.1Sskrll#define GCC_SLEEP_CLK_SRC				116
1281.1Sskrll#define GCC_SNOC_LPASS_CFG_CLK				117
1291.1Sskrll#define GCC_SNOC_NSSNOC_1_CLK				118
1301.1Sskrll#define GCC_SNOC_NSSNOC_CLK				119
1311.1Sskrll#define GCC_SNOC_PCIE3_1LANE_1_M_CLK			120
1321.1Sskrll#define GCC_SNOC_PCIE3_1LANE_1_S_CLK			121
1331.1Sskrll#define GCC_SNOC_PCIE3_1LANE_M_CLK			122
1341.1Sskrll#define GCC_SNOC_PCIE3_1LANE_S_CLK			123
1351.1Sskrll#define GCC_SNOC_PCIE3_2LANE_M_CLK			124
1361.1Sskrll#define GCC_SNOC_PCIE3_2LANE_S_CLK			125
1371.1Sskrll#define GCC_SNOC_USB_CLK				126
1381.1Sskrll#define GCC_SYS_NOC_AT_CLK				127
1391.1Sskrll#define GCC_SYS_NOC_WCSS_AHB_CLK			128
1401.1Sskrll#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC			129
1411.1Sskrll#define GCC_UNIPHY0_AHB_CLK				130
1421.1Sskrll#define GCC_UNIPHY0_SYS_CLK				131
1431.1Sskrll#define GCC_UNIPHY1_AHB_CLK				132
1441.1Sskrll#define GCC_UNIPHY1_SYS_CLK				133
1451.1Sskrll#define GCC_UNIPHY_SYS_CLK_SRC				134
1461.1Sskrll#define GCC_USB0_AUX_CLK				135
1471.1Sskrll#define GCC_USB0_AUX_CLK_SRC				136
1481.1Sskrll#define GCC_USB0_EUD_AT_CLK				137
1491.1Sskrll#define GCC_USB0_LFPS_CLK				138
1501.1Sskrll#define GCC_USB0_LFPS_CLK_SRC				139
1511.1Sskrll#define GCC_USB0_MASTER_CLK				140
1521.1Sskrll#define GCC_USB0_MASTER_CLK_SRC				141
1531.1Sskrll#define GCC_USB0_MOCK_UTMI_CLK				142
1541.1Sskrll#define GCC_USB0_MOCK_UTMI_CLK_SRC			143
1551.1Sskrll#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC			144
1561.1Sskrll#define GCC_USB0_PHY_CFG_AHB_CLK			145
1571.1Sskrll#define GCC_USB0_PIPE_CLK				146
1581.1Sskrll#define GCC_USB0_SLEEP_CLK				147
1591.1Sskrll#define GCC_WCSS_AHB_CLK_SRC				148
1601.1Sskrll#define GCC_WCSS_AXIM_CLK				149
1611.1Sskrll#define GCC_WCSS_AXIS_CLK				150
1621.1Sskrll#define GCC_WCSS_DBG_IFC_APB_BDG_CLK			151
1631.1Sskrll#define GCC_WCSS_DBG_IFC_APB_CLK			152
1641.1Sskrll#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK			153
1651.1Sskrll#define GCC_WCSS_DBG_IFC_ATB_CLK			154
1661.1Sskrll#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK			155
1671.1Sskrll#define GCC_WCSS_DBG_IFC_NTS_CLK			156
1681.1Sskrll#define GCC_WCSS_ECAHB_CLK				157
1691.1Sskrll#define GCC_WCSS_MST_ASYNC_BDG_CLK			158
1701.1Sskrll#define GCC_WCSS_SLV_ASYNC_BDG_CLK			159
1711.1Sskrll#define GCC_XO_CLK					160
1721.1Sskrll#define GCC_XO_CLK_SRC					161
1731.1Sskrll#define GCC_XO_DIV4_CLK					162
1741.1Sskrll#define GCC_IM_SLEEP_CLK				163
1751.1Sskrll#define GCC_NSSNOC_PCNOC_1_CLK				164
1761.1Sskrll#define GCC_MEM_NOC_AHB_CLK				165
1771.1Sskrll#define GCC_MEM_NOC_APSS_AXI_CLK			166
1781.1Sskrll#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC		167
1791.1Sskrll#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK			168
1801.1Sskrll#define GCC_PCIE3X2_PIPE_CLK_SRC			169
1811.1Sskrll#define GCC_PCIE3X1_0_PIPE_CLK_SRC			170
1821.1Sskrll#define GCC_PCIE3X1_1_PIPE_CLK_SRC			171
1831.1Sskrll#define GCC_USB0_PIPE_CLK_SRC				172
1841.1Sskrll
1851.1Sskrll#define GCC_ADSS_BCR					0
1861.1Sskrll#define GCC_ADSS_PWM_CLK_ARES				1
1871.1Sskrll#define GCC_AHB_CLK_ARES				2
1881.1Sskrll#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR		3
1891.1Sskrll#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES	4
1901.1Sskrll#define GCC_APSS_AHB_CLK_ARES				5
1911.1Sskrll#define GCC_APSS_AXI_CLK_ARES				6
1921.1Sskrll#define GCC_BLSP1_AHB_CLK_ARES				7
1931.1Sskrll#define GCC_BLSP1_BCR					8
1941.1Sskrll#define GCC_BLSP1_QUP1_BCR				9
1951.1Sskrll#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES		10
1961.1Sskrll#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES		11
1971.1Sskrll#define GCC_BLSP1_QUP2_BCR				12
1981.1Sskrll#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES		13
1991.1Sskrll#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES		14
2001.1Sskrll#define GCC_BLSP1_QUP3_BCR				15
2011.1Sskrll#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES		16
2021.1Sskrll#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES		17
2031.1Sskrll#define GCC_BLSP1_SLEEP_CLK_ARES			18
2041.1Sskrll#define GCC_BLSP1_UART1_APPS_CLK_ARES			19
2051.1Sskrll#define GCC_BLSP1_UART1_BCR				20
2061.1Sskrll#define GCC_BLSP1_UART2_APPS_CLK_ARES			21
2071.1Sskrll#define GCC_BLSP1_UART2_BCR				22
2081.1Sskrll#define GCC_BLSP1_UART3_APPS_CLK_ARES			23
2091.1Sskrll#define GCC_BLSP1_UART3_BCR				24
2101.1Sskrll#define GCC_CE_BCR					25
2111.1Sskrll#define GCC_CMN_BLK_BCR					26
2121.1Sskrll#define GCC_CMN_LDO0_BCR				27
2131.1Sskrll#define GCC_CMN_LDO1_BCR				28
2141.1Sskrll#define GCC_DCC_BCR					29
2151.1Sskrll#define GCC_GP1_CLK_ARES				30
2161.1Sskrll#define GCC_GP2_CLK_ARES				31
2171.1Sskrll#define GCC_LPASS_BCR					32
2181.1Sskrll#define GCC_LPASS_CORE_AXIM_CLK_ARES			33
2191.1Sskrll#define GCC_LPASS_SWAY_CLK_ARES				34
2201.1Sskrll#define GCC_MDIOM_BCR					35
2211.1Sskrll#define GCC_MDIOS_BCR					36
2221.1Sskrll#define GCC_NSS_BCR					37
2231.1Sskrll#define GCC_NSS_TS_CLK_ARES				38
2241.1Sskrll#define GCC_NSSCC_CLK_ARES				39
2251.1Sskrll#define GCC_NSSCFG_CLK_ARES				40
2261.1Sskrll#define GCC_NSSNOC_ATB_CLK_ARES				41
2271.1Sskrll#define GCC_NSSNOC_NSSCC_CLK_ARES			42
2281.1Sskrll#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES			43
2291.1Sskrll#define GCC_NSSNOC_SNOC_1_CLK_ARES			44
2301.1Sskrll#define GCC_NSSNOC_SNOC_CLK_ARES			45
2311.1Sskrll#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES			46
2321.1Sskrll#define GCC_NSSNOC_XO_DCD_CLK_ARES			47
2331.1Sskrll#define GCC_PCIE3X1_0_AHB_CLK_ARES			48
2341.1Sskrll#define GCC_PCIE3X1_0_AUX_CLK_ARES			49
2351.1Sskrll#define GCC_PCIE3X1_0_AXI_M_CLK_ARES			50
2361.1Sskrll#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES		51
2371.1Sskrll#define GCC_PCIE3X1_0_AXI_S_CLK_ARES			52
2381.1Sskrll#define GCC_PCIE3X1_0_BCR				53
2391.1Sskrll#define GCC_PCIE3X1_0_LINK_DOWN_BCR			54
2401.1Sskrll#define GCC_PCIE3X1_0_PHY_BCR				55
2411.1Sskrll#define GCC_PCIE3X1_0_PHY_PHY_BCR			56
2421.1Sskrll#define GCC_PCIE3X1_1_AHB_CLK_ARES			57
2431.1Sskrll#define GCC_PCIE3X1_1_AUX_CLK_ARES			58
2441.1Sskrll#define GCC_PCIE3X1_1_AXI_M_CLK_ARES			59
2451.1Sskrll#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES		60
2461.1Sskrll#define GCC_PCIE3X1_1_AXI_S_CLK_ARES			61
2471.1Sskrll#define GCC_PCIE3X1_1_BCR				62
2481.1Sskrll#define GCC_PCIE3X1_1_LINK_DOWN_BCR			63
2491.1Sskrll#define GCC_PCIE3X1_1_PHY_BCR				64
2501.1Sskrll#define GCC_PCIE3X1_1_PHY_PHY_BCR			65
2511.1Sskrll#define GCC_PCIE3X1_PHY_AHB_CLK_ARES			66
2521.1Sskrll#define GCC_PCIE3X2_AHB_CLK_ARES			67
2531.1Sskrll#define GCC_PCIE3X2_AUX_CLK_ARES			68
2541.1Sskrll#define GCC_PCIE3X2_AXI_M_CLK_ARES			69
2551.1Sskrll#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES		70
2561.1Sskrll#define GCC_PCIE3X2_AXI_S_CLK_ARES			71
2571.1Sskrll#define GCC_PCIE3X2_BCR					72
2581.1Sskrll#define GCC_PCIE3X2_LINK_DOWN_BCR			73
2591.1Sskrll#define GCC_PCIE3X2_PHY_AHB_CLK_ARES			74
2601.1Sskrll#define GCC_PCIE3X2_PHY_BCR				75
2611.1Sskrll#define GCC_PCIE3X2PHY_PHY_BCR				76
2621.1Sskrll#define GCC_PCNOC_BCR					77
2631.1Sskrll#define GCC_PCNOC_LPASS_CLK_ARES			78
2641.1Sskrll#define GCC_PRNG_AHB_CLK_ARES				79
2651.1Sskrll#define GCC_PRNG_BCR					80
2661.1Sskrll#define GCC_Q6_AHB_CLK_ARES				81
2671.1Sskrll#define GCC_Q6_AHB_S_CLK_ARES				82
2681.1Sskrll#define GCC_Q6_AXIM_CLK_ARES				83
2691.1Sskrll#define GCC_Q6_AXIS_CLK_ARES				84
2701.1Sskrll#define GCC_Q6_TSCTR_1TO2_CLK_ARES			85
2711.1Sskrll#define GCC_Q6SS_ATBM_CLK_ARES				86
2721.1Sskrll#define GCC_Q6SS_PCLKDBG_CLK_ARES			87
2731.1Sskrll#define GCC_Q6SS_TRIG_CLK_ARES				88
2741.1Sskrll#define GCC_QDSS_APB2JTAG_CLK_ARES			89
2751.1Sskrll#define GCC_QDSS_AT_CLK_ARES				90
2761.1Sskrll#define GCC_QDSS_BCR					91
2771.1Sskrll#define GCC_QDSS_CFG_AHB_CLK_ARES			92
2781.1Sskrll#define GCC_QDSS_DAP_AHB_CLK_ARES			93
2791.1Sskrll#define GCC_QDSS_DAP_CLK_ARES				94
2801.1Sskrll#define GCC_QDSS_ETR_USB_CLK_ARES			95
2811.1Sskrll#define GCC_QDSS_EUD_AT_CLK_ARES			96
2821.1Sskrll#define GCC_QDSS_STM_CLK_ARES				97
2831.1Sskrll#define GCC_QDSS_TRACECLKIN_CLK_ARES			98
2841.1Sskrll#define GCC_QDSS_TS_CLK_ARES				99
2851.1Sskrll#define GCC_QDSS_TSCTR_DIV16_CLK_ARES			100
2861.1Sskrll#define GCC_QDSS_TSCTR_DIV2_CLK_ARES			101
2871.1Sskrll#define GCC_QDSS_TSCTR_DIV3_CLK_ARES			102
2881.1Sskrll#define GCC_QDSS_TSCTR_DIV4_CLK_ARES			103
2891.1Sskrll#define GCC_QDSS_TSCTR_DIV8_CLK_ARES			104
2901.1Sskrll#define GCC_QPIC_AHB_CLK_ARES				105
2911.1Sskrll#define GCC_QPIC_CLK_ARES				106
2921.1Sskrll#define GCC_QPIC_BCR					107
2931.1Sskrll#define GCC_QPIC_IO_MACRO_CLK_ARES			108
2941.1Sskrll#define GCC_QPIC_SLEEP_CLK_ARES				109
2951.1Sskrll#define GCC_QUSB2_0_PHY_BCR				110
2961.1Sskrll#define GCC_SDCC1_AHB_CLK_ARES				111
2971.1Sskrll#define GCC_SDCC1_APPS_CLK_ARES				112
2981.1Sskrll#define GCC_SDCC_BCR					113
2991.1Sskrll#define GCC_SNOC_BCR					114
3001.1Sskrll#define GCC_SNOC_LPASS_CFG_CLK_ARES			115
3011.1Sskrll#define GCC_SNOC_NSSNOC_1_CLK_ARES			116
3021.1Sskrll#define GCC_SNOC_NSSNOC_CLK_ARES			117
3031.1Sskrll#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES		118
3041.1Sskrll#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES			119
3051.1Sskrll#define GCC_UNIPHY0_AHB_CLK_ARES			120
3061.1Sskrll#define GCC_UNIPHY0_BCR					121
3071.1Sskrll#define GCC_UNIPHY0_SYS_CLK_ARES			122
3081.1Sskrll#define GCC_UNIPHY1_AHB_CLK_ARES			123
3091.1Sskrll#define GCC_UNIPHY1_BCR					124
3101.1Sskrll#define GCC_UNIPHY1_SYS_CLK_ARES			125
3111.1Sskrll#define GCC_USB0_AUX_CLK_ARES				126
3121.1Sskrll#define GCC_USB0_EUD_AT_CLK_ARES			127
3131.1Sskrll#define GCC_USB0_LFPS_CLK_ARES				128
3141.1Sskrll#define GCC_USB0_MASTER_CLK_ARES			129
3151.1Sskrll#define GCC_USB0_MOCK_UTMI_CLK_ARES			130
3161.1Sskrll#define GCC_USB0_PHY_BCR				131
3171.1Sskrll#define GCC_USB0_PHY_CFG_AHB_CLK_ARES			132
3181.1Sskrll#define GCC_USB0_SLEEP_CLK_ARES				133
3191.1Sskrll#define GCC_USB3PHY_0_PHY_BCR				134
3201.1Sskrll#define GCC_USB_BCR					135
3211.1Sskrll#define GCC_WCSS_AXIM_CLK_ARES				136
3221.1Sskrll#define GCC_WCSS_AXIS_CLK_ARES				137
3231.1Sskrll#define GCC_WCSS_BCR					138
3241.1Sskrll#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES		139
3251.1Sskrll#define GCC_WCSS_DBG_IFC_APB_CLK_ARES			140
3261.1Sskrll#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES		141
3271.1Sskrll#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES			142
3281.1Sskrll#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES		143
3291.1Sskrll#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES			144
3301.1Sskrll#define GCC_WCSS_ECAHB_CLK_ARES				145
3311.1Sskrll#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES			146
3321.1Sskrll#define GCC_WCSS_Q6_BCR					147
3331.1Sskrll#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES			148
3341.1Sskrll#define GCC_XO_CLK_ARES					149
3351.1Sskrll#define GCC_XO_DIV4_CLK_ARES				150
3361.1Sskrll#define GCC_Q6SS_DBG_ARES				151
3371.1Sskrll#define GCC_WCSS_DBG_BDG_ARES				152
3381.1Sskrll#define GCC_WCSS_DBG_ARES				153
3391.1Sskrll#define GCC_WCSS_AXI_S_ARES				154
3401.1Sskrll#define GCC_WCSS_AXI_M_ARES				155
3411.1Sskrll#define GCC_WCSSAON_ARES				156
3421.1Sskrll#define GCC_PCIE3X2_PIPE_ARES				157
3431.1Sskrll#define GCC_PCIE3X2_CORE_STICKY_ARES			158
3441.1Sskrll#define GCC_PCIE3X2_AXI_S_STICKY_ARES			159
3451.1Sskrll#define GCC_PCIE3X2_AXI_M_STICKY_ARES			160
3461.1Sskrll#define GCC_PCIE3X1_0_PIPE_ARES				161
3471.1Sskrll#define GCC_PCIE3X1_0_CORE_STICKY_ARES			162
3481.1Sskrll#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES			163
3491.1Sskrll#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES			164
3501.1Sskrll#define GCC_PCIE3X1_1_PIPE_ARES				165
3511.1Sskrll#define GCC_PCIE3X1_1_CORE_STICKY_ARES			166
3521.1Sskrll#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES			167
3531.1Sskrll#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES			168
3541.1Sskrll#define GCC_IM_SLEEP_CLK_ARES				169
3551.1Sskrll#define GCC_NSSNOC_PCNOC_1_CLK_ARES			170
3561.1Sskrll#define GCC_UNIPHY0_XPCS_ARES				171
3571.1Sskrll#define GCC_UNIPHY1_XPCS_ARES				172
3581.1Sskrll#endif
359